1 /****************************************************************************** 2 * @file clock_update.c 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 // Include Files 31 32 #include "clock_update.h" 33 #include "rsi_pll.h" 34 #include "rsi_power_save.h" 35 #include "rsi_ulpss_clk.h" 36 37 #ifdef __SYSTICK 38 volatile uint32_t _dwTickCount = 0; 39 40 /** @addtogroup SOC2 41 * @{ 42 */ 43 /*==============================================*/ 44 /** 45 * @fn void SysTick_Handler(void) 46 * @brief Systic handler use for generation delay for XTAL clock enable 47 * @return None 48 */ SysTick_Handler(void)49void SysTick_Handler(void) 50 { 51 _dwTickCount++; 52 } 53 54 /*==============================================*/ 55 /** 56 * @fn uint32_t GetTickCount(void) 57 * @brief Get tick count. 58 * @return return the count of tick. 59 */ GetTickCount(void)60uint32_t GetTickCount(void) 61 { 62 /*gets the tick count from systic ISR */ 63 return _dwTickCount; 64 } 65 66 /*==============================================*/ 67 /** 68 * @fn void rsi_delay_ms(uint32_t val) 69 * @brief This callback function for generation delay for XTAL clock. 70 * @param[in] Number of delay in us. 71 * @return None. 72 */ rsi_delay_ms(uint32_t val)73void rsi_delay_ms(uint32_t val) 74 { 75 uint32_t start = 0; 76 77 start = GetTickCount(); 78 do { 79 } while (GetTickCount() - start < val); 80 81 return; 82 } 83 #endif 84 // It will gets the clock of each peripheral 85 86 /*==============================================*/ 87 /** 88 * @fn uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) 89 * @brief gets the clock of each peripheral 90 * @param[in] peri_src 91 * @return src_clk 92 */ RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src)93uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) 94 { 95 uint32_t src_clk_mux = 0; 96 uint32_t src_clk = 0; 97 uint32_t div_fac = 0; 98 uint32_t swallow_val = 0; 99 uint32_t odd_div = 0; 100 switch (peri_src) { 101 case M4_USART0: 102 // Read the ULP UART clock mux 103 src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL; 104 switch (src_clk_mux) { 105 case USART_ULPREFCLK: 106 switch (system_clocks.m4_ref_clock_source) { 107 case ULPSS_REF_BYP_CLK: 108 src_clk = system_clocks.byp_rc_ref_clock; 109 break; 110 case ULPSS_ULP_MHZ_RC_CLK: 111 src_clk = system_clocks.rc_mhz_clock; 112 break; 113 case ULPSS_40MHZ_CLK: 114 src_clk = system_clocks.rf_ref_clock; 115 break; 116 case ULPSS_MEMS_REF_CLK: 117 src_clk = system_clocks.rc_mhz_clock; 118 break; 119 case ULPSS_ULP_20MHZ_RINGOSC_CLK: 120 src_clk = system_clocks.ro_20mhz_clock; 121 break; 122 case ULPSS_ULP_DOUBLER_CLK: 123 src_clk = system_clocks.doubler_clock; 124 break; 125 default: 126 break; 127 } 128 break; 129 case USART_MODELPLLCLK2: 130 src_clk = system_clocks.modem_pll_clock2; 131 break; 132 case USART_INTFPLLCLK: 133 src_clk = system_clocks.intf_pll_clock; 134 break; 135 case USART_SOCPLLCLK: 136 src_clk = system_clocks.soc_pll_clock; 137 break; 138 case M4_SOCCLKFOROTHERCLOCKS: 139 src_clk = system_clocks.soc_clock; 140 break; 141 default: 142 break; 143 } 144 div_fac = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC; 145 swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL; 146 if (swallow_val) { 147 if (div_fac == 0) { 148 break; // Clock is gated 149 } else { 150 src_clk = (uint32_t)(src_clk / (div_fac + 0.5)); 151 } 152 } else { 153 if (div_fac == 0) { 154 return src_clk; //divider bypassed 155 } else { 156 src_clk = src_clk / div_fac; 157 } 158 } 159 break; 160 161 case M4_UART1: 162 src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL; 163 switch (src_clk_mux) { 164 case USART_ULPREFCLK: 165 switch (system_clocks.m4_ref_clock_source) { 166 case ULPSS_REF_BYP_CLK: 167 src_clk = system_clocks.byp_rc_ref_clock; 168 break; 169 case ULPSS_ULP_MHZ_RC_CLK: 170 src_clk = system_clocks.rc_mhz_clock; 171 break; 172 case ULPSS_40MHZ_CLK: 173 src_clk = system_clocks.rf_ref_clock; 174 break; 175 case ULPSS_MEMS_REF_CLK: 176 src_clk = system_clocks.rc_mhz_clock; 177 break; 178 case ULPSS_ULP_20MHZ_RINGOSC_CLK: 179 src_clk = system_clocks.ro_20mhz_clock; 180 break; 181 case ULPSS_ULP_DOUBLER_CLK: 182 src_clk = system_clocks.doubler_clock; 183 break; 184 default: 185 break; 186 } 187 break; 188 case USART_MODELPLLCLK2: 189 src_clk = system_clocks.modem_pll_clock2; 190 break; 191 case USART_INTFPLLCLK: 192 src_clk = system_clocks.intf_pll_clock; 193 break; 194 case USART_SOCPLLCLK: 195 src_clk = system_clocks.soc_pll_clock; 196 break; 197 case M4_SOCCLKFOROTHERCLOCKS: 198 src_clk = system_clocks.soc_clock; 199 break; 200 default: 201 break; 202 } 203 div_fac = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC; 204 swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL; 205 if (swallow_val) { 206 if (div_fac == 0) { 207 break; // Clock is gated 208 } else { 209 src_clk = (uint32_t)(src_clk / (div_fac + 0.5)); 210 } 211 } else { 212 if (div_fac == 0) { 213 return src_clk; //divider bypassed 214 } else { 215 src_clk = src_clk / div_fac; 216 } 217 } 218 break; 219 220 case M4_SSI_MST: 221 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL; 222 switch (src_clk_mux) { 223 case SSI_ULPREFCLK: 224 switch (system_clocks.m4_ref_clock_source) { 225 case ULPSS_REF_BYP_CLK: 226 src_clk = system_clocks.byp_rc_ref_clock; 227 break; 228 case ULPSS_ULP_MHZ_RC_CLK: 229 src_clk = system_clocks.rc_mhz_clock; 230 break; 231 case ULPSS_40MHZ_CLK: 232 src_clk = system_clocks.rf_ref_clock; 233 break; 234 case ULPSS_MEMS_REF_CLK: 235 src_clk = system_clocks.rc_mhz_clock; 236 break; 237 case ULPSS_ULP_20MHZ_RINGOSC_CLK: 238 src_clk = system_clocks.ro_20mhz_clock; 239 break; 240 case ULPSS_ULP_DOUBLER_CLK: 241 src_clk = system_clocks.doubler_clock; 242 break; 243 default: 244 break; 245 } 246 break; 247 case SSI_SOCPLLCLK: 248 src_clk = system_clocks.soc_pll_clock; 249 break; 250 case SSI_MODEMPLLCLK1: 251 src_clk = system_clocks.modem_pll_clock; 252 break; 253 case SSI_INTFPLLCLK: 254 src_clk = system_clocks.intf_pll_clock; 255 break; 256 case SSI_MODELPLLCLK2: 257 src_clk = system_clocks.modem_pll_clock2; 258 break; 259 case M4_SOCCLKFOROTHERCLKS: 260 src_clk = system_clocks.soc_clock; 261 break; 262 default: 263 break; 264 } 265 div_fac = (M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC); 266 if (div_fac == 0) { 267 return src_clk; 268 } else { 269 src_clk = (src_clk / div_fac); 270 } 271 break; 272 273 case M4_CT: 274 src_clk_mux = M4CLK->CLK_CONFIG_REG5_b.CT_CLK_SEL; 275 switch (src_clk_mux) { 276 case CT_ULPREFCLK: 277 switch (system_clocks.m4_ref_clock_source) { 278 case ULPSS_REF_BYP_CLK: 279 src_clk = system_clocks.byp_rc_ref_clock; 280 break; 281 case ULPSS_ULP_MHZ_RC_CLK: 282 src_clk = system_clocks.rc_mhz_clock; 283 break; 284 case ULPSS_40MHZ_CLK: 285 src_clk = system_clocks.rf_ref_clock; 286 break; 287 case ULPSS_MEMS_REF_CLK: 288 src_clk = system_clocks.rc_mhz_clock; 289 break; 290 case ULPSS_ULP_20MHZ_RINGOSC_CLK: 291 src_clk = system_clocks.ro_20mhz_clock; 292 break; 293 case ULPSS_ULP_DOUBLER_CLK: 294 src_clk = system_clocks.doubler_clock; 295 break; 296 default: 297 break; 298 } 299 break; 300 case CT_INTFPLLCLK: 301 src_clk = system_clocks.intf_pll_clock; 302 break; 303 case CT_SOCPLLCLK: 304 src_clk = system_clocks.soc_pll_clock; 305 break; 306 case M4_SOCCLKFOROTHERCLKSCT: 307 src_clk = system_clocks.soc_clock; 308 break; 309 default: 310 break; 311 } 312 div_fac = (M4CLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC); 313 if (div_fac == 0) { 314 return src_clk; 315 } else { 316 src_clk = (src_clk / (2 * div_fac)); 317 } 318 break; 319 #if !defined(SLI_SI917) && !defined(SLI_SI915) 320 case M4_SD_MEM: 321 src_clk_mux = M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL; 322 switch (src_clk_mux) { 323 case SDMEM_SOCPLLCLK: 324 src_clk = system_clocks.soc_pll_clock; 325 break; 326 case SDMEM_MODEMPLLCLK1: 327 src_clk = system_clocks.modem_pll_clock2; 328 break; 329 case SDMEM_INTFPLLCLK: 330 src_clk = system_clocks.intf_pll_clock; 331 break; 332 case M4_SOCCLKFOROTHERCLKSSDMEM: 333 src_clk = system_clocks.soc_clock; 334 break; 335 default: 336 break; 337 } 338 swallow_val = M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL; 339 div_fac = (M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC); 340 if (swallow_val) { 341 if (div_fac == 0) { 342 return src_clk; 343 } else { 344 src_clk = (src_clk / div_fac); 345 } 346 } else { 347 if (div_fac == 0) { 348 src_clk = (src_clk / 2); //divider bypassed 349 } else { 350 src_clk = (src_clk / (2 * div_fac)); 351 } 352 } 353 break; 354 355 case M4_CCI: 356 src_clk_mux = M4CLK->CLK_CONFIG_REG4_b.CCI_CLK_SEL; 357 switch (src_clk_mux) { 358 case CCI_M4_SOC_CLK_FOR_OTHER_CLKS: 359 src_clk = system_clocks.soc_clock; 360 break; 361 case CCI_INTF_PLL_CLK: 362 src_clk = system_clocks.intf_pll_clock; 363 break; 364 default: 365 break; 366 } 367 div_fac = (M4CLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC); 368 if (div_fac == 0) { 369 return src_clk; 370 } else { 371 src_clk = (src_clk / (2 * div_fac)); 372 } 373 break; 374 #endif 375 case M4_QSPI: 376 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL; 377 switch (src_clk_mux) { 378 case QSPI_ULPREFCLK: 379 src_clk = system_clocks.rc_mhz_clock; 380 break; 381 case QSPI_MODELPLLCLK2: 382 src_clk = system_clocks.modem_pll_clock2; 383 break; 384 case QSPI_INTFPLLCLK: 385 src_clk = system_clocks.intf_pll_clock; 386 break; 387 case QSPI_SOCPLLCLK: 388 src_clk = system_clocks.soc_pll_clock; 389 break; 390 case M4_SOCCLKNOSWLSYNCCLKTREEGATED: 391 break; 392 default: 393 break; 394 } 395 swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); 396 div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); 397 odd_div = (M4CLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL); 398 if (swallow_val) { 399 if (odd_div == 0) { 400 if (div_fac == 0) { 401 return src_clk; 402 } else { 403 src_clk = (src_clk / div_fac); 404 } 405 } else { 406 if ((div_fac % 2 != 0) && (div_fac >= 3)) { 407 src_clk = (src_clk / div_fac); 408 } else { 409 break; //clock gated 410 } 411 } 412 } else { 413 if (odd_div == 0) { 414 if (div_fac == 0) { 415 src_clk = (src_clk / 2); 416 } else { 417 src_clk = (src_clk / (2 * div_fac)); 418 } 419 } else { 420 if ((div_fac % 2 != 0) && (div_fac >= 3)) { 421 src_clk = (src_clk / div_fac); 422 } else { 423 break; //clock gated 424 } 425 } 426 } 427 break; 428 429 case M4_QSPI2: 430 src_clk_mux = M4CLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL; 431 switch (src_clk_mux) { 432 case QSPI_ULPREFCLK: 433 src_clk = system_clocks.rc_mhz_clock; 434 break; 435 case QSPI_MODELPLLCLK2: 436 src_clk = system_clocks.modem_pll_clock2; 437 break; 438 case QSPI_INTFPLLCLK: 439 src_clk = system_clocks.intf_pll_clock; 440 break; 441 case QSPI_SOCPLLCLK: 442 src_clk = system_clocks.soc_pll_clock; 443 break; 444 case M4_SOCCLKNOSWLSYNCCLKTREEGATED: 445 break; 446 default: 447 break; 448 } 449 swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); 450 div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); 451 odd_div = (M4CLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL); 452 if (swallow_val) { 453 if (odd_div == 0) { 454 if (div_fac == 0) { 455 return src_clk; 456 } else { 457 src_clk = (src_clk / div_fac); 458 } 459 } else { 460 if ((div_fac % 2 != 0) && (div_fac >= 3)) { 461 src_clk = (src_clk / div_fac); 462 } else { 463 break; //clock gated 464 } 465 } 466 } else { 467 if (odd_div == 0) { 468 if (div_fac == 0) { 469 src_clk = (src_clk / 2); 470 } else { 471 src_clk = (src_clk / (2 * div_fac)); 472 } 473 } else { 474 if ((div_fac % 2 != 0) && (div_fac >= 3)) { 475 src_clk = (src_clk / div_fac); 476 } else { 477 break; //clock gated 478 } 479 } 480 } 481 break; 482 483 case M4_GSPI: 484 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL; 485 switch (src_clk_mux) { 486 case GSPI_M4_SOC_CLK_FOR_OTHER_CLKS: 487 src_clk = system_clocks.soc_clock; 488 break; 489 case GSPI_ULP_REF_CLK: 490 switch (system_clocks.m4_ref_clock_source) { 491 case ULPSS_REF_BYP_CLK: 492 src_clk = system_clocks.byp_rc_ref_clock; 493 break; 494 case ULPSS_ULP_MHZ_RC_CLK: 495 src_clk = system_clocks.rc_mhz_clock; 496 break; 497 case ULPSS_40MHZ_CLK: 498 src_clk = system_clocks.rf_ref_clock; 499 break; 500 case ULPSS_MEMS_REF_CLK: 501 src_clk = system_clocks.rc_mhz_clock; 502 break; 503 case ULPSS_ULP_20MHZ_RINGOSC_CLK: 504 src_clk = system_clocks.ro_20mhz_clock; 505 break; 506 case ULPSS_ULP_DOUBLER_CLK: 507 src_clk = system_clocks.doubler_clock; 508 break; 509 default: 510 break; 511 } 512 break; 513 case GSPI_SOC_PLL_CLK: 514 src_clk = system_clocks.soc_pll_clock; 515 break; 516 case GSPI_MODEM_PLL_CLK2: 517 src_clk = system_clocks.modem_pll_clock2; 518 break; 519 case GSPI_INTF_PLL_CLK: 520 src_clk = system_clocks.intf_pll_clock; 521 break; 522 default: 523 break; 524 } 525 break; 526 527 case M4_ETHERNET: 528 src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL; 529 switch (src_clk_mux) { 530 case ETH_INTF_PLL_CLK: 531 src_clk = system_clocks.intf_pll_clock; 532 break; 533 case ETH_SOC_PLL_CLK: 534 src_clk = system_clocks.soc_pll_clock; 535 break; 536 default: 537 break; 538 } 539 540 div_fac = (M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_DIV_FAC); 541 swallow_val = (M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SWALLOW_SEL); 542 if (swallow_val) { 543 if (div_fac == 0) { 544 return src_clk; 545 } else { 546 src_clk = (src_clk / div_fac); 547 } 548 } else { 549 if (div_fac == 0) { 550 src_clk = (src_clk / 2); //divider bypassed 551 } else { 552 src_clk = (src_clk / (2 * div_fac)); 553 } 554 } 555 break; 556 557 case M4_I2SM: 558 src_clk_mux = M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL; 559 switch (src_clk_mux) { 560 case I2S_PLLCLK: 561 src_clk = system_clocks.i2s_pll_clock; 562 break; 563 case I2S_M4SOCCLKFOROTHERS: 564 src_clk = system_clocks.soc_clock; 565 break; 566 default: 567 break; 568 } 569 div_fac = (M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC); 570 if (div_fac == 0) { 571 return src_clk; 572 } else { 573 src_clk = (src_clk / (2 * div_fac)); 574 } 575 break; 576 577 case ULPSS_SSI: 578 src_clk_mux = ULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL; 579 switch (src_clk_mux) { 580 case ULP_SSI_REF_CLK: 581 src_clk = system_clocks.ulpss_ref_clk; 582 break; 583 case ULP_SSI_ULP_32KHZ_RO_CLK: 584 src_clk = system_clocks.ro_32khz_clock; 585 break; 586 case ULP_SSI_ULP_32KHZ_RC_CLK: 587 src_clk = system_clocks.rc_32khz_clock; 588 break; 589 case ULP_SSI_ULP_32KHZ_XTAL_CLK: 590 src_clk = system_clocks.xtal_32khz_clock; 591 break; 592 case ULP_SSI_ULP_MHZ_RC_CLK: 593 src_clk = system_clocks.rc_mhz_clock; 594 break; 595 case ULP_SSI_ULP_20MHZ_RO_CLK: 596 src_clk = system_clocks.ro_20mhz_clock; 597 break; 598 case ULP_SSI_SOC_CLK: 599 src_clk = system_clocks.soc_clock; 600 break; 601 default: 602 break; 603 } 604 div_fac = (ULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_DIV_FACTOR); 605 if (div_fac == 0) { 606 return src_clk; 607 } else { 608 src_clk = (src_clk / div_fac); 609 } 610 break; 611 612 case ULPSS_I2S: 613 src_clk_mux = ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b; 614 switch (src_clk_mux) { 615 case ULP_I2S_REF_CLK: 616 src_clk = system_clocks.ulpss_ref_clk; 617 break; 618 case ULP_I2S_ULP_32KHZ_RO_CLK: 619 src_clk = system_clocks.ro_32khz_clock; 620 break; 621 case ULP_I2S_ULP_32KHZ_RC_CLK: 622 src_clk = system_clocks.rc_32khz_clock; 623 break; 624 case ULP_I2S_ULP_32KHZ_XTAL_CLK: 625 src_clk = system_clocks.xtal_32khz_clock; 626 break; 627 case ULP_I2S_ULP_MHZ_RC_CLK: 628 src_clk = system_clocks.rc_mhz_clock; 629 break; 630 case ULP_I2S_ULP_20MHZ_RO_CLK: 631 src_clk = system_clocks.ro_20mhz_clock; 632 break; 633 default: 634 break; 635 } 636 div_fac = (ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLKDIV_FACTOR); 637 if (div_fac == 0) { 638 return src_clk; 639 } else { 640 src_clk = (src_clk / (2 * div_fac)); 641 } 642 break; 643 644 case ULPSS_UART: 645 src_clk_mux = ULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL; 646 switch (src_clk_mux) { 647 case ULP_UART_REF_CLK: 648 src_clk = system_clocks.ulpss_ref_clk; 649 break; 650 case ULP_UART_ULP_32KHZ_RO_CLK: 651 src_clk = system_clocks.ro_32khz_clock; 652 break; 653 case ULP_UART_ULP_32KHZ_RC_CLK: 654 src_clk = system_clocks.rc_32khz_clock; 655 break; 656 case ULP_UART_ULP_32KHZ_XTAL_CLK: 657 src_clk = system_clocks.xtal_32khz_clock; 658 break; 659 case ULP_UART_ULP_MHZ_RC_CLK: 660 src_clk = system_clocks.rc_mhz_clock; 661 break; 662 case ULP_UART_ULP_20MHZ_RO_CLK: 663 src_clk = system_clocks.ro_20mhz_clock; 664 break; 665 case ULP_UART_SOC_CLK: 666 src_clk = system_clocks.soc_clock; 667 break; 668 case ULP_UART_ULP_DOUBLER_CLK: 669 src_clk = system_clocks.doubler_clock; 670 break; 671 default: 672 break; 673 } 674 div_fac = (ULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLKDIV_FACTOR); 675 if (div_fac == 0) { 676 return src_clk; 677 } else { 678 src_clk = (src_clk / div_fac); 679 } 680 break; 681 682 case ULPSS_TIMER: 683 src_clk_mux = ULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL; 684 switch (src_clk_mux) { 685 case ULP_TIMER_REF_CLK: 686 src_clk = system_clocks.ulpss_ref_clk; 687 break; 688 case ULP_TIMER_32KHZ_RO_CLK: 689 src_clk = system_clocks.ro_32khz_clock; 690 break; 691 case ULP_TIMER_32KHZ_RC_CLK: 692 src_clk = system_clocks.rc_32khz_clock; 693 break; 694 case ULP_TIMER_32KHZ_XTAL_CLK: 695 src_clk = system_clocks.xtal_32khz_clock; 696 break; 697 case ULP_TIMER_MHZ_RC_CLK: 698 src_clk = system_clocks.rc_mhz_clock; 699 break; 700 case ULP_TIMER_20MHZ_RO_CLK: 701 src_clk = system_clocks.ro_20mhz_clock; 702 break; 703 case ULP_TIMER_ULP_SOC_CLK: 704 src_clk = system_clocks.soc_clock; 705 break; 706 default: 707 break; 708 } 709 //no division factor 710 break; 711 712 case ULPSS_AUX: 713 src_clk_mux = ULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL; 714 switch (src_clk_mux) { 715 case ULP_AUX_REF_CLK: 716 src_clk = system_clocks.ulpss_ref_clk; 717 break; 718 case ULP_AUX_32KHZ_RO_CLK: 719 src_clk = system_clocks.ro_32khz_clock; 720 break; 721 case ULP_AUX_32KHZ_RC_CLK: 722 src_clk = system_clocks.rc_32khz_clock; 723 break; 724 case ULP_AUX_32KHZ_XTAL_CLK: 725 src_clk = system_clocks.xtal_32khz_clock; 726 break; 727 case ULP_AUX_MHZ_RC_CLK: 728 src_clk = system_clocks.rc_mhz_clock; 729 break; 730 case ULP_AUX_20MHZ_RO_CLK: 731 src_clk = system_clocks.ro_20mhz_clock; 732 break; 733 case ULP_AUX_ULP_SOC_CLK: 734 src_clk = system_clocks.soc_clock; 735 break; 736 case ULP_AUX_ULP_DOUBLER_CLK: 737 src_clk = system_clocks.doubler_clock; 738 break; 739 case ULP_AUX_I2S_PLL_CLK: 740 src_clk = system_clocks.i2s_pll_clock; 741 break; 742 default: 743 break; 744 } 745 //no division factor 746 break; 747 748 case ULPSS_TOUCH: 749 src_clk_mux = ULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL; 750 switch (src_clk_mux) { 751 case ULP_TOUCH_REF_CLK: 752 src_clk = system_clocks.ulpss_ref_clk; 753 break; 754 case ULP_TOUCH_32KHZ_RO_CLK: 755 src_clk = system_clocks.ro_32khz_clock; 756 break; 757 case ULP_TOUCH_32KHZ_RC_CLK: 758 src_clk = system_clocks.rc_32khz_clock; 759 break; 760 case ULP_TOUCH_32KHZ_XTAL_CLK: 761 src_clk = system_clocks.xtal_32khz_clock; 762 break; 763 case ULP_TOUCH_MHZ_RC_CLK: 764 src_clk = system_clocks.rc_mhz_clock; 765 break; 766 case ULP_TOUCH_20MHZ_RO_CLK: 767 src_clk = system_clocks.ro_20mhz_clock; 768 break; 769 case ULP_TOUCH_ULP_SOC_CLK: 770 src_clk = system_clocks.soc_clock; 771 break; 772 default: 773 break; 774 } 775 div_fac = (ULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLKDIV_FACTOR); 776 if (div_fac == 0) { 777 return src_clk; 778 } else { 779 src_clk = (src_clk / div_fac); 780 } 781 break; 782 } 783 return src_clk; 784 } 785 /** @} */ 786
