1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32WBAxx_HAL_GTZC_H 20 #define STM32WBAxx_HAL_GTZC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32wbaxx_hal_def.h" 28 29 /** @addtogroup STM32WBAxx_HAL_Driver 30 * @{ 31 */ 32 33 #if defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) 34 35 /** @addtogroup GTZC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup GTZC_Exported_Types GTZC Exported Types 42 * @{ 43 */ 44 45 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ 46 #if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx) 47 #define GTZC_MPCBB_NB_VCTR_REG_MAX 4U /*!< Maximum number of superblocks */ 48 #endif 49 #define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 1U /*!< Maximum number of 32-bit registers to lock superblocks */ 50 typedef struct 51 { 52 uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. 53 Each bit corresponds to a block inside the super-block. 54 0 means non-secure, 1 means secure */ 55 uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. 56 Each bit corresponds to a block inside the super-block. 57 0 means non-privilege, 1 means privilege */ 58 uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 59 0 means unlocked, 1 means locked */ 60 } MPCBB_Attribute_ConfigTypeDef; 61 62 typedef struct 63 { 64 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access 65 field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 66 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 67 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 68 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 69 } MPCBB_ConfigTypeDef; 70 71 /** 72 * @} 73 */ 74 75 /* Private constants ---------------------------------------------------------*/ 76 77 /** @defgroup GTZC_Private_Constants GTZC Private Constants 78 * @{ 79 */ 80 81 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 82 * @{ 83 */ 84 85 /* composition definition for Peripheral identifier parameter (PeriphId) used in 86 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 87 * functions and also in all HAL_GTZC_TZIC relative functions. 88 * Bitmap Definition 89 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 90 * Each bit is dedicated to a single register. 91 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 92 * all peripherals within all registers. 93 * bits[4:0] Field "bit position". Define the bit position within the 94 * register dedicated to the peripheral, value from 0 to 31. 95 */ 96 #define GTZC_PERIPH_REG_SHIFT (28U) 97 #define GTZC_PERIPH_REG (0xF0000000U) 98 #define GTZC_PERIPH_REG1 (0x00000000U) 99 #define GTZC_PERIPH_REG2 (0x10000000U) 100 #define GTZC_PERIPH_REG3 (0x20000000U) 101 #define GTZC_PERIPH_REG4 (0x30000000U) 102 #define GTZC_PERIPH_BIT_POSITION (0x0000001FU) 103 104 /** 105 * @} 106 */ 107 108 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 109 * @{ 110 */ 111 #define GTZC_ATTR_SEC_MASK 0x100U 112 #define GTZC_ATTR_PRIV_MASK 0x200U 113 114 /** 115 * @} 116 */ 117 118 /** 119 * @} 120 */ 121 122 /* Exported constants --------------------------------------------------------*/ 123 124 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 125 * @{ 126 */ 127 128 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 129 * @{ 130 */ 131 132 #define GTZC_MPCBB_SRWILADIS_ENABLE 0U 133 #define GTZC_MPCBB_SRWILADIS_DISABLE GTZC_MPCBB_CR_SRWILADIS_Msk 134 135 /** 136 * @} 137 */ 138 139 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 140 * @{ 141 */ 142 143 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED 0U 144 #define GTZC_MPCBB_INVSECSTATE_INVERTED GTZC_MPCBB_CR_INVSECSTATE_Msk 145 146 /** 147 * @} 148 */ 149 150 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 151 * @{ 152 */ 153 /* GTZC */ 154 #define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 155 #if defined (TIM3) 156 #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 157 #endif /* TIM3 */ 158 #if defined (WWDG) 159 #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 160 #endif /* WWDG */ 161 #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 162 #if defined (USART2) 163 #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 164 #endif /* USART2 */ 165 #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 166 #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 167 168 #if defined (TIM1) 169 #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) 170 #endif /* TIM1 */ 171 #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) 172 #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 173 #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 174 #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 175 #if defined (SAI1) 176 #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 177 #endif /* SAI1 */ 178 #if defined (SPI3) 179 #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) 180 #endif /* SPI3 */ 181 #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) 182 #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) 183 #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) 184 #if defined (COMP1) 185 #define GTZC_PERIPH_COMP (GTZC_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) 186 #endif /* COMP1 */ 187 #define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) 188 189 #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) 190 #if defined (TSC) 191 #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) 192 #endif /* TSC */ 193 #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) 194 #define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) 195 #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) 196 #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) 197 #if defined (SAES) 198 #define GTZC_PERIPH_SAES (GTZC_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) 199 #endif /* SAES */ 200 #if defined (HSEM) 201 #define GTZC_PERIPH_HSEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSEM_Pos) 202 #endif /* HSEM */ 203 #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) 204 #define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) 205 #define GTZC_PERIPH_RADIO (GTZC_PERIPH_REG3 | GTZC_CFGR3_RADIO_Pos) 206 #if defined (PTACONV) 207 #define GTZC_PERIPH_PTACONV (GTZC_PERIPH_REG3 | GTZC_CFGR3_PTACONV_Pos) 208 #endif /* PTACONV */ 209 210 #define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) 211 #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) 212 #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) 213 #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) 214 #define GTZC_PERIPH_RTC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) 215 #define GTZC_PERIPH_TAMP (GTZC_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos) 216 #define GTZC_PERIPH_PWR (GTZC_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos) 217 #define GTZC_PERIPH_RCC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos) 218 #define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos) 219 #define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos) 220 #define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos) 221 #define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) 222 #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) 223 #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) 224 #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) 225 #if defined (SRAM6_BASE) 226 #define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) 227 #define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) 228 #endif /* SRAM6 */ 229 230 #define GTZC_PERIPH_ALL (0x00000020U) 231 232 /* Note that two maximum values are also defined here: 233 * - max number of securable AHB/APB peripherals or masters 234 * (used in TZSC sub-block) 235 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 236 * (used in TZIC sub-block) 237 */ 238 #if defined (PTACONV) 239 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PTACONV) + 1U) 240 #else 241 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RADIO) + 1U) 242 #endif /* PTACONV */ 243 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB6_REG) + 1U) 244 245 /** 246 * @} 247 */ 248 249 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 250 * @{ 251 */ 252 253 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 254 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 255 * functions 256 */ 257 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 258 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 259 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 260 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 261 262 /** 263 * @} 264 */ 265 266 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 267 * @{ 268 */ 269 270 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 271 #define GTZC_TZSC_LOCK_OFF 0U 272 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 273 274 /** 275 * @} 276 */ 277 278 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 279 * @{ 280 */ 281 282 /* user-oriented definitions for MPCBB */ 283 #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ 284 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ 285 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED 0U 286 #define GTZC_MCPBB_SUPERBLOCK_LOCKED 1U 287 288 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 289 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 290 #define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) 291 #define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) 292 293 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 294 #define GTZC_MCPBB_LOCK_OFF 0U 295 #define GTZC_MCPBB_LOCK_ON 1U 296 297 /** 298 * @} 299 */ 300 301 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 302 * @{ 303 */ 304 305 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 306 #define GTZC_TZIC_NO_ILA_EVENT 0U 307 #define GTZC_TZIC_ILA_EVENT_PENDING 1U 308 309 /** 310 * @} 311 */ 312 313 /** 314 * @} 315 */ 316 317 /* Private macros ------------------------------------------------------------*/ 318 319 /** @defgroup GTZC_Private_Macros GTZC Private Macros 320 * @{ 321 */ 322 323 /* retrieve information to access register for a specific PeriphId */ 324 #define GTZC_GET_REG_INDEX(periph_id)\ 325 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 326 #define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ 327 ((((periph_id) & GTZC_PERIPH_REG) <= GTZC_PERIPH_REG4) ? \ 328 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ 329 ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) 330 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 331 332 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 333 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 334 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 335 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 336 #else 337 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 338 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) 339 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 340 341 /* MISRA C:2012 Rule-20.10 deviation granted to use the definition of */ 342 /* GTZC_MEM_SIZE(), GTZC_BASE_ADDRESS_S() and GTZC_BASE_ADDRESS_NS() */ 343 #define GTZC_MEM_SIZE(mem)\ 344 ( mem ## _SIZE ) 345 346 #define GTZC_BASE_ADDRESS_S(mem)\ 347 ( mem ## _BASE_S ) 348 349 #define GTZC_BASE_ADDRESS_NS(mem)\ 350 ( mem ## _BASE_NS ) 351 352 /** 353 * @} 354 */ 355 356 /* Exported macros -----------------------------------------------------------*/ 357 358 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 359 * @{ 360 */ 361 362 /* user-oriented macro to get array index of a specific PeriphId 363 * in case of GTZC_PERIPH_ALL usage in the two following functions: 364 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 365 */ 366 #define HAL_GTZC_GET_ARRAY_INDEX(periph_id) \ 367 ((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id))) 368 369 #define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ 370 (((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id))) 371 372 #define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ 373 ((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id))) 374 375 /** 376 * @} 377 */ 378 379 /* Exported functions --------------------------------------------------------*/ 380 381 /** @addtogroup GTZC_Exported_Functions 382 * @{ 383 */ 384 385 /** @addtogroup GTZC_Exported_Functions_Group1 386 * @brief TZSC Initialization and Configuration functions 387 * @{ 388 */ 389 390 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 391 uint32_t PeriphAttributes); 392 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 393 uint32_t *PeriphAttributes); 394 395 /** 396 * @} 397 */ 398 399 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 400 401 /** @addtogroup GTZC_Exported_Functions_Group3 402 * @brief TZSC and TZSC-MPCWM Lock functions 403 * @{ 404 */ 405 406 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 407 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); 408 409 /** 410 * @} 411 */ 412 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 413 /** @addtogroup GTZC_Exported_Functions_Group4 414 * @brief MPCBB Initialization and Configuration functions 415 * @{ 416 */ 417 418 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 419 const MPCBB_ConfigTypeDef *pMPCBB_desc); 420 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 421 MPCBB_ConfigTypeDef *pMPCBB_desc); 422 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 423 uint32_t NbBlocks, 424 const uint32_t *pMemAttributes); 425 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 426 uint32_t NbBlocks, 427 uint32_t *pMemAttributes); 428 429 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 430 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 431 uint32_t NbSuperBlocks, 432 const uint32_t *pLockAttributes); 433 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 434 uint32_t NbSuperBlocks, 435 uint32_t *pLockAttributes); 436 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 437 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 438 uint32_t *pLockState); 439 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 440 441 /** 442 * @} 443 */ 444 445 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 446 447 /** @addtogroup GTZC_Exported_Functions_Group5 448 * @brief TZIC functions 449 * @{ 450 */ 451 452 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 453 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 454 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 455 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 456 457 /** 458 * @} 459 */ 460 461 /** @addtogroup GTZC_Exported_Functions_Group6 462 * @brief IRQ related Functions 463 * @{ 464 */ 465 466 void HAL_GTZC_IRQHandler(void); 467 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 468 469 /** 470 * @} 471 */ 472 473 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 474 475 /** 476 * @} 477 */ 478 479 /** 480 * @} 481 */ 482 483 #endif /* defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) */ 484 485 /** 486 * @} 487 */ 488 489 #ifdef __cplusplus 490 } 491 #endif 492 493 #endif /* STM32WBAxx_HAL_GTZC_H */ 494
