1 /** 2 ****************************************************************************** 3 * @file stm32wbaxx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32WBAxx_HAL_GTZC_H 20 #define STM32WBAxx_HAL_GTZC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32wbaxx_hal_def.h" 28 29 /** @addtogroup STM32WBAxx_HAL_Driver 30 * @{ 31 */ 32 33 #if defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) 34 35 /** @addtogroup GTZC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup GTZC_Exported_Types GTZC Exported Types 42 * @{ 43 */ 44 45 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ 46 #define GTZC_MCPBB_NB_VCTR_REG_MAX (4U) 47 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) 48 typedef struct 49 { 50 uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. 51 Each bit corresponds to a block inside the super-block. 52 0 means non-secure, 1 means secure */ 53 uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. 54 Each bit corresponds to a block inside the super-block. 55 0 means non-privilege, 1 means privilege */ 56 uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 57 0 means unlocked, 1 means locked */ 58 } MPCBB_Attribute_ConfigTypeDef; 59 60 typedef struct 61 { 62 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access 63 field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 64 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 65 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 66 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 67 } MPCBB_ConfigTypeDef; 68 69 /** 70 * @} 71 */ 72 73 /* Private constants ---------------------------------------------------------*/ 74 75 /** @defgroup GTZC_Private_Constants GTZC Private Constants 76 * @{ 77 */ 78 79 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 80 * @{ 81 */ 82 83 /* composition definition for Peripheral identifier parameter (PeriphId) used in 84 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 85 * functions and also in all HAL_GTZC_TZIC relative functions. 86 * Bitmap Definition 87 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 88 * Each bit is dedicated to a single register. 89 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 90 * all peripherals within all registers. 91 * bits[4:0] Field "bit position". Define the bit position within the 92 * register dedicated to the peripheral, value from 0 to 31. 93 */ 94 #define GTZC_PERIPH_REG_SHIFT (28U) 95 #define GTZC_PERIPH_REG (0xF0000000U) 96 #define GTZC_PERIPH_REG1 (0x00000000U) 97 #define GTZC_PERIPH_REG2 (0x10000000U) 98 #define GTZC_PERIPH_REG3 (0x20000000U) 99 #define GTZC_PERIPH_REG4 (0x30000000U) 100 #define GTZC_PERIPH_BIT_POSITION (0x0000001FU) 101 102 /** 103 * @} 104 */ 105 106 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 107 * @{ 108 */ 109 #define GTZC_ATTR_SEC_MASK 0x100U 110 #define GTZC_ATTR_PRIV_MASK 0x200U 111 112 /** 113 * @} 114 */ 115 116 /** 117 * @} 118 */ 119 120 /* Exported constants --------------------------------------------------------*/ 121 122 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 123 * @{ 124 */ 125 126 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 127 * @{ 128 */ 129 130 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 131 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 132 133 /** 134 * @} 135 */ 136 137 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 138 * @{ 139 */ 140 141 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 142 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 143 144 /** 145 * @} 146 */ 147 148 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 149 * @{ 150 */ 151 /* GTZC */ 152 #define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 153 #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 154 #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 155 #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 156 #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 157 #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 158 #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 159 160 #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) 161 #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) 162 #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 163 #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 164 #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 165 #if defined (STM32WBA54xx) || defined (STM32WBA55xx) 166 #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 167 #endif /* STM32WBA54xx || STM32WBA55xx */ 168 #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) 169 #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) 170 #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) 171 #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) 172 #if defined (STM32WBA54xx) || defined (STM32WBA55xx) 173 #define GTZC_PERIPH_COMP (GTZC_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) 174 #endif /* STM32WBA54xx || STM32WBA55xx */ 175 #define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) 176 177 #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) 178 #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) 179 #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) 180 #define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) 181 #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) 182 #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) 183 #define GTZC_PERIPH_SAES (GTZC_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) 184 #define GTZC_PERIPH_HSEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSEM_Pos) 185 #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) 186 #define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) 187 #define GTZC_PERIPH_RADIO (GTZC_PERIPH_REG3 | GTZC_CFGR3_RADIO_Pos) 188 #if defined (PTACONV) 189 #define GTZC_PERIPH_PTACONV (GTZC_PERIPH_REG3 | GTZC_CFGR3_PTACONV_Pos) 190 #endif /* PTACONV */ 191 192 #define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) 193 #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) 194 #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) 195 #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) 196 #define GTZC_PERIPH_RTC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) 197 #define GTZC_PERIPH_TAMP (GTZC_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos) 198 #define GTZC_PERIPH_PWR (GTZC_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos) 199 #define GTZC_PERIPH_RCC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos) 200 #define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos) 201 #define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos) 202 #define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos) 203 #define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) 204 #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) 205 #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) 206 #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) 207 #define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) 208 #define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) 209 210 #define GTZC_PERIPH_ALL (0x00000020U) 211 212 /* Note that two maximum values are also defined here: 213 * - max number of securable AHB/APB peripherals or masters 214 * (used in TZSC sub-block) 215 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 216 * (used in TZIC sub-block) 217 */ 218 #if defined (PTACONV) 219 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PTACONV) + 1U) 220 #else 221 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RADIO) + 1U) 222 #endif /* PTACONV */ 223 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB6_REG) + 1U) 224 225 /** 226 * @} 227 */ 228 229 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 230 * @{ 231 */ 232 233 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 234 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 235 * functions 236 */ 237 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 238 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 239 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 240 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 241 242 /** 243 * @} 244 */ 245 246 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 247 * @{ 248 */ 249 250 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 251 #define GTZC_TZSC_LOCK_OFF (0U) 252 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 253 254 /** 255 * @} 256 */ 257 258 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 259 * @{ 260 */ 261 262 /* user-oriented definitions for MPCBB */ 263 #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ 264 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ 265 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) 266 #define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) 267 268 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 269 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 270 #define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) 271 #define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) 272 273 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 274 #define GTZC_MCPBB_LOCK_OFF (0U) 275 #define GTZC_MCPBB_LOCK_ON (1U) 276 277 /** 278 * @} 279 */ 280 281 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 282 * @{ 283 */ 284 285 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 286 #define GTZC_TZIC_NO_ILA_EVENT (0U) 287 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 288 289 /** 290 * @} 291 */ 292 293 /** 294 * @} 295 */ 296 297 /* Private macros ------------------------------------------------------------*/ 298 299 /** @defgroup GTZC_Private_Macros GTZC Private Macros 300 * @{ 301 */ 302 303 /* retrieve information to access register for a specific PeriphId */ 304 #define GTZC_GET_REG_INDEX(periph_id)\ 305 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 306 #define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ 307 ((((periph_id) & GTZC_PERIPH_REG) <= GTZC_PERIPH_REG4) ? \ 308 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ 309 ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) 310 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 311 312 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 313 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 314 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 315 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 316 #else 317 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 318 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) 319 #endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 320 321 /* MISRA C:2012 Rule-20.10 deviation granted to use the definition of */ 322 /* GTZC_MEM_SIZE(), GTZC_BASE_ADDRESS_S() and GTZC_BASE_ADDRESS_NS() */ 323 #define GTZC_MEM_SIZE(mem)\ 324 ( mem ## _SIZE ) 325 326 #define GTZC_BASE_ADDRESS_S(mem)\ 327 ( mem ## _BASE_S ) 328 329 #define GTZC_BASE_ADDRESS_NS(mem)\ 330 ( mem ## _BASE_NS ) 331 332 /** 333 * @} 334 */ 335 336 /* Exported macros -----------------------------------------------------------*/ 337 338 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 339 * @{ 340 */ 341 342 /* user-oriented macro to get array index of a specific PeriphId 343 * in case of GTZC_PERIPH_ALL usage in the two following functions: 344 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 345 */ 346 #define HAL_GTZC_GET_ARRAY_INDEX(periph_id) \ 347 ((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id))) 348 349 #define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ 350 (((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id))) 351 352 #define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ 353 ((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id))) 354 355 /** 356 * @} 357 */ 358 359 /* Exported functions --------------------------------------------------------*/ 360 361 /** @addtogroup GTZC_Exported_Functions 362 * @{ 363 */ 364 365 /** @addtogroup GTZC_Exported_Functions_Group1 366 * @brief TZSC Initialization and Configuration functions 367 * @{ 368 */ 369 370 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 371 uint32_t PeriphAttributes); 372 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 373 uint32_t *PeriphAttributes); 374 375 /** 376 * @} 377 */ 378 379 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 380 381 /** @addtogroup GTZC_Exported_Functions_Group3 382 * @brief TZSC and TZSC-MPCWM Lock functions 383 * @{ 384 */ 385 386 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 387 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); 388 389 /** 390 * @} 391 */ 392 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 393 /** @addtogroup GTZC_Exported_Functions_Group4 394 * @brief MPCBB Initialization and Configuration functions 395 * @{ 396 */ 397 398 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 399 const MPCBB_ConfigTypeDef *pMPCBB_desc); 400 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 401 MPCBB_ConfigTypeDef *pMPCBB_desc); 402 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 403 uint32_t NbBlocks, 404 const uint32_t *pMemAttributes); 405 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 406 uint32_t NbBlocks, 407 uint32_t *pMemAttributes); 408 409 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 410 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 411 uint32_t NbSuperBlocks, 412 const uint32_t *pLockAttributes); 413 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 414 uint32_t NbSuperBlocks, 415 uint32_t *pLockAttributes); 416 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 417 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 418 uint32_t *pLockState); 419 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 420 421 /** 422 * @} 423 */ 424 425 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 426 427 /** @addtogroup GTZC_Exported_Functions_Group5 428 * @brief TZIC functions 429 * @{ 430 */ 431 432 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 433 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 434 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 435 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 436 437 /** 438 * @} 439 */ 440 441 /** @addtogroup GTZC_Exported_Functions_Group6 442 * @brief IRQ related Functions 443 * @{ 444 */ 445 446 void HAL_GTZC_IRQHandler(void); 447 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 448 449 /** 450 * @} 451 */ 452 453 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 454 455 /** 456 * @} 457 */ 458 459 /** 460 * @} 461 */ 462 463 #endif /* defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) */ 464 465 /** 466 * @} 467 */ 468 469 #ifdef __cplusplus 470 } 471 #endif 472 473 #endif /* STM32WBAxx_HAL_GTZC_H */ 474
