1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32U5xx_HAL_GTZC_H 20 #define STM32U5xx_HAL_GTZC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32u5xx_hal_def.h" 28 29 /** @addtogroup STM32U5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup GTZC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup GTZC_Exported_Types GTZC Exported Types 40 * @{ 41 */ 42 43 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ 44 #if defined (SRAM5_BASE) 45 #define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */ 46 #define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */ 47 #else 48 #define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */ 49 #define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */ 50 #endif /* SRAM5_BASE */ 51 52 typedef struct 53 { 54 uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for 55 a super-block. Each bit corresponds to a block 56 inside the super-block. 0 means non-secure, 57 1 means secure */ 58 uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for 59 a super-block. Each bit corresponds to a block 60 inside the super-block. 0 means non-privilege, 61 1 means privilege */ 62 uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of 63 a super-block (32 blocks). 0 means unlocked, 64 1 means locked */ 65 } MPCBB_Attribute_ConfigTypeDef; 66 67 typedef struct 68 { 69 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access 70 field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 71 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 72 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 73 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 74 } MPCBB_ConfigTypeDef; 75 76 typedef struct 77 { 78 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 79 GTZC_MPCWM_AreaId */ 80 uint32_t Offset; /*!< Offset of the watermark area, starting from the selected 81 memory base address. It must aligned on 128KB for FMC 82 and OCTOSPI memories, and on 32-byte for BKPSRAM */ 83 uint32_t Length; /*!< Length of the watermark area, starting from the selected 84 Offset. It must aligned on 128KB for FMC and OCTOSPI 85 memories, and on 32-byte for BKPSRAM */ 86 uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value 87 of @ref GTZC_MPCWM_Attribute */ 88 uint32_t Lock; /*!< Lock of the watermark area. It can be a value 89 of @ref GTZC_MPCWM_Lock */ 90 uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to 91 ENABLE or DISABLE */ 92 } MPCWM_ConfigTypeDef; 93 94 /** 95 * @} 96 */ 97 98 /* Private constants ---------------------------------------------------------*/ 99 100 /** @defgroup GTZC_Private_Constants GTZC Private Constants 101 * @{ 102 */ 103 104 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 105 * @{ 106 */ 107 108 /* composition definition for Peripheral identifier parameter (PeriphId) used in 109 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 110 * functions and also in all HAL_GTZC_TZIC relative functions. 111 * Bitmap Definition 112 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 113 * Each bit is dedicated to a single register. 114 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 115 * all peripherals within all registers. 116 * bits[4:0] Field "bit position". Define the bit position within the 117 * register dedicated to the peripheral, value from 0 to 31. 118 */ 119 #define GTZC_PERIPH_REG_SHIFT (28U) 120 #define GTZC_PERIPH_REG (0xF0000000U) 121 #define GTZC1_PERIPH_REG1 (0x00000000U) 122 #define GTZC1_PERIPH_REG2 (0x10000000U) 123 #define GTZC1_PERIPH_REG3 (0x20000000U) 124 #define GTZC1_PERIPH_REG4 (0x30000000U) 125 #define GTZC2_PERIPH_REG1 (0x40000000U) 126 #define GTZC2_PERIPH_REG2 (0x50000000U) 127 #define GTZC_PERIPH_BIT_POSITION (0x0000001FU) 128 129 /** 130 * @} 131 */ 132 133 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 134 * @{ 135 */ 136 #define GTZC_ATTR_SEC_MASK 0x100U 137 #define GTZC_ATTR_PRIV_MASK 0x200U 138 139 /** 140 * @} 141 */ 142 143 /** 144 * @} 145 */ 146 147 /* Exported constants --------------------------------------------------------*/ 148 149 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 150 * @{ 151 */ 152 153 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 154 * @{ 155 */ 156 157 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 158 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 159 160 /** 161 * @} 162 */ 163 164 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 165 * @{ 166 */ 167 168 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 169 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 170 171 /** 172 * @} 173 */ 174 175 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 176 * @{ 177 */ 178 179 #define GTZC_TZSC_MPCWM_ID1 (0U) 180 #define GTZC_TZSC_MPCWM_ID2 (1U) 181 182 /** 183 * @} 184 */ 185 186 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 187 * @{ 188 */ 189 /* GTZC1 */ 190 #define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 191 #define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 192 #define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) 193 #define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) 194 #define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) 195 #define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) 196 #define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 197 #define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 198 #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) 199 #if defined (USART2) 200 #define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 201 #endif /* USART2 */ 202 #define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) 203 #define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) 204 #define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) 205 #define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 206 #define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) 207 #define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) 208 #define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) 209 #define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 210 #define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) 211 #if defined (UCPD1) 212 #define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) 213 #endif /* UCPD1 */ 214 #if defined (USART6) 215 #define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) 216 #endif /* USART6 */ 217 #if defined (I2C5) 218 #define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos) 219 #endif /* I2C5 */ 220 #if defined (I2C6) 221 #define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos) 222 #endif /* I2C6 */ 223 #define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) 224 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) 225 #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) 226 #define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 227 #define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) 228 #define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 229 #define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 230 #define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 231 #if defined (SAI2) 232 #define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) 233 #endif /* SAI2 */ 234 #if defined (LTDC) || defined (USB_DRD_FS) 235 #define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos) 236 #endif /* LTDC || USB_DRD_FS */ 237 #if defined (DSI) 238 #define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos) 239 #endif /* DSI */ 240 #if defined (GFXTIM) 241 #define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos) 242 #endif /* GFXTIM */ 243 #define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos) 244 #define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) 245 #define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) 246 #define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) 247 #define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) 248 #if defined (DMA2D) 249 #define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos) 250 #endif /* DMA2D */ 251 #define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) 252 #define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) 253 #define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) 254 #define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) 255 #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 256 #define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) 257 #endif /* (USB_OTG_FS) || (USB_OTG_HS) */ 258 #if defined (AES) 259 #define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) 260 #endif /* AES */ 261 #define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) 262 #define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) 263 #if defined (PKA) 264 #define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) 265 #endif /* PKA */ 266 #if defined (SAES) 267 #define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) 268 #endif /* SAES */ 269 #if defined (OCTOSPIM) 270 #define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos) 271 #endif /* OCTOSPIM */ 272 #define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) 273 #if defined (SDMMC2) 274 #define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) 275 #endif /* SDMMC2 */ 276 #if defined (FMC_BASE) 277 #define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos) 278 #endif /* FMC_BASE */ 279 #define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) 280 #if defined (OCTOSPI2) 281 #define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos) 282 #endif /* OCTOSPI2 */ 283 #define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) 284 #if defined (GPU2D) 285 #define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos) 286 #endif /* GPU2D */ 287 #if defined (GFXMMU) 288 #define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos) 289 #define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos) 290 #endif /* GFXMMU */ 291 #if defined (HSPI1) 292 #define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos) 293 #endif /* HSPI1 */ 294 #if defined (DCACHE2) 295 #define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos) 296 #endif /* DCACHE2 */ 297 #if defined (JPEG) 298 #define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos) 299 #endif /* JPEG */ 300 #define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) 301 #define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) 302 #define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) 303 #if defined (OTFDEC2) 304 #define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) 305 #endif /* OTFDEC2 */ 306 #if defined (OTFDEC1) 307 #define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) 308 #endif /* OTFDEC1 */ 309 #define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos) 310 #define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos) 311 #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) 312 #if defined (FMC_BASE) 313 #define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos) 314 #endif /* FMC_BASE */ 315 #define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) 316 #if defined (OCTOSPI2) 317 #define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos) 318 #endif /* OCTOSPI2 */ 319 #if defined (HSPI1) 320 #define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos) 321 #endif /* HSPI1 */ 322 #if defined (SRAM6_BASE) 323 #define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) 324 #define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) 325 #endif /* SRAM6_BASE */ 326 #define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) 327 #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) 328 #define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) 329 #define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) 330 #if defined (SRAM3_BASE) 331 #define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) 332 #endif /* SRAM3_BASE */ 333 #define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) 334 #if defined (SRAM5_BASE) 335 #define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos) 336 #define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos) 337 #endif /* SRAM5_BASE */ 338 339 /* GTZC2 */ 340 #define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) 341 #define GTZC_PERIPH_LPUART1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos) 342 #define GTZC_PERIPH_I2C3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos) 343 #define GTZC_PERIPH_LPTIM1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos) 344 #define GTZC_PERIPH_LPTIM3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos) 345 #define GTZC_PERIPH_LPTIM4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM4_Pos) 346 #define GTZC_PERIPH_OPAMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos) 347 #define GTZC_PERIPH_COMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos) 348 #define GTZC_PERIPH_ADC4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADC4_Pos) 349 #define GTZC_PERIPH_VREFBUF (GTZC2_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos) 350 #define GTZC_PERIPH_DAC1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) 351 #define GTZC_PERIPH_ADF1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADF1_Pos) 352 #define GTZC_PERIPH_SYSCFG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos) 353 #define GTZC_PERIPH_RTC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos) 354 #define GTZC_PERIPH_TAMP (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TAMP_Pos) 355 #define GTZC_PERIPH_PWR (GTZC2_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos) 356 #define GTZC_PERIPH_RCC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos) 357 #define GTZC_PERIPH_LPDMA1 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_LPDMA1_Pos) 358 #define GTZC_PERIPH_EXTI (GTZC2_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos) 359 #define GTZC_PERIPH_TZSC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZSC2_Pos) 360 #define GTZC_PERIPH_TZIC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZIC2_Pos) 361 #define GTZC_PERIPH_SRAM4 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SRAM4_Pos) 362 #define GTZC_PERIPH_MPCBB4_REG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_MPCBB4_REG_Pos) 363 364 #define GTZC_PERIPH_ALL (0x00000020U) 365 366 /* Note that two maximum values are also defined here: 367 * - max number of securable AHB/APB peripherals or masters 368 * (used in TZSC sub-block) 369 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 370 * (used in TZIC sub-block) 371 */ 372 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_TZSC_GET_ARRAY_INDEX(GTZC_PERIPH_ADF1 + 1U)) 373 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_TZIC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB4_REG + 1U)) 374 375 /** 376 * @} 377 */ 378 379 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 380 * @{ 381 */ 382 383 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 384 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 385 * functions 386 */ 387 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 388 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 389 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 390 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 391 392 /** 393 * @} 394 */ 395 396 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 397 * @{ 398 */ 399 400 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 401 #define GTZC_TZSC_LOCK_OFF (0U) 402 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 403 404 /** 405 * @} 406 */ 407 408 /** @defgroup GTZC_MPCWM_Group GTZC MPCWM values 409 * @{ 410 */ 411 412 /* user-oriented definitions for TZSC_MPCWM */ 413 #define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ 414 #define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */ 415 416 /** 417 * @} 418 */ 419 420 /** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values 421 * @{ 422 */ 423 424 /* user-oriented definitions for TZSC_MPCWM */ 425 #define GTZC_TZSC_MPCWM_LOCK_OFF (0U) 426 #define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk 427 428 /** 429 * @} 430 */ 431 432 /** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values 433 * @{ 434 */ 435 436 /* user-oriented definitions for TZSC_MPCWM */ 437 #define GTZC_TZSC_MPCWM_REGION_NSEC (0U) 438 #define GTZC_TZSC_MPCWM_REGION_SEC (1U) 439 #define GTZC_TZSC_MPCWM_REGION_NPRIV (0U) 440 #define GTZC_TZSC_MPCWM_REGION_PRIV (2U) 441 442 /** 443 * @} 444 */ 445 446 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 447 * @{ 448 */ 449 450 /* user-oriented definitions for MPCBB */ 451 #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ 452 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ 453 #define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U) 454 #define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U) 455 456 #define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 457 #define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 458 #define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) 459 #define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) 460 461 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 462 #define GTZC_MPCBB_LOCK_OFF (0U) 463 #define GTZC_MPCBB_LOCK_ON (1U) 464 465 /** 466 * @} 467 */ 468 469 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 470 * @{ 471 */ 472 473 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 474 #define GTZC_TZIC_NO_ILA_EVENT (0U) 475 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 476 477 /** 478 * @} 479 */ 480 481 /** 482 * @} 483 */ 484 485 /* Private macros ------------------------------------------------------------*/ 486 487 /** @defgroup GTZC_Private_Macros GTZC Private Macros 488 * @{ 489 */ 490 491 /* retrieve information to access register for a specific PeriphId */ 492 #define GTZC_GET_REG_INDEX(periph_id)\ 493 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 494 #define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ 495 ((((periph_id) & GTZC_PERIPH_REG) <= GTZC1_PERIPH_REG4) ? \ 496 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ 497 ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) 498 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 499 500 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 501 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 502 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 503 504 #define GTZC_MEM_SIZE(mem)\ 505 ( mem ## _SIZE ) 506 507 #define GTZC_BASE_ADDRESS_S(mem)\ 508 ( mem ## _BASE_S ) 509 510 #define GTZC_BASE_ADDRESS_NS(mem)\ 511 ( mem ## _BASE_NS ) 512 513 /** 514 * @} 515 */ 516 517 /* Exported macros -----------------------------------------------------------*/ 518 519 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 520 * @{ 521 */ 522 523 /* user-oriented macro to get array index of a specific PeriphId 524 * in case of GTZC_PERIPH_ALL usage in the two following functions: 525 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 526 */ 527 #define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ 528 (uint32_t)((HAL_GTZC_TZSC_GET_INSTANCE(periph_id) == GTZC_TZSC1)? \ 529 ((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id)) : \ 530 (((GTZC_GET_REG_INDEX(periph_id) - 1U) * 32U) + GTZC_GET_PERIPH_POS(periph_id) )) 531 532 #define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ 533 ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) 534 535 /* user-oriented macro to get TZSC instance of a specific PeriphId */ 536 #define HAL_GTZC_TZSC_GET_INSTANCE(periph_id) \ 537 ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4 >> GTZC_PERIPH_REG_SHIFT))? \ 538 GTZC_TZSC1 : GTZC_TZSC2) 539 540 /* user-oriented macro to get TZIC instance of a specific PeriphId */ 541 #define HAL_GTZC_TZIC_GET_INSTANCE(periph_id) \ 542 ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4>> GTZC_PERIPH_REG_SHIFT))? \ 543 GTZC_TZIC1 : GTZC_TZIC2) 544 545 /** 546 * @} 547 */ 548 549 /* Exported functions --------------------------------------------------------*/ 550 551 /** @addtogroup GTZC_Exported_Functions 552 * @{ 553 */ 554 555 /** @addtogroup GTZC_Exported_Functions_Group1 556 * @brief TZSC Initialization and Configuration functions 557 * @{ 558 */ 559 560 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 561 uint32_t PeriphAttributes); 562 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 563 uint32_t *PeriphAttributes); 564 565 /** 566 * @} 567 */ 568 569 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 570 571 /** @addtogroup GTZC_Exported_Functions_Group2 572 * @brief MPCWM Initialization and Configuration functions 573 * @{ 574 */ 575 576 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, 577 const MPCWM_ConfigTypeDef *pMPCWM_Desc); 578 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, 579 MPCWM_ConfigTypeDef *pMPCWM_Desc); 580 /** 581 * @} 582 */ 583 584 /** @addtogroup GTZC_Exported_Functions_Group3 585 * @brief TZSC and TZSC-MPCWM Lock functions 586 * @{ 587 */ 588 589 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 590 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); 591 592 /** 593 * @} 594 */ 595 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 596 /** @addtogroup GTZC_Exported_Functions_Group4 597 * @brief MPCBB Initialization and Configuration functions 598 * @{ 599 */ 600 601 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 602 const MPCBB_ConfigTypeDef *pMPCBB_desc); 603 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 604 MPCBB_ConfigTypeDef *pMPCBB_desc); 605 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 606 uint32_t NbBlocks, 607 const uint32_t *pMemAttributes); 608 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 609 uint32_t NbBlocks, 610 uint32_t *pMemAttributes); 611 612 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 613 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 614 uint32_t NbSuperBlocks, 615 const uint32_t *pLockAttributes); 616 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 617 uint32_t NbSuperBlocks, 618 uint32_t *pLockAttributes); 619 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 620 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 621 uint32_t *pLockState); 622 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 623 624 /** 625 * @} 626 */ 627 628 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 629 630 /** @addtogroup GTZC_Exported_Functions_Group5 631 * @brief TZIC functions 632 * @{ 633 */ 634 635 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 636 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 637 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 638 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 639 640 /** 641 * @} 642 */ 643 644 /** @addtogroup GTZC_Exported_Functions_Group6 645 * @brief IRQ related Functions 646 * @{ 647 */ 648 649 void HAL_GTZC_IRQHandler(void); 650 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 651 652 /** 653 * @} 654 */ 655 656 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 657 658 /** 659 * @} 660 */ 661 662 /** 663 * @} 664 */ 665 666 /** 667 * @} 668 */ 669 670 #ifdef __cplusplus 671 } 672 #endif 673 674 #endif /* STM32U5xx_HAL_GTZC_H */ 675 676
