1 /****************************************************************************** 2 * @file GSPI.h 3 ******************************************************************************* 4 * # License 5 * <b>Copyright 2023,2024 Silicon Laboratories Inc. www.silabs.com</b> 6 ******************************************************************************* 7 * 8 * SPDX-License-Identifier: Zlib 9 * 10 * The licensor of this software is Silicon Laboratories Inc. 11 * 12 * This software is provided 'as-is', without any express or implied 13 * warranty. In no event will the authors be held liable for any damages 14 * arising from the use of this software. 15 * 16 * Permission is granted to anyone to use this software for any purpose, 17 * including commercial applications, and to alter it and redistribute it 18 * freely, subject to the following restrictions: 19 * 20 * 1. The origin of this software must not be misrepresented; you must not 21 * claim that you wrote the original software. If you use this software 22 * in a product, an acknowledgment in the product documentation would be 23 * appreciated but is not required. 24 * 2. Altered source versions must be plainly marked as such, and must not be 25 * misrepresented as being the original software. 26 * 3. This notice may not be removed or altered from any source distribution. 27 * 28 ******************************************************************************/ 29 30 31 #ifndef __GSPI_H__ 32 #define __GSPI_H__ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include "rsi_pll.h" 39 #include "Driver_SPI.h" 40 #include "rsi_ccp_common.h" 41 42 #include "UDMA.h" 43 44 45 46 /* Current driver status flag definition */ 47 #define SPI_INITIALIZED (1 << 0) // SPI initialized 48 #define SPI_POWERED (1 << 1) // SPI powered on 49 #define SPI_CONFIGURED (1 << 2) // SPI configured 50 #define SPI_DATA_LOST (1 << 3) // SPI data lost occurred 51 #define SPI_MODE_FAULT (1 << 4) // SPI mode fault occurred 52 #define RSI_MUTLI_SLAVE_SELECT_ERROR -7 53 54 /** 55 * Macro defines for GSPI MANUAL STATUS Register 56 */ 57 58 #define GSPI_MANUAL_STATUS_BITMASK 0x07AF /*!< GSPI Manual Status reg bitmask*/ 59 #define GSPI_BUSY_F 0x01 /*!< A read,write or dummy cycle operation is in process in manual mode*/ 60 #define GSPI_FIFO_FULL_WFIFO_S 0x02 /*!< Full status indication for Wfifo in manual mode*/ 61 #define GSPI_FIFO_AFULL_WFIFO_S 0x04 /*!< AFull status indication for Wfifo in manual mode*/ 62 #define GSPI_FIFO_EMPTY_WFIFO_S 0x08 /*!< Empty status indication for Wfifo in manual mode*/ 63 #define GSPI_FIFO_EMPTY_RFIFO_S 0x80 /*!< Empty status indication for Rfifo in manual mode*/ 64 #define GSPI_FIFO_AEMPTY_WFIFO_S 0x100 /*!< AEmpty status indication for Rfifo in manual mode*/ 65 #define GSPI_MAN_CSN 0x400 /*!< Status of chip select signal*/ 66 67 /** 68 * Macro defines for GSPI INTR MASK Register 69 */ 70 #define GSPI_INTR_MASK_BITMASK 0x7F /*!< GSPI Interrupt mask reg bitmask*/ 71 #define GSPI_INTR_MASK_BIT 0x01 /*!< Mask the GSPI intr*/ 72 #define GSPI_FIFO_AEMPTY_RFIFO_MASK 0x02 /*!< read fifo almost empty intr mask */ 73 #define GSPI_FIFO_AFULL_RFIFO_MASK 0x04 /*!< read fifo almost full intr mask*/ 74 #define GSPI_FIFO_AEMPTY_WFIFO_MASK 0x08 /*!< write fifo almost empty intr mask*/ 75 #define GSPI_FIFO_AFULL_WFIFO_MASK 0x10 /*!< Write Fifo almost full intr mask*/ 76 #define GSPI_FIFO_FULL_WFIFO_MASK 0x20 /*!< write fifo is full intr mask*/ 77 #define GSPI_FIFO_EMPTY_RFIFO_MASK 0x40 /*!< read fifo is empty intr mask*/ 78 /** 79 * Macro defines for GSPI INTR UNMASK Register 80 */ 81 #define GSPI_INTR_UNMASK_BITMASK 0x7F /*!< GSPI Interrupt Unmask reg bitmask*/ 82 #define GSPI_INTR_UNMASK_BIT 0x01 /*!< Unmask the GSPI intr*/ 83 #define GSPI_FIFO_AEMPTY_RFIFO_UNMASK 0x02 /*!< read fifo almost empty intr unmask */ 84 #define GSPI_FIFO_AFULL_RFIFO_UNMASK 0x04 /*!< read fifo almost full intr unmask*/ 85 #define GSPI_FIFO_AEMPTY_WFIFO_UNMASK 0x08 /*!< write fifo almost empty intr unmask*/ 86 #define GSPI_FIFO_AFULL_WFIFO_UNMASK 0x10 /*!< Write Fifo almost full intr unmask*/ 87 #define GSPI_FIFO_FULL_WFIFO_UNMASK 0x20 /*!< write fifo is full intr unmask*/ 88 #define GSPI_FIFO_EMPTY_RFIFO_UNMASK 0x40 /*!< read fifo is empty intr unmask*/ 89 90 #define GSPI_CS0 0 91 #define GSPI_CS1 1 92 #define GSPI_CS2 2 93 94 // SPI DMA 95 typedef struct _SPI_DMA 96 { 97 RSI_UDMA_CHA_CFG_T chnl_cfg; 98 uint8_t channel; // DMA Channel number 99 UDMA_SignalEvent_t cb_event; // DMA Event callback 100 } GSPI_DMA; 101 /* SPI status */ 102 typedef struct _SPI_STATUS { 103 uint8_t busy; // Transmitter/Receiver busy flag 104 uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) 105 uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) 106 } GSPI_STATUS; 107 108 /* SPI Information (Run-time) */ 109 typedef struct _SPI_INFO { 110 ARM_SPI_SignalEvent_t cb_event; // Event Callback 111 GSPI_STATUS status; // Status flags 112 uint8_t state; // Current SPI state 113 uint32_t mode; // Current SPI mode 114 } GSPI_INFO; 115 116 /* SPI Transfer Information (Run-Time) */ 117 typedef struct _SPI_TRANSFER_INFO { 118 uint32_t num; // Total number of transfers 119 uint8_t *rx_buf; // Pointer to in data buffer 120 uint8_t *tx_buf; // Pointer to out data buffer 121 uint32_t rx_cnt; // Number of data received 122 uint32_t tx_cnt; // Number of data sent 123 uint32_t dump_val; // Variable for dumping DMA data 124 uint16_t def_val; // Default transfer value 125 } GSPI_TRANSFER_INFO; 126 127 /* SPI Pins Configuration */ 128 typedef const struct _GSPI_PIN { 129 uint8_t port; ///< SPI GPIO port 130 uint8_t pin; ///< SPI GPIO pin 131 uint8_t mode; ///< SPI GPIO mode 132 uint8_t pad_sel; ///< SPI GPIO pad selection 133 }GSPI_PIN; 134 135 // SPI Input/Output Configuration 136 typedef struct GSPI_IO_PINS { 137 GSPI_PIN *clock; 138 GSPI_PIN *cs0; 139 #ifdef GSPI_MULTI_SLAVE 140 GSPI_PIN *cs1; 141 GSPI_PIN *cs2; 142 #endif 143 GSPI_PIN *mosi; 144 GSPI_PIN *miso; 145 } GSPI_IO; 146 147 typedef struct __GSPI_FIFO_THRESHOLDS { 148 uint8_t txdma_arb_size; 149 uint8_t rxdma_arb_size; 150 uint8_t gspi_afull_threshold ; 151 uint8_t gspi_aempty_threshold; 152 }GSPI_FIFO_THRESHOLDS; 153 154 /* SPI Resources */ 155 typedef const struct { 156 GSPI0_Type *reg; // SPI peripheral register interface 157 IRQn_Type irq_num; // SPI IRQ number 158 GSPI_DMA *rx_dma; // Receive stream register interface 159 GSPI_DMA *tx_dma; // Transmit stream register interface 160 GSPI_INFO *info; // SPI Run-time information 161 GSPI_TRANSFER_INFO *xfer; // SPI transfer information 162 GSPI_IO io; 163 GSPI_CLK_SRC_SEL_T clock_source; 164 GSPI_FIFO_THRESHOLDS *threshold; 165 uint32_t cs_en; 166 } GSPI_RESOURCES; 167 168 void RSI_GSPI_SetSlaveSelectNumber(uint8_t slavenumber); 169 uint8_t RSI_GSPI_GetSlaveSelectNumber(void); 170 ARM_DRIVER_VERSION GSPI_MASTER_GetVersion(void); 171 uint8_t RSI_GSPI_GetSlaveSelectNumber(void); 172 ARM_SPI_CAPABILITIES GSPI_MASTER_GetCapabilities(void); 173 void GSPI_WriteDummyByte(void); 174 #ifdef __cplusplus 175 } 176 #endif 177 #endif // __GSPI_H__ 178
