1 /* 2 * Copyright (c) 2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GPT_RME_PRIVATE_H 8 #define GPT_RME_PRIVATE_H 9 10 #include <arch.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <lib/utils_def.h> 13 14 /******************************************************************************/ 15 /* GPT descriptor definitions */ 16 /******************************************************************************/ 17 18 /* GPT level 0 descriptor bit definitions. */ 19 #define GPT_L0_TYPE_MASK UL(0xF) 20 #define GPT_L0_TYPE_SHIFT U(0) 21 22 /* For now, we don't support contiguous descriptors, only table and block. */ 23 #define GPT_L0_TYPE_TBL_DESC UL(0x3) 24 #define GPT_L0_TYPE_BLK_DESC UL(0x1) 25 26 #define GPT_L0_TBL_DESC_L1ADDR_MASK UL(0xFFFFFFFFFF) 27 #define GPT_L0_TBL_DESC_L1ADDR_SHIFT U(12) 28 29 #define GPT_L0_BLK_DESC_GPI_MASK UL(0xF) 30 #define GPT_L0_BLK_DESC_GPI_SHIFT U(4) 31 32 /* GPT level 1 descriptor bit definitions */ 33 #define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF) 34 35 /* 36 * This macro fills out every GPI entry in a granules descriptor to the same 37 * value. 38 */ 39 #define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \ 40 ((uint64_t)(_gpi) << 4*1) | \ 41 ((uint64_t)(_gpi) << 4*2) | \ 42 ((uint64_t)(_gpi) << 4*3) | \ 43 ((uint64_t)(_gpi) << 4*4) | \ 44 ((uint64_t)(_gpi) << 4*5) | \ 45 ((uint64_t)(_gpi) << 4*6) | \ 46 ((uint64_t)(_gpi) << 4*7) | \ 47 ((uint64_t)(_gpi) << 4*8) | \ 48 ((uint64_t)(_gpi) << 4*9) | \ 49 ((uint64_t)(_gpi) << 4*10) | \ 50 ((uint64_t)(_gpi) << 4*11) | \ 51 ((uint64_t)(_gpi) << 4*12) | \ 52 ((uint64_t)(_gpi) << 4*13) | \ 53 ((uint64_t)(_gpi) << 4*14) | \ 54 ((uint64_t)(_gpi) << 4*15)) 55 56 /******************************************************************************/ 57 /* GPT platform configuration */ 58 /******************************************************************************/ 59 60 /* This value comes from GPCCR_EL3 so no externally supplied definition. */ 61 #define GPT_L0GPTSZ ((unsigned int)((read_gpccr_el3() >> \ 62 GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK)) 63 64 /* The "S" value is directly related to L0GPTSZ */ 65 #define GPT_S_VAL (GPT_L0GPTSZ + 30U) 66 67 /* 68 * Map PPS values to T values. 69 * 70 * PPS Size T 71 * 0b000 4GB 32 72 * 0b001 64GB 36 73 * 0b010 1TB 40 74 * 0b011 4TB 42 75 * 0b100 16TB 44 76 * 0b101 256TB 48 77 * 0b110 4PB 52 78 * 79 * See section 15.1.27 of the RME specification. 80 */ 81 typedef enum { 82 PPS_4GB_T = 32U, 83 PPS_64GB_T = 36U, 84 PPS_1TB_T = 40U, 85 PPS_4TB_T = 42U, 86 PPS_16TB_T = 44U, 87 PPS_256TB_T = 48U, 88 PPS_4PB_T = 52U 89 } gpt_t_val_e; 90 91 /* 92 * Map PGS values to P values. 93 * 94 * PGS Size P 95 * 0b00 4KB 12 96 * 0b10 16KB 14 97 * 0b01 64KB 16 98 * 99 * Note that pgs=0b10 is 16KB and pgs=0b01 is 64KB, this is not a typo. 100 * 101 * See section 15.1.27 of the RME specification. 102 */ 103 typedef enum { 104 PGS_4KB_P = 12U, 105 PGS_16KB_P = 14U, 106 PGS_64KB_P = 16U 107 } gpt_p_val_e; 108 109 /* 110 * Internal structure to retrieve the values from get_gpi_info(); 111 */ 112 typedef struct gpi_info { 113 uint64_t gpt_l1_desc; 114 uint64_t *gpt_l1_addr; 115 unsigned int idx; 116 unsigned int gpi_shift; 117 unsigned int gpi; 118 } gpi_info_t; 119 120 /* Max valid value for PGS. */ 121 #define GPT_PGS_MAX (2U) 122 123 /* Max valid value for PPS. */ 124 #define GPT_PPS_MAX (6U) 125 126 /******************************************************************************/ 127 /* L0 address attribute macros */ 128 /******************************************************************************/ 129 130 /* 131 * Width of the L0 index field. 132 * 133 * If S is greater than or equal to T then there is a single L0 region covering 134 * the entire protected space so there is no L0 index, so the width (and the 135 * derivative mask value) are both zero. If we don't specifically handle this 136 * special case we'll get a negative width value which does not make sense and 137 * would cause problems. 138 */ 139 #define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \ 140 ((_t) - GPT_S_VAL) : (0U)) 141 142 /* Bit shift for the L0 index field in a PA. */ 143 #define GPT_L0_IDX_SHIFT (GPT_S_VAL) 144 145 /* 146 * Mask for the L0 index field, must be shifted. 147 * 148 * The value 0x3FFFFF is 22 bits wide which is the maximum possible width of the 149 * L0 index within a physical address. This is calculated by 150 * ((t_max - 1) - s_min + 1) where t_max is 52 for 4PB, the largest PPS, and 151 * s_min is 30 for 1GB, the smallest L0GPTSZ. 152 */ 153 #define GPT_L0_IDX_MASK(_t) (0x3FFFFFUL >> (22U - \ 154 (GPT_L0_IDX_WIDTH(_t)))) 155 156 /* Total number of L0 regions. */ 157 #define GPT_L0_REGION_COUNT(_t) ((GPT_L0_IDX_MASK(_t)) + 1U) 158 159 /* Total size of each GPT L0 region in bytes. */ 160 #define GPT_L0_REGION_SIZE (1UL << (GPT_L0_IDX_SHIFT)) 161 162 /* Total size in bytes of the whole L0 table. */ 163 #define GPT_L0_TABLE_SIZE(_t) ((GPT_L0_REGION_COUNT(_t)) << 3U) 164 165 /******************************************************************************/ 166 /* L1 address attribute macros */ 167 /******************************************************************************/ 168 169 /* 170 * Width of the L1 index field. 171 * 172 * This field does not have a special case to handle widths less than zero like 173 * the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ 174 * (s) will result in a positive width value. 175 */ 176 #define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U)) 177 178 /* Bit shift for the L1 index field. */ 179 #define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U) 180 181 /* 182 * Mask for the L1 index field, must be shifted. 183 * 184 * The value 0x7FFFFF is 23 bits wide and is the maximum possible width of the 185 * L1 index within a physical address. It is calculated by 186 * ((s_max - 1) - (p_min + 4) + 1) where s_max is 39 for 512gb, the largest 187 * L0GPTSZ, and p_min is 12 for 4KB granules, the smallest PGS. 188 */ 189 #define GPT_L1_IDX_MASK(_p) (0x7FFFFFUL >> (23U - \ 190 (GPT_L1_IDX_WIDTH(_p)))) 191 192 /* Bit shift for the index of the L1 GPI in a PA. */ 193 #define GPT_L1_GPI_IDX_SHIFT(_p) (_p) 194 195 /* Mask for the index of the L1 GPI in a PA. */ 196 #define GPT_L1_GPI_IDX_MASK (0xF) 197 198 /* Total number of entries in each L1 table. */ 199 #define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U) 200 201 /* Total size in bytes of each L1 table. */ 202 #define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U) 203 204 /******************************************************************************/ 205 /* General helper macros */ 206 /******************************************************************************/ 207 208 /* Protected space actual size in bytes. */ 209 #define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t)) 210 211 /* Granule actual size in bytes. */ 212 #define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p)) 213 214 /* L0 GPT region size in bytes. */ 215 #define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL) 216 217 /* Get the index of the L0 entry from a physical address. */ 218 #define GPT_L0_IDX(_pa) ((_pa) >> GPT_L0_IDX_SHIFT) 219 220 /* 221 * This definition is used to determine if a physical address lies on an L0 222 * region boundary. 223 */ 224 #define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0)) 225 226 /* Get the type field from an L0 descriptor. */ 227 #define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \ 228 GPT_L0_TYPE_MASK) 229 230 /* Create an L0 block descriptor. */ 231 #define GPT_L0_BLK_DESC(_gpi) (GPT_L0_TYPE_BLK_DESC | \ 232 (((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \ 233 GPT_L0_BLK_DESC_GPI_SHIFT)) 234 235 /* Create an L0 table descriptor with an L1 table address. */ 236 #define GPT_L0_TBL_DESC(_pa) (GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \ 237 (GPT_L0_TBL_DESC_L1ADDR_MASK << \ 238 GPT_L0_TBL_DESC_L1ADDR_SHIFT))) 239 240 /* Get the GPI from an L0 block descriptor. */ 241 #define GPT_L0_BLKD_GPI(_desc) (((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \ 242 GPT_L0_BLK_DESC_GPI_MASK) 243 244 /* Get the L1 address from an L0 table descriptor. */ 245 #define GPT_L0_TBLD_ADDR(_desc) ((uint64_t *)(((_desc) & \ 246 (GPT_L0_TBL_DESC_L1ADDR_MASK << \ 247 GPT_L0_TBL_DESC_L1ADDR_SHIFT)))) 248 249 /* Get the index into the L1 table from a physical address. */ 250 #define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \ 251 GPT_L1_IDX_MASK(_p)) 252 253 /* Get the index of the GPI within an L1 table entry from a physical address. */ 254 #define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \ 255 GPT_L1_GPI_IDX_MASK) 256 257 /* Determine if an address is granule-aligned. */ 258 #define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \ 259 == U(0)) 260 261 #endif /* GPT_RME_PRIVATE_H */ 262
