1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR5_PCTL.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_GPR5_PCTL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR5_PCTL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR5_PCTL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR5_PCTL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR5_PCTL_Peripheral_Access_Layer GPR5_PCTL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR5_PCTL - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t EDMA5PCTL; /**< eDMA_5 Clock Control Enable, offset: 0x0 */ 74 __IO uint32_t DSPI8PCTL; /**< SPI_8 Clock Control Enable, offset: 0x4 */ 75 __IO uint32_t DSPI9PCTL; /**< SPI_9 Clock Control Enable, offset: 0x8 */ 76 __IO uint32_t LIN9PCTL; /**< LINFlex_9 Clock Control Enable, offset: 0xC */ 77 __IO uint32_t LIN10PCTL; /**< LINFlex_10 Clock Control Enable, offset: 0x10 */ 78 __IO uint32_t LIN11PCTL; /**< LINFlex_11 Clock Control Enable, offset: 0x14 */ 79 __IO uint32_t SIUL5PCTL; /**< SIUL2_5 Clock Control Enable, offset: 0x18 */ 80 } GPR5_PCTL_Type, *GPR5_PCTL_MemMapPtr; 81 82 /** Number of instances of the GPR5_PCTL module. */ 83 #define GPR5_PCTL_INSTANCE_COUNT (1u) 84 85 /* GPR5_PCTL - Peripheral instance base addresses */ 86 /** Peripheral GPR5_PCTL base address */ 87 #define IP_GPR5_PCTL_BASE (0x42810000u) 88 /** Peripheral GPR5_PCTL base pointer */ 89 #define IP_GPR5_PCTL ((GPR5_PCTL_Type *)IP_GPR5_PCTL_BASE) 90 /** Array initializer of GPR5_PCTL peripheral base addresses */ 91 #define IP_GPR5_PCTL_BASE_ADDRS { IP_GPR5_PCTL_BASE } 92 /** Array initializer of GPR5_PCTL peripheral base pointers */ 93 #define IP_GPR5_PCTL_BASE_PTRS { IP_GPR5_PCTL } 94 95 /* ---------------------------------------------------------------------------- 96 -- GPR5_PCTL Register Masks 97 ---------------------------------------------------------------------------- */ 98 99 /*! 100 * @addtogroup GPR5_PCTL_Register_Masks GPR5_PCTL Register Masks 101 * @{ 102 */ 103 104 /*! @name EDMA5PCTL - eDMA_5 Clock Control Enable */ 105 /*! @{ */ 106 107 #define GPR5_PCTL_EDMA5PCTL_PCTL_0_MASK (0x1U) 108 #define GPR5_PCTL_EDMA5PCTL_PCTL_0_SHIFT (0U) 109 #define GPR5_PCTL_EDMA5PCTL_PCTL_0_WIDTH (1U) 110 #define GPR5_PCTL_EDMA5PCTL_PCTL_0(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_EDMA5PCTL_PCTL_0_SHIFT)) & GPR5_PCTL_EDMA5PCTL_PCTL_0_MASK) 111 112 #define GPR5_PCTL_EDMA5PCTL_PCTL_1_MASK (0x2U) 113 #define GPR5_PCTL_EDMA5PCTL_PCTL_1_SHIFT (1U) 114 #define GPR5_PCTL_EDMA5PCTL_PCTL_1_WIDTH (1U) 115 #define GPR5_PCTL_EDMA5PCTL_PCTL_1(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_EDMA5PCTL_PCTL_1_SHIFT)) & GPR5_PCTL_EDMA5PCTL_PCTL_1_MASK) 116 117 #define GPR5_PCTL_EDMA5PCTL_PCTL_2_MASK (0x4U) 118 #define GPR5_PCTL_EDMA5PCTL_PCTL_2_SHIFT (2U) 119 #define GPR5_PCTL_EDMA5PCTL_PCTL_2_WIDTH (1U) 120 #define GPR5_PCTL_EDMA5PCTL_PCTL_2(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_EDMA5PCTL_PCTL_2_SHIFT)) & GPR5_PCTL_EDMA5PCTL_PCTL_2_MASK) 121 122 #define GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK (0x8U) 123 #define GPR5_PCTL_EDMA5PCTL_PCTL_3_SHIFT (3U) 124 #define GPR5_PCTL_EDMA5PCTL_PCTL_3_WIDTH (1U) 125 #define GPR5_PCTL_EDMA5PCTL_PCTL_3(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_EDMA5PCTL_PCTL_3_SHIFT)) & GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK) 126 /*! @} */ 127 128 /*! @name DSPI8PCTL - SPI_8 Clock Control Enable */ 129 /*! @{ */ 130 131 #define GPR5_PCTL_DSPI8PCTL_PCTL_MASK (0x1U) 132 #define GPR5_PCTL_DSPI8PCTL_PCTL_SHIFT (0U) 133 #define GPR5_PCTL_DSPI8PCTL_PCTL_WIDTH (1U) 134 #define GPR5_PCTL_DSPI8PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_DSPI8PCTL_PCTL_SHIFT)) & GPR5_PCTL_DSPI8PCTL_PCTL_MASK) 135 /*! @} */ 136 137 /*! @name DSPI9PCTL - SPI_9 Clock Control Enable */ 138 /*! @{ */ 139 140 #define GPR5_PCTL_DSPI9PCTL_PCTL_MASK (0x1U) 141 #define GPR5_PCTL_DSPI9PCTL_PCTL_SHIFT (0U) 142 #define GPR5_PCTL_DSPI9PCTL_PCTL_WIDTH (1U) 143 #define GPR5_PCTL_DSPI9PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_DSPI9PCTL_PCTL_SHIFT)) & GPR5_PCTL_DSPI9PCTL_PCTL_MASK) 144 /*! @} */ 145 146 /*! @name LIN9PCTL - LINFlex_9 Clock Control Enable */ 147 /*! @{ */ 148 149 #define GPR5_PCTL_LIN9PCTL_PCTL_MASK (0x1U) 150 #define GPR5_PCTL_LIN9PCTL_PCTL_SHIFT (0U) 151 #define GPR5_PCTL_LIN9PCTL_PCTL_WIDTH (1U) 152 #define GPR5_PCTL_LIN9PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_LIN9PCTL_PCTL_SHIFT)) & GPR5_PCTL_LIN9PCTL_PCTL_MASK) 153 /*! @} */ 154 155 /*! @name LIN10PCTL - LINFlex_10 Clock Control Enable */ 156 /*! @{ */ 157 158 #define GPR5_PCTL_LIN10PCTL_PCTL_MASK (0x1U) 159 #define GPR5_PCTL_LIN10PCTL_PCTL_SHIFT (0U) 160 #define GPR5_PCTL_LIN10PCTL_PCTL_WIDTH (1U) 161 #define GPR5_PCTL_LIN10PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_LIN10PCTL_PCTL_SHIFT)) & GPR5_PCTL_LIN10PCTL_PCTL_MASK) 162 /*! @} */ 163 164 /*! @name LIN11PCTL - LINFlex_11 Clock Control Enable */ 165 /*! @{ */ 166 167 #define GPR5_PCTL_LIN11PCTL_PCTL_MASK (0x1U) 168 #define GPR5_PCTL_LIN11PCTL_PCTL_SHIFT (0U) 169 #define GPR5_PCTL_LIN11PCTL_PCTL_WIDTH (1U) 170 #define GPR5_PCTL_LIN11PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_LIN11PCTL_PCTL_SHIFT)) & GPR5_PCTL_LIN11PCTL_PCTL_MASK) 171 /*! @} */ 172 173 /*! @name SIUL5PCTL - SIUL2_5 Clock Control Enable */ 174 /*! @{ */ 175 176 #define GPR5_PCTL_SIUL5PCTL_PCTL_MASK (0x1U) 177 #define GPR5_PCTL_SIUL5PCTL_PCTL_SHIFT (0U) 178 #define GPR5_PCTL_SIUL5PCTL_PCTL_WIDTH (1U) 179 #define GPR5_PCTL_SIUL5PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR5_PCTL_SIUL5PCTL_PCTL_SHIFT)) & GPR5_PCTL_SIUL5PCTL_PCTL_MASK) 180 /*! @} */ 181 182 /*! 183 * @} 184 */ /* end of group GPR5_PCTL_Register_Masks */ 185 186 /*! 187 * @} 188 */ /* end of group GPR5_PCTL_Peripheral_Access_Layer */ 189 190 #endif /* #if !defined(S32Z2_GPR5_PCTL_H_) */ 191
