1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR1_PCTL.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_GPR1_PCTL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR1_PCTL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR1_PCTL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR1_PCTL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR1_PCTL_Peripheral_Access_Layer GPR1_PCTL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR1_PCTL - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t I3C1PCTL; /**< I3C_1 Clock Control Enable, offset: 0x0 */ 74 __IO uint32_t EDMA1PCTL; /**< eDMA_1 Clock Control Enable, offset: 0x4 */ 75 __IO uint32_t DSPI2PCTL; /**< SPI_2 Clock Control Enable, offset: 0x8 */ 76 __IO uint32_t DSPI3PCTL; /**< SPI_3 Clock Control Enable, offset: 0xC */ 77 __IO uint32_t DSPI4PCTL; /**< SPI_4 Clock Control Enable, offset: 0x10 */ 78 __IO uint32_t LIN3PCTL; /**< LINFlex_3 Clock Control Enable, offset: 0x14 */ 79 __IO uint32_t LIN4PCTL; /**< LINFlex_4 Clock Control Enable, offset: 0x18 */ 80 __IO uint32_t LIN5PCTL; /**< LINFlex_5 Clock Control Enable, offset: 0x1C */ 81 __IO uint32_t SIPI0PCTL; /**< SIPI_0 Clock Control Enable, offset: 0x20 */ 82 __IO uint32_t SIPI1PCTL; /**< SIPI_1 Clock Control Enable, offset: 0x24 */ 83 __IO uint32_t SRX0PCTL; /**< SRX_0 Clock Control Enable, offset: 0x28 */ 84 uint8_t RESERVED_0[4]; 85 __IO uint32_t ENET0PCTL; /**< ENET_0 Clock Control Enable, offset: 0x30 */ 86 uint8_t RESERVED_1[4]; 87 __IO uint32_t SIUL1PCTL; /**< SIUL2_1 Clock Control Enable, offset: 0x38 */ 88 } GPR1_PCTL_Type, *GPR1_PCTL_MemMapPtr; 89 90 /** Number of instances of the GPR1_PCTL module. */ 91 #define GPR1_PCTL_INSTANCE_COUNT (1u) 92 93 /* GPR1_PCTL - Peripheral instance base addresses */ 94 /** Peripheral GPR1_PCTL base address */ 95 #define IP_GPR1_PCTL_BASE (0x40810000u) 96 /** Peripheral GPR1_PCTL base pointer */ 97 #define IP_GPR1_PCTL ((GPR1_PCTL_Type *)IP_GPR1_PCTL_BASE) 98 /** Array initializer of GPR1_PCTL peripheral base addresses */ 99 #define IP_GPR1_PCTL_BASE_ADDRS { IP_GPR1_PCTL_BASE } 100 /** Array initializer of GPR1_PCTL peripheral base pointers */ 101 #define IP_GPR1_PCTL_BASE_PTRS { IP_GPR1_PCTL } 102 103 /* ---------------------------------------------------------------------------- 104 -- GPR1_PCTL Register Masks 105 ---------------------------------------------------------------------------- */ 106 107 /*! 108 * @addtogroup GPR1_PCTL_Register_Masks GPR1_PCTL Register Masks 109 * @{ 110 */ 111 112 /*! @name I3C1PCTL - I3C_1 Clock Control Enable */ 113 /*! @{ */ 114 115 #define GPR1_PCTL_I3C1PCTL_PCTL_MASK (0x1U) 116 #define GPR1_PCTL_I3C1PCTL_PCTL_SHIFT (0U) 117 #define GPR1_PCTL_I3C1PCTL_PCTL_WIDTH (1U) 118 #define GPR1_PCTL_I3C1PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_I3C1PCTL_PCTL_SHIFT)) & GPR1_PCTL_I3C1PCTL_PCTL_MASK) 119 /*! @} */ 120 121 /*! @name EDMA1PCTL - eDMA_1 Clock Control Enable */ 122 /*! @{ */ 123 124 #define GPR1_PCTL_EDMA1PCTL_PCTL_0_MASK (0x1U) 125 #define GPR1_PCTL_EDMA1PCTL_PCTL_0_SHIFT (0U) 126 #define GPR1_PCTL_EDMA1PCTL_PCTL_0_WIDTH (1U) 127 #define GPR1_PCTL_EDMA1PCTL_PCTL_0(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_EDMA1PCTL_PCTL_0_SHIFT)) & GPR1_PCTL_EDMA1PCTL_PCTL_0_MASK) 128 129 #define GPR1_PCTL_EDMA1PCTL_PCTL_1_MASK (0x2U) 130 #define GPR1_PCTL_EDMA1PCTL_PCTL_1_SHIFT (1U) 131 #define GPR1_PCTL_EDMA1PCTL_PCTL_1_WIDTH (1U) 132 #define GPR1_PCTL_EDMA1PCTL_PCTL_1(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_EDMA1PCTL_PCTL_1_SHIFT)) & GPR1_PCTL_EDMA1PCTL_PCTL_1_MASK) 133 134 #define GPR1_PCTL_EDMA1PCTL_PCTL_2_MASK (0x4U) 135 #define GPR1_PCTL_EDMA1PCTL_PCTL_2_SHIFT (2U) 136 #define GPR1_PCTL_EDMA1PCTL_PCTL_2_WIDTH (1U) 137 #define GPR1_PCTL_EDMA1PCTL_PCTL_2(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_EDMA1PCTL_PCTL_2_SHIFT)) & GPR1_PCTL_EDMA1PCTL_PCTL_2_MASK) 138 139 #define GPR1_PCTL_EDMA1PCTL_PCTL_3_MASK (0x8U) 140 #define GPR1_PCTL_EDMA1PCTL_PCTL_3_SHIFT (3U) 141 #define GPR1_PCTL_EDMA1PCTL_PCTL_3_WIDTH (1U) 142 #define GPR1_PCTL_EDMA1PCTL_PCTL_3(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_EDMA1PCTL_PCTL_3_SHIFT)) & GPR1_PCTL_EDMA1PCTL_PCTL_3_MASK) 143 /*! @} */ 144 145 /*! @name DSPI2PCTL - SPI_2 Clock Control Enable */ 146 /*! @{ */ 147 148 #define GPR1_PCTL_DSPI2PCTL_PCTL_MASK (0x1U) 149 #define GPR1_PCTL_DSPI2PCTL_PCTL_SHIFT (0U) 150 #define GPR1_PCTL_DSPI2PCTL_PCTL_WIDTH (1U) 151 #define GPR1_PCTL_DSPI2PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_DSPI2PCTL_PCTL_SHIFT)) & GPR1_PCTL_DSPI2PCTL_PCTL_MASK) 152 /*! @} */ 153 154 /*! @name DSPI3PCTL - SPI_3 Clock Control Enable */ 155 /*! @{ */ 156 157 #define GPR1_PCTL_DSPI3PCTL_PCTL_MASK (0x1U) 158 #define GPR1_PCTL_DSPI3PCTL_PCTL_SHIFT (0U) 159 #define GPR1_PCTL_DSPI3PCTL_PCTL_WIDTH (1U) 160 #define GPR1_PCTL_DSPI3PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_DSPI3PCTL_PCTL_SHIFT)) & GPR1_PCTL_DSPI3PCTL_PCTL_MASK) 161 /*! @} */ 162 163 /*! @name DSPI4PCTL - SPI_4 Clock Control Enable */ 164 /*! @{ */ 165 166 #define GPR1_PCTL_DSPI4PCTL_PCTL_MASK (0x1U) 167 #define GPR1_PCTL_DSPI4PCTL_PCTL_SHIFT (0U) 168 #define GPR1_PCTL_DSPI4PCTL_PCTL_WIDTH (1U) 169 #define GPR1_PCTL_DSPI4PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_DSPI4PCTL_PCTL_SHIFT)) & GPR1_PCTL_DSPI4PCTL_PCTL_MASK) 170 /*! @} */ 171 172 /*! @name LIN3PCTL - LINFlex_3 Clock Control Enable */ 173 /*! @{ */ 174 175 #define GPR1_PCTL_LIN3PCTL_PCTL_MASK (0x1U) 176 #define GPR1_PCTL_LIN3PCTL_PCTL_SHIFT (0U) 177 #define GPR1_PCTL_LIN3PCTL_PCTL_WIDTH (1U) 178 #define GPR1_PCTL_LIN3PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_LIN3PCTL_PCTL_SHIFT)) & GPR1_PCTL_LIN3PCTL_PCTL_MASK) 179 /*! @} */ 180 181 /*! @name LIN4PCTL - LINFlex_4 Clock Control Enable */ 182 /*! @{ */ 183 184 #define GPR1_PCTL_LIN4PCTL_PCTL_MASK (0x1U) 185 #define GPR1_PCTL_LIN4PCTL_PCTL_SHIFT (0U) 186 #define GPR1_PCTL_LIN4PCTL_PCTL_WIDTH (1U) 187 #define GPR1_PCTL_LIN4PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_LIN4PCTL_PCTL_SHIFT)) & GPR1_PCTL_LIN4PCTL_PCTL_MASK) 188 /*! @} */ 189 190 /*! @name LIN5PCTL - LINFlex_5 Clock Control Enable */ 191 /*! @{ */ 192 193 #define GPR1_PCTL_LIN5PCTL_PCTL_MASK (0x1U) 194 #define GPR1_PCTL_LIN5PCTL_PCTL_SHIFT (0U) 195 #define GPR1_PCTL_LIN5PCTL_PCTL_WIDTH (1U) 196 #define GPR1_PCTL_LIN5PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_LIN5PCTL_PCTL_SHIFT)) & GPR1_PCTL_LIN5PCTL_PCTL_MASK) 197 /*! @} */ 198 199 /*! @name SIPI0PCTL - SIPI_0 Clock Control Enable */ 200 /*! @{ */ 201 202 #define GPR1_PCTL_SIPI0PCTL_PCTL_MASK (0x1U) 203 #define GPR1_PCTL_SIPI0PCTL_PCTL_SHIFT (0U) 204 #define GPR1_PCTL_SIPI0PCTL_PCTL_WIDTH (1U) 205 #define GPR1_PCTL_SIPI0PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_SIPI0PCTL_PCTL_SHIFT)) & GPR1_PCTL_SIPI0PCTL_PCTL_MASK) 206 /*! @} */ 207 208 /*! @name SIPI1PCTL - SIPI_1 Clock Control Enable */ 209 /*! @{ */ 210 211 #define GPR1_PCTL_SIPI1PCTL_PCTL_MASK (0x1U) 212 #define GPR1_PCTL_SIPI1PCTL_PCTL_SHIFT (0U) 213 #define GPR1_PCTL_SIPI1PCTL_PCTL_WIDTH (1U) 214 #define GPR1_PCTL_SIPI1PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_SIPI1PCTL_PCTL_SHIFT)) & GPR1_PCTL_SIPI1PCTL_PCTL_MASK) 215 /*! @} */ 216 217 /*! @name SRX0PCTL - SRX_0 Clock Control Enable */ 218 /*! @{ */ 219 220 #define GPR1_PCTL_SRX0PCTL_PCTL_MASK (0x1U) 221 #define GPR1_PCTL_SRX0PCTL_PCTL_SHIFT (0U) 222 #define GPR1_PCTL_SRX0PCTL_PCTL_WIDTH (1U) 223 #define GPR1_PCTL_SRX0PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_SRX0PCTL_PCTL_SHIFT)) & GPR1_PCTL_SRX0PCTL_PCTL_MASK) 224 /*! @} */ 225 226 /*! @name ENET0PCTL - ENET_0 Clock Control Enable */ 227 /*! @{ */ 228 229 #define GPR1_PCTL_ENET0PCTL_PCTL_MASK (0x1U) 230 #define GPR1_PCTL_ENET0PCTL_PCTL_SHIFT (0U) 231 #define GPR1_PCTL_ENET0PCTL_PCTL_WIDTH (1U) 232 #define GPR1_PCTL_ENET0PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_ENET0PCTL_PCTL_SHIFT)) & GPR1_PCTL_ENET0PCTL_PCTL_MASK) 233 /*! @} */ 234 235 /*! @name SIUL1PCTL - SIUL2_1 Clock Control Enable */ 236 /*! @{ */ 237 238 #define GPR1_PCTL_SIUL1PCTL_PCTL_MASK (0x1U) 239 #define GPR1_PCTL_SIUL1PCTL_PCTL_SHIFT (0U) 240 #define GPR1_PCTL_SIUL1PCTL_PCTL_WIDTH (1U) 241 #define GPR1_PCTL_SIUL1PCTL_PCTL(x) (((uint32_t)(((uint32_t)(x)) << GPR1_PCTL_SIUL1PCTL_PCTL_SHIFT)) & GPR1_PCTL_SIUL1PCTL_PCTL_MASK) 242 /*! @} */ 243 244 /*! 245 * @} 246 */ /* end of group GPR1_PCTL_Register_Masks */ 247 248 /*! 249 * @} 250 */ /* end of group GPR1_PCTL_Peripheral_Access_Layer */ 251 252 #endif /* #if !defined(S32Z2_GPR1_PCTL_H_) */ 253
