1 /**************************************************************************//** 2 * @file sys_reg.h 3 * @version V3.00 4 * @brief SYS register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SYS_REG_H__ 10 #define __SYS_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 22 /*---------------------- System Manger Controller -------------------------*/ 23 /** 24 @addtogroup SYS System Manger Controller (SYS) 25 Memory Mapped Structure for SYS Controller 26 @{ */ 27 28 typedef struct 29 { 30 31 32 /** 33 * @var SYS_T::PDID 34 * Offset: 0x00 Part Device Identification Number Register 35 * --------------------------------------------------------------------------------------------------- 36 * |Bits |Field |Descriptions 37 * | :----: | :----: | :---- | 38 * |[31:0] |PDID |Part Device Identification Number (Read Only) 39 * | | |This register reflects device part number code. 40 * | | |Software can read this register to identify which device is used. 41 * @var SYS_T::RSTSTS 42 * Offset: 0x04 System Reset Status Register 43 * --------------------------------------------------------------------------------------------------- 44 * |Bits |Field |Descriptions 45 * | :----: | :----: | :---- | 46 * |[0] |PORF |POR Reset Flag 47 * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 48 * | | |0 = No reset from POR or CHIPRST. 49 * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. 50 * | | |Note: Write 1 to clear this bit to 0. 51 * |[1] |PINRF |nRESET Pin Reset Flag 52 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 53 * | | |0 = No reset from nRESET pin. 54 * | | |1 = Pin nRESET had issued the reset signal to reset the system. 55 * | | |Note: Write 1 to clear this bit to 0. 56 * |[2] |WDTRF |WDT Reset Flag 57 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 58 * | | |0 = No reset from watchdog timer or window watchdog timer. 59 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. 60 * | | |Note 1: Write 1 to clear this bit to 0. 61 * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset 62 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 63 * |[3] |LVRF |LVR Reset Flag 64 * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 65 * | | |0 = No reset from LVR. 66 * | | |1 = LVR controller had issued the reset signal to reset the system. 67 * | | |Note: Write 1 to clear this bit to 0. 68 * |[4] |BODRF |BOD Reset Flag 69 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. 70 * | | |0 = No reset from BOD. 71 * | | |1 = The BOD had issued the reset signal to reset the system. 72 * | | |Note: Write 1 to clear this bit to 0. 73 * |[5] |MCURF |MCU Reset Flag 74 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. 75 * | | |0 = No reset from Cortex-M4. 76 * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. 77 * | | |Note: Write 1 to clear this bit to 0. 78 * |[6] |HRESETRF |HRESET Reset Flag 79 * | | |The HRESET reset flag is set by the "Reset Signal" from the HRESET. 80 * | | |0 = No reset from HRESET. 81 * | | |1 = Reset from HRESET. 82 * | | |Note 1: Write 1 to clear this bit to 0. 83 * | | |Note 2: HRESET includes: POR, Reset Pin, LVR, BOD, WDT, WWDT, CPU lock up, CHIP and MCU reset. 84 * |[7] |CPURF |CPU Reset Flag 85 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). 86 * | | |0 = No reset from CPU. 87 * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. 88 * | | |Note: Write 1 to clear this bit to 0. 89 * |[8] |CPULKRF |CPU Lockup Reset Flag 90 * | | |0 = No reset from CPU lockup happened. 91 * | | |1 = The Cortex-M4 lockup happened and chip is reset. 92 * | | |Note 1: Write 1 to clear this bit to 0. 93 * | | |Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset. 94 * @var SYS_T::IPRST0 95 * Offset: 0x08 Peripheral Reset Control Register 0 96 * --------------------------------------------------------------------------------------------------- 97 * |Bits |Field |Descriptions 98 * | :----: | :----: | :---- | 99 * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) 100 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. 101 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. 102 * | | |0 = Chip normal operation. 103 * | | |1 = Chip one-shot reset. 104 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 105 * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) 106 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 107 * | | |0 = Processor core normal operation. 108 * | | |1 = Processor core one-shot reset. 109 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 110 * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) 111 * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 controller. 112 * | | |User needs to set this bit to 0 to release from reset state. 113 * | | |0 = PDMA0 controller normal operation. 114 * | | |1 = PDMA0 controller reset. 115 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 116 * |[3] |EBIRST |EBI Controller Reset (Write Protect) 117 * | | |Set this bit to 1 will generate a reset signal to the EBI controller. 118 * | | |User needs to set this bit to 0 to release from the reset state. 119 * | | |0 = EBI controller normal operation. 120 * | | |1 = EBI controller reset. 121 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 122 * |[5] |EMAC0RST |EMAC0 Controller Reset (Write Protect) 123 * | | |Setting this bit to 1 will generate a reset signal to the EMAC0 controller. 124 * | | |User needs to set this bit to 0 to release from the reset state. 125 * | | |0 = EMAC0 controller normal operation. 126 * | | |1 = EMAC0 controller reset. 127 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 128 * |[6] |SDH0RST |SDH0 Controller Reset (Write Protect) 129 * | | |Setting this bit to 1 will generate a reset signal to the SDH0 controller. 130 * | | |User needs to set this bit to 0 to release from the reset state. 131 * | | |0 = SDH0 controller normal operation. 132 * | | |1 = SDH0 controller reset. 133 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 134 * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) 135 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller. 136 * | | |User needs to set this bit to 0 to release from the reset state. 137 * | | |0 = CRC calculation controller normal operation. 138 * | | |1 = CRC calculation controller reset. 139 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 140 * |[8] |CCAPRST |CCAP Controller Reset (Write Protect) 141 * | | |Set this bit to 1 will generate a reset signal to the CCAP controller. 142 * | | |User needs to set this bit to 0 to release from the reset state. 143 * | | |0 = CCAP controller normal operation. 144 * | | |1 = CCAP controller reset. 145 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 146 * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) 147 * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller. 148 * | | |User needs to set this bit to 0 to release from the reset state. 149 * | | |0 = HSUSBD controller normal operation. 150 * | | |1 = HSUSBD controller reset. 151 * |[11] |HBIRST |HBI Controller Reset (Write Protect) 152 * | | |Setting this bit to 1 will generate a reset signal to the HBI controller. 153 * | | |User needs to set this bit to 0 to release from the reset state. 154 * | | |0 = HBI controller normal operation. 155 * | | |1 = HBI controller reset. 156 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 157 * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) 158 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. 159 * | | |User needs to set this bit to 0 to release from the reset state. 160 * | | |0 = CRYPTO controller normal operation. 161 * | | |1 = CRYPTO controller reset. 162 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 163 * |[13] |KSRST |Key Store Controller Reset (Write Protect) 164 * | | |Setting this bit to 1 will generate a reset signal to the Key Store controller 165 * | | |User needs to set this bit to 0 to release from the reset state. 166 * | | |0 = Key Store controller normal operation. 167 * | | |1 = Key Store controller reset. 168 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 169 * |[14] |SPIMRST |SPIM Controller Reset (Write Protect) 170 * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller. 171 * | | |User needs to set this bit to 0 to release from the reset state. 172 * | | |0 = SPIM controller normal operation. 173 * | | |1 = SPIM controller reset. 174 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 175 * |[16] |HSUSBHRST |HSUSBH Controller Reset (Write Protect) 176 * | | |Set this bit to 1 will generate a reset signal to the HSUSBH controller. 177 * | | |User needs to set this bit to 0 to release from the reset state. 178 * | | |0 = HSUSBH controller normal operation. 179 * | | |1 = HSUSBH controller reset. 180 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 181 * |[17] |SDH1RST |SDH1 Controller Reset (Write Protect) 182 * | | |Setting this bit to 1 will generate a reset signal to the SDH1 controller. 183 * | | |User needs to set this bit to 0 to release from the reset state. 184 * | | |0 = SDH1 controller normal operation. 185 * | | |1 = SDH1 controller reset. 186 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 187 * |[18] |PDMA1RST |PDMA1 Controller Reset (Write Protect) 188 * | | |Setting this bit to 1 will generate a reset signal to the PDMA1 controller. 189 * | | |User needs to set this bit to 0 to release from reset state. 190 * | | |0 = PDMA1 controller normal operation. 191 * | | |1 = PDMA1 controller reset. 192 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 193 * |[20] |CANFD0RST |CANFD0 Controller Reset (Write Protect) 194 * | | |Setting this bit to 1 will generate a reset signal to the CANFD0 controller. 195 * | | |User needs to set this bit to 0 to release from reset state. 196 * | | |0 = CANFD0 controller normal operation. 197 * | | |1 = CANFD0 controller reset. 198 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 199 * |[21] |CANFD1RST |CANFD1 Controller Reset (Write Protect) 200 * | | |Setting this bit to 1 will generate a reset signal to the CANFD1 controller. 201 * | | |User needs to set this bit to 0 to release from reset state. 202 * | | |0 = CANFD1 controller normal operation. 203 * | | |1 = CANFD1 controller reset. 204 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 205 * |[22] |CANFD2RST |CANFD2 Controller Reset (Write Protect) 206 * | | |Setting this bit to 1 will generate a reset signal to the CANFD2 controller. 207 * | | |User needs to set this bit to 0 to release from reset state. 208 * | | |0 = CANFD2 controller normal operation. 209 * | | |1 = CANFD2 controller reset. 210 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 211 * |[23] |CANFD3RST |CANFD3 Controller Reset (Write Protect) 212 * | | |Setting this bit to 1 will generate a reset signal to the CANFD3 controller. 213 * | | |User needs to set this bit to 0 to release from reset state. 214 * | | |0 = CANFD3 controller normal operation. 215 * | | |1 = CANFD3 controller reset. 216 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 217 * |[28] |BMCRST |BMC Controller Reset (Write Protect) 218 * | | |Setting this bit to 1 will generate a reset signal to the BMC controller. 219 * | | |User needs to set this bit to 0 to release from reset state. 220 * | | |0 = BCM controller normal operation. 221 * | | |1 = BMC controller reset. 222 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 223 * @var SYS_T::IPRST1 224 * Offset: 0x0C Peripheral Reset Control Register 1 225 * --------------------------------------------------------------------------------------------------- 226 * |Bits |Field |Descriptions 227 * | :----: | :----: | :---- | 228 * |[1] |GPIORST |GPIO Controller Reset 229 * | | |0 = GPIO controller normal operation. 230 * | | |1 = GPIO controller reset. 231 * |[2] |TMR0RST |Timer0 Controller Reset 232 * | | |0 = Timer0 controller normal operation. 233 * | | |1 = Timer0 controller reset. 234 * |[3] |TMR1RST |Timer1 Controller Reset 235 * | | |0 = Timer1 controller normal operation. 236 * | | |1 = Timer1 controller reset. 237 * |[4] |TMR2RST |Timer2 Controller Reset 238 * | | |0 = Timer2 controller normal operation. 239 * | | |1 = Timer2 controller reset. 240 * |[5] |TMR3RST |Timer3 Controller Reset 241 * | | |0 = Timer3 controller normal operation. 242 * | | |1 = Timer3 controller reset. 243 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset 244 * | | |0 = Analog Comparator 0/1 controller normal operation. 245 * | | |1 = Analog Comparator 0/1 controller reset. 246 * |[8] |I2C0RST |I2C0 Controller Reset 247 * | | |0 = I2C0 controller normal operation. 248 * | | |1 = I2C0 controller reset. 249 * |[9] |I2C1RST |I2C1 Controller Reset 250 * | | |0 = I2C1 controller normal operation. 251 * | | |1 = I2C1 controller reset. 252 * |[10] |I2C2RST |I2C2 Controller Reset 253 * | | |0 = I2C2 controller normal operation. 254 * | | |1 = I2C2 controller reset. 255 * |[11] |I2C3RST |I2C3 Controller Reset 256 * | | |0 = I2C3 controller normal operation. 257 * | | |1 = I2C3 controller reset. 258 * |[12] |QSPI0RST |QSPI0 Controller Reset 259 * | | |0 = QSPI0 controller normal operation. 260 * | | |1 = QSPI0 controller reset. 261 * |[13] |SPI0RST |SPI0 Controller Reset 262 * | | |0 = SPI0 controller normal operation. 263 * | | |1 = SPI0 controller reset. 264 * |[14] |SPI1RST |SPI1 Controller Reset 265 * | | |0 = SPI1 controller normal operation. 266 * | | |1 = SPI1 controller reset. 267 * |[15] |SPI2RST |SPI2 Controller Reset 268 * | | |0 = SPI2 controller normal operation. 269 * | | |1 = SPI2 controller reset. 270 * |[16] |UART0RST |UART0 Controller Reset 271 * | | |0 = UART0 controller normal operation. 272 * | | |1 = UART0 controller reset. 273 * |[17] |UART1RST |UART1 Controller Reset 274 * | | |0 = UART1 controller normal operation. 275 * | | |1 = UART1 controller reset. 276 * |[18] |UART2RST |UART2 Controller Reset 277 * | | |0 = UART2 controller normal operation. 278 * | | |1 = UART2 controller reset. 279 * |[19] |UART3RST |UART3 Controller Reset 280 * | | |0 = UART3 controller normal operation. 281 * | | |1 = UART3 controller reset. 282 * |[20] |UART4RST |UART4 Controller Reset 283 * | | |0 = UART4 controller normal operation. 284 * | | |1 = UART4 controller reset. 285 * |[21] |UART5RST |UART5 Controller Reset 286 * | | |0 = UART5 controller normal operation. 287 * | | |1 = UART5 controller reset. 288 * |[22] |UART6RST |UART6 Controller Reset 289 * | | |0 = UART6 controller normal operation. 290 * | | |1 = UART6 controller reset. 291 * |[23] |UART7RST |UART7 Controller Reset 292 * | | |0 = UART7 controller normal operation. 293 * | | |1 = UART7 controller reset. 294 * |[26] |OTGRST |OTG Controller Reset 295 * | | |0 = OTG controller normal operation. 296 * | | |1 = OTG controller reset. 297 * |[27] |USBDRST |USBD Controller Reset 298 * | | |0 = USBD controller normal operation. 299 * | | |1 = USBD controller reset. 300 * |[28] |EADC0RST |EADC0 Controller Reset 301 * | | |0 = EADC0 controller normal operation. 302 * | | |1 = EADC0 controller reset. 303 * |[29] |I2S0RST |I2S0 Controller Reset 304 * | | |0 = I2S0 controller normal operation. 305 * | | |1 = I2S0 controller reset. 306 * |[30] |HSOTGRST |HSOTG Controller Reset 307 * | | |0 = HSOTG controller normal operation. 308 * | | |1 = HSOTG controller reset. 309 * |[31] |TRNGRST |TRNG Controller Reset 310 * | | |0 = TRNG controller normal operation. 311 * | | |1 = TRNG controller reset. 312 * @var SYS_T::IPRST2 313 * Offset: 0x10 Peripheral Reset Control Register 2 314 * --------------------------------------------------------------------------------------------------- 315 * |Bits |Field |Descriptions 316 * | :----: | :----: | :---- | 317 * |[0] |SC0RST |SC0 Controller Reset 318 * | | |0 = SC0 controller normal operation. 319 * | | |1 = SC0 controller reset. 320 * |[1] |SC1RST |SC1 Controller Reset 321 * | | |0 = SC1 controller normal operation. 322 * | | |1 = SC1 controller reset. 323 * |[2] |SC2RST |SC2 Controller Reset 324 * | | |0 = SC2 controller normal operation. 325 * | | |1 = SC2 controller reset. 326 * |[3] |I2C4RST |I2C4 Controller Reset 327 * | | |0 = I2C4 controller normal operation. 328 * | | |1 = I2C4 controller reset. 329 * |[4] |QSPI1RST |QSPI1 Controller Reset 330 * | | |0 = QSPI1 controller normal operation. 331 * | | |1 = QSPI1 controller reset. 332 * |[6] |SPI3RST |SPI3 Controller Reset 333 * | | |0 = SPI3 controller normal operation. 334 * | | |1 = SPI3 controller reset. 335 * |[7] |SPI4RST |SPI4 Controller Reset 336 * | | |0 = SPI4 controller normal operation. 337 * | | |1 = SPI4 controller reset. 338 * |[8] |USCI0RST |USCI0 Controller Reset 339 * | | |0 = USCI0 controller normal operation. 340 * | | |1 = USCI0 controller reset. 341 * |[10] |PSIORST |PSIO Controller Reset 342 * | | |0 = PSIO controller normal operation. 343 * | | |1 = PSIO controller reset. 344 * |[12] |DACRST |DAC Controller Reset 345 * | | |0 = DAC controller normal operation. 346 * | | |1 = DAC controller reset. 347 * |[13] |ECAP2RST |ECAP2 Controller Reset 348 * | | |0 = ECAP2 controller normal operation. 349 * | | |1 = ECAP2 controller reset. 350 * |[14] |ECAP3RST |ECAP3 Controller Reset 351 * | | |0 = ECAP3 controller normal operation. 352 * | | |1 = ECAP3 controller reset. 353 * |[16] |EPWM0RST |EPWM0 Controller Reset 354 * | | |0 = EPWM0 controller normal operation. 355 * | | |1 = EPWM0 controller reset. 356 * |[17] |EPWM1RST |EPWM1 Controller Reset 357 * | | |0 = EPWM1 controller normal operation. 358 * | | |1 = EPWM1 controller reset. 359 * |[18] |BPWM0RST |BPWM0 Controller Reset 360 * | | |0 = BPWM0 controller normal operation. 361 * | | |1 = BPWM0 controller reset. 362 * |[19] |BPWM1RST |BPWM1 Controller Reset 363 * | | |0 = BPWM1 controller normal operation. 364 * | | |1 = BPWM1 controller reset. 365 * |[20] |EQEI2RST |EQEI2 Controller Reset 366 * | | |0 = EQEI2 controller normal operation. 367 * | | |1 = EQEI2 controller reset. 368 * |[21] |EQEI3RST |EQEI3 Controller Reset 369 * | | |0 = EQEI3 controller normal operation. 370 * | | |1 = EQEI3 controller reset. 371 * |[22] |EQEI0RST |EQEI0 Controller Reset 372 * | | |0 = EQEI0 controller normal operation. 373 * | | |1 = EQEI0 controller reset. 374 * |[23] |EQEI1RST |EQEI1 Controller Reset 375 * | | |0 = EQEI1 controller normal operation. 376 * | | |1 = EQEI1 controller reset. 377 * |[26] |ECAP0RST |ECAP0 Controller Reset 378 * | | |0 = ECAP0 controller normal operation. 379 * | | |1 = ECAP0 controller reset. 380 * |[27] |ECAP1RST |ECAP1 Controller Reset 381 * | | |0 = ECAP1 controller normal operation. 382 * | | |1 = ECAP1 controller reset. 383 * |[29] |I2S1RST |I2S1 Controller Reset 384 * | | |0 = I2S1 controller normal operation. 385 * | | |1 = I2S1 controller reset. 386 * |[31] |EADC1RST |EADC1 Controller Reset 387 * | | |0 = EADC1 controller normal operation. 388 * | | |1 = EADC1 controller reset. 389 * @var SYS_T::BODCTL 390 * Offset: 0x18 Brown-out Detector Control Register 391 * --------------------------------------------------------------------------------------------------- 392 * |Bits |Field |Descriptions 393 * | :----: | :----: | :---- | 394 * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) 395 * | | |The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). 396 * | | |0 = Brown-out Detector function Disabled. 397 * | | |1 = Brown-out Detector function Enabled. 398 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 399 * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) 400 * | | |The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit. 401 * | | |0 = Brown-out "INTERRUPT" function Enabled. 402 * | | |1 = Brown-out "RESET" function Enabled. 403 * | | |Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). 404 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODIF is high. 405 * | | |BOD interrupt will keep till the BODIF set to 0. 406 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). 407 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 408 * |[4] |BODIF |Brown-out Detector Interrupt Flag 409 * | | |0 = Brown-out Detector does not detect any voltage draft at AVDD down through or up through the voltage of BODVL setting. 410 * | | |1 = When Brown-out Detector detects the AVDD is dropped down through the voltage of BODVL setting or the AVDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. 411 * | | |Note: Write 1 to clear this bit to 0. 412 * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) 413 * | | |0 = BOD operate in normal mode (default). 414 * | | |1 = BOD Low Power mode Enabled. 415 * | | |Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 416 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 417 * |[6] |BODOUT |Brown-out Detector Output Status 418 * | | |0 = Brown-out Detector output status is 0. 419 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. 420 * | | |1 = Brown-out Detector output status is 1. 421 * | | |It means the detected voltage is lower than BODVL setting 422 * | | |If the BODEN is 0, BOD function disabled, this bit always responds 0. 423 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) 424 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. 425 * | | |0 = Low Voltage Reset function Disabled (default). 426 * | | |1 = Low Voltage Reset function Enabled. 427 * | | |Note 1: After enabling the bit, the LVR function will be active with 100us ~ 200us delay for LVR output stable. 428 * | | |LVRRDY(SYS_BODCTL[15]) is used to indicate LVR ready status. 429 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 430 * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) 431 * | | |000 = BOD output is sampled by LIRC clock. 432 * | | |001 = 4 system clock (HCLK). 433 * | | |010 = 8 system clock (HCLK). 434 * | | |011 = 16 system clock (HCLK). 435 * | | |100 = 32 system clock (HCLK). 436 * | | |101 = 64 system clock (HCLK). 437 * | | |110 = 128 system clock (HCLK). 438 * | | |111 = 256 system clock (HCLK). 439 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 440 * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) 441 * | | |000 = Without de-glitch function. 442 * | | |001 = 4 system clock (HCLK). 443 * | | |010 = 8 system clock (HCLK). 444 * | | |011 = 16 system clock (HCLK). 445 * | | |100 = 32 system clock (HCLK). 446 * | | |101 = 64 system clock (HCLK). 447 * | | |110 = 128 system clock (HCLK). 448 * | | |111 = 256 system clock (HCLK). 449 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 450 * |[15] |LVRRDY |Low Voltage Reset Ready Flag (Read Only) 451 * | | |When the LVR function first enable, need more HCLK to wait LVR ready. 452 * | | |0 = Low Voltage Reset function not ready. 453 * | | |1 = Low Voltage Reset function ready. 454 * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) 455 * | | |The default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]). 456 * | | |000 = Brown-Out Detector threshold voltage is 1.6V. 457 * | | |001 = Brown-Out Detector threshold voltage is 1.8V. 458 * | | |010 = Brown-Out Detector threshold voltage is 2.0V. 459 * | | |011 = Brown-Out Detector threshold voltage is 2.2V. 460 * | | |100 = Brown-Out Detector threshold voltage is 2.4V. 461 * | | |101 = Brown-Out Detector threshold voltage is 2.6V. 462 * | | |110 = Brown-Out Detector threshold voltage is 2.8V. 463 * | | |111 = Brown-Out Detector threshold voltage is 3.0V. 464 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 465 * @var SYS_T::IVSCTL 466 * Offset: 0x1C Internal Voltage Source Control Register 467 * --------------------------------------------------------------------------------------------------- 468 * |Bits |Field |Descriptions 469 * | :----: | :----: | :---- | 470 * |[0] |VTEMPEN |Temperature Sensor Enable Bit 471 * | | |This bit is used to enable/disable temperature sensor function. 472 * | | |0 = Temperature sensor function Disabled (default). 473 * | | |1 = Temperature sensor function Enabled. 474 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit 475 * | | |This bit is used to enable/disable VBAT unity gain buffer function. 476 * | | |0 = VBAT unity gain buffer function Disabled (default). 477 * | | |1 = VBAT unity gain buffer function Enabled. 478 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result 479 * @var SYS_T::IPRST3 480 * Offset: 0x20 Peripheral Reset Control Register 3 481 * --------------------------------------------------------------------------------------------------- 482 * |Bits |Field |Descriptions 483 * | :----: | :----: | :---- | 484 * |[0] |KPIRST |KPI Controller Reset 485 * | | |0 = KPI controller normal operation. 486 * | | |1 = KPI controller reset. 487 * |[6] |EADC2RST |EADC2 Controller Reset 488 * | | |0 = EADC2 controller normal operation. 489 * | | |1 = EADC2 controller reset. 490 * |[7] |ACMP23RST |Analog Comparator 2/3 Controller Reset 491 * | | |0 = Analog Comparator 2/3 controller normal operation. 492 * | | |1 = Analog Comparator 2/3 controller reset. 493 * |[8] |SPI5RST |SPI5 Controller Reset 494 * | | |0 = SPI5 controller normal operation. 495 * | | |1 = SPI5 controller reset. 496 * |[9] |SPI6RST |SPI6 Controller Reset 497 * | | |0 = SPI6 controller normal operation. 498 * | | |1 = SPI6 controller reset. 499 * |[10] |SPI7RST |SPI7 Controller Reset 500 * | | |0 = SPI7 controller normal operation. 501 * | | |1 = SPI7 controller reset. 502 * |[11] |SPI8RST |SPI8 Controller Reset 503 * | | |0 = SPI8 controller normal operation. 504 * | | |1 = SPI8 controller reset. 505 * |[12] |SPI9RST |SPI9 Controller Reset 506 * | | |0 = SPI9 controller normal operation. 507 * | | |1 = SPI9 controller reset. 508 * |[13] |SPI10RST |SPI10 Controller Reset 509 * | | |0 = SPI10 controller normal operation. 510 * | | |1 = SPI10 controller reset. 511 * |[16] |UART8RST |UART8 Controller Reset 512 * | | |0 = UART8 controller normal operation. 513 * | | |1 = UART8 controller reset. 514 * |[17] |UART9RST |UART9 Controller Reset 515 * | | |0 = UART9 controller normal operation. 516 * | | |1 = UART9 controller reset. 517 * @var SYS_T::PORCTL 518 * Offset: 0x24 Power-On-reset Controller Register 519 * --------------------------------------------------------------------------------------------------- 520 * |Bits |Field |Descriptions 521 * | :----: | :----: | :---- | 522 * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) 523 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. 524 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 525 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 526 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 527 * | | |Note 1: Need to disable LVR by setting LVREN(SYS_BODCTL[7]) to 0 when setting POROFF(SYS_PORCTL[15:0]) to 0x5AA5. 528 * | | |Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. 529 * @var SYS_T::VREFCTL 530 * Offset: 0x28 VREF Control Register 531 * --------------------------------------------------------------------------------------------------- 532 * |Bits |Field |Descriptions 533 * | :----: | :----: | :---- | 534 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) 535 * | | |00000 = VREF is from external pin. 536 * | | |00011 = VREF is internal 1.6V. 537 * | | |00111 = VREF is internal 2.0V. 538 * | | |01011 = VREF is internal 2.5V. 539 * | | |01111 = VREF is internal 3.0V. 540 * | | |Others = Reserved. 541 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 542 * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect) 543 * | | |00 = pre-load time is 60us for 0.1uF Capacitor. 544 * | | |01 = pre-load time is 310us for 1uF Capacitor. 545 * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. 546 * | | |11 = pre-load time is 2650us for 10uF Capacitor. 547 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 548 * |[24] |VBGFEN |Chip Internal Voltage Bandgap Force Enable Bit (Write Protect) 549 * | | |0 = Chip internal voltage bandgap controlled by ADC/ACMP if source selected. 550 * | | |1 = Chip internal voltage bandgap force enable. 551 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 552 * |[26:25] |VBGISEL |Chip Internal Voltage Bandgap Current Selection Bits (Write Protect) 553 * | | |00 = Bandgap voltage buffer current is 4.2uA. 554 * | | |01 = Bandgap voltage buffer current is 7.3uA. 555 * | | |10 = Bandgap voltage buffer current is 10.4uA. 556 * | | |11 = Bandgap voltage buffer current is 13.5uA. 557 * | | |Note 1: When ADC conversion source select bandgap voltage, suggest set VBGISEL as 10. 558 * | | |Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. 559 * @var SYS_T::USBPHY 560 * Offset: 0x2C USB PHY Control Register 561 * --------------------------------------------------------------------------------------------------- 562 * |Bits |Field |Descriptions 563 * | :----: | :----: | :---- | 564 * |[1:0] |USBROLE |USB Role Option (Write Protect) 565 * | | |These two bits are used to select the role of USB. 566 * | | |00 = Standard USB Device mode. 567 * | | |01 = Standard USB Host mode. 568 * | | |10 = ID dependent mode. 569 * | | |11 = On-The-Go device mode. 570 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 571 * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable. 572 * |[8] |USBEN |USB PHY Enable 573 * | | |This bit is used to enable/disable USB PHY. 574 * | | |0 = USB PHY Disabled. 575 * | | |1 = USB PHY Enabled. 576 * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) 577 * | | |These two bits are used to select the role of HSUSB. 578 * | | |00 = Standard HSUSB Device mode. 579 * | | |01 = Standard HSUSB Host mode. 580 * | | |10 = ID dependent mode. 581 * | | |11 = On-The-Go device mode. 582 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 583 * |[24] |HSUSBEN |HSUSB PHY Enable 584 * | | |This bit is used to enable/disable HSUSB PHY. 585 * | | |0 = HSUSB PHY Disabled. 586 * | | |1 = HSUSB PHY Enabled. 587 * |[25] |HSUSBACT |HSUSB PHY Active Control 588 * | | |This bit is used to control HSUSB PHY at reset state or active state. 589 * | | |0 = HSUSB PHY at reset state. 590 * | | |1 = HSUSB PHY at active state. 591 * | | |Note: After setting HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10us before changing to active mode. 592 * @var SYS_T::GPA_MFOS 593 * Offset: 0x80-0xA4 GPIOA-GPIOJ Multiple Function Output Select Register 594 * --------------------------------------------------------------------------------------------------- 595 * |Bits |Field |Descriptions 596 * | :----: | :----: | :---- | 597 * |[n] |MFOSn |GPIOA-J Pin[n] Multiple Function Pin Output Mode Select 598 * | | |This bit used to select multiple function pin output mode type for Px.n pin. 599 * | | |0 = Multiple function pin output mode type is Push-pull mode. 600 * | | |1 = Multiple function pin output mode type is Open-drain mode. 601 * | | |Note: 602 * | | |Max. n=15 for port A/B/E/G/H. 603 * | | |Max. n=14 for port C/D. 604 * | | |Max. n=11 for port F. 605 * | | |n=6~15 for port I. 606 * | | |Max. n=13 for port J. 607 * @var SYS_T::SRAM_INTCTL 608 * Offset: 0xC0 System SRAM Interrupt Enable Control Register 609 * --------------------------------------------------------------------------------------------------- 610 * |Bits |Field |Descriptions 611 * | :----: | :----: | :---- | 612 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit 613 * | | |0 = SRAM parity check error interrupt Disabled. 614 * | | |1 = SRAM parity check error interrupt Enabled. 615 * @var SYS_T::SRAM_STATUS 616 * Offset: 0xC4 System SRAM Parity Error Status Register 617 * --------------------------------------------------------------------------------------------------- 618 * |Bits |Field |Descriptions 619 * | :----: | :----: | :---- | 620 * |[0] |PERRIF |SRAM Parity Check Error Flag 621 * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 622 * | | |0 = No System SRAM parity error. 623 * | | |1 = System SRAM parity error occur. 624 * @var SYS_T::SRAM_ERRADDR 625 * Offset: 0xC8 System SRAM Parity Check Error Address Register 626 * --------------------------------------------------------------------------------------------------- 627 * |Bits |Field |Descriptions 628 * | :----: | :----: | :---- | 629 * |[31:0] |ERRADDR |System SRAM Parity Error Address (Read Only) 630 * | | |This register shows system SRAM parity error byte address. 631 * @var SYS_T::SRAM_BISTCTL 632 * Offset: 0xD0 System SRAM BIST Test Control Register 633 * --------------------------------------------------------------------------------------------------- 634 * |Bits |Field |Descriptions 635 * | :----: | :----: | :---- | 636 * |[0] |SRBIST0 |System SRAM Bank0 BIST Enable Bit (Write Protect) 637 * | | |This bit enables BIST test for system SRAM bank0. 638 * | | |0 = System SRAM bank0 BIST Disabled. 639 * | | |1 = System SRAM bank0 BIST Enabled. 640 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 641 * |[1] |SRBIST1 |System SRAM Bank1 BIST Enable Bit (Write Protect) 642 * | | |This bit enables BIST test for system SRAM bank1. 643 * | | |0 = System SRAM bank1 BIST Disabled. 644 * | | |1 = System SRAM bank1 BIST Enabled. 645 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 646 * |[2] |CRBIST |CACHE SRAM BIST Enable Bit (Write Protect) 647 * | | |This bit enables BIST test for CACHE SRAM. 648 * | | |0 = CACHE SRAM BIST Disabled. 649 * | | |1 = CACHE SRAM BIST Enabled. 650 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 651 * |[3] |CANBIST |CAN SRAM BIST Enable Bit (Write Protect) 652 * | | |This bit enables BIST test for CAN SRAM. 653 * | | |0 = CAN SRAM BIST Disabled. 654 * | | |1 = CAN SRAM BIST Enabled. 655 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 656 * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) 657 * | | |This bit enables BIST test for USB SRAM. 658 * | | |0 = USB SRAM BIST Disabled. 659 * | | |1 = USB SRAM BIST Enabled. 660 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 661 * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) 662 * | | |This bit enables BIST test for SPIM SRAM. 663 * | | |0 = SPIM SRAM BIST Disabled. 664 * | | |1 = SPIM SRAM BIST Enabled. 665 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 666 * |[6] |EMAC0BIST |EMAC0 BIST Enable Bit (Write Protect) 667 * | | |This bit enables BIST test for EMAC0 SRAM. 668 * | | |0 = EMAC0 SRAM BIST Disabled. 669 * | | |1 = EMAC0 SRAM BIST Enabled. 670 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 671 * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) 672 * | | |This bit enables BIST test for HSUSBD SRAM. 673 * | | |0 = HSUSBD SRAM BIST Disabled. 674 * | | |1 = HSUSBD SRAM BIST Enabled. 675 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 676 * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) 677 * | | |This bit enables BIST test for HSUSBH SRAM. 678 * | | |0 = HSUSBH SRAM BIST Disabled. 679 * | | |1 = HSUSBH SRAM BIST Enabled. 680 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 681 * |[10] |SRBIST2 |System SRAM Bank2 BIST Enable Bit (Write Protect) 682 * | | |This bit enables BIST test for system SRAM bank2. 683 * | | |0 = System SRAM bank2 BIST Disabled. 684 * | | |1 = System SRAM bank2 BIST Enabled. 685 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 686 * |[11] |KSBIST |Key Store SRAM BIST Enable Bit (Write Protect) 687 * | | |This bit enables BIST test for Key Store SRAM. 688 * | | |0 = Key Store SRAM BIST Disabled. 689 * | | |1 = Key Store SRAM BIST Enabled. 690 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 691 * |[12] |CCAPBIST |CCAP SRAM BIST Enable Bit (Write Protect) 692 * | | |This bit enables BIST test for CCAP SRAM. 693 * | | |0 = CCAP SRAM BIST Disabled. 694 * | | |1 = CCAP SRAM BIST Enabled. 695 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 696 * |[13] |RSABIST |RSA SRAM BIST Enable Bit (Write Protect) 697 * | | |This bit enables BIST test for RSA SRAM. 698 * | | |0 = RSA SRAM BIST Disabled. 699 * | | |1 = RSA SRAM BIST Enabled. 700 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 701 * @var SYS_T::SRAM_BISTSTS 702 * Offset: 0xD4 System SRAM BIST Test Status Register 703 * --------------------------------------------------------------------------------------------------- 704 * |Bits |Field |Descriptions 705 * | :----: | :----: | :---- | 706 * |[0] |SRBISTEF0 |System SRAM Bank0 BIST Fail Flag (Read Only) 707 * | | |0 = System SRAM bank0 BIST test pass. 708 * | | |1 = System SRAM bank0 BIST test fail. 709 * |[1] |SRBISTEF1 |System System Bank1 SRAM BIST Fail Flag (Read Only) 710 * | | |0 = System SRAM bank1 BIST test pass. 711 * | | |1 = System SRAM bank1 BIST test fail. 712 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag (Read Only) 713 * | | |0 = CACHE SRAM BIST test pass. 714 * | | |1 = CACHE SRAM BIST test fail. 715 * |[3] |CANBEF |CAN SRAM BIST Fail Flag (Read Only) 716 * | | |0 = CAN SRAM BIST test pass. 717 * | | |1 = CAN SRAM BIST test fail. 718 * | | |Note: Any of the CAN SRAM macros BIST fail, this flag is 1. 719 * |[4] |USBBEF |USB SRAM BIST Fail Flag (Read Only) 720 * | | |0 = USB SRAM BIST test pass. 721 * | | |1 = USB SRAM BIST test fail. 722 * |[5] |SPIMBEF |SPIM SRAM BIST Fail Flag (Read Only) 723 * | | |0 = SPIM SRAM BIST test pass. 724 * | | |1 = SPIM SRAM BIST test fail. 725 * |[6] |EMAC0BEF |EMAC0 SRAM BIST Fail Flag (Read Only) 726 * | | |0 = EMAC0 SRAM BIST test pass. 727 * | | |1 = EMAC0 SRAM BIST test fail. 728 * |[8] |HSUSBDBEF |HSUSBD SRAM BIST Fail Flag (Read Only) 729 * | | |0 = HSUSBD SRAM BIST test pass. 730 * | | |1 = HSUSBD SRAM BIST test fail. 731 * |[9] |HSUSBHBEF |HSUSBH BIST Fail Flag (Read Only) 732 * | | |0 = HSUSBH SRAM BIST test pass. 733 * | | |1 = HSUSBH SRAM BIST test fail. 734 * |[10] |SRBISTEF2 |System SRAM Bank2 BIST Fail Flag (Read Only) 735 * | | |0 = System SRAM bank2 BIST test pass. 736 * | | |1 = System SRAM bank2 BIST test fail. 737 * |[11] |KSBISTEF |Key Store SRAM BIST Fail Flag (Read Only) 738 * | | |0 = Key Store SRAM BIST test pass. 739 * | | |1 = Key Store SRAM BIST test fail. 740 * |[12] |CCAPBISTEF|CCAP BIST Fail Flag (Read Only) 741 * | | |0 = CCAP BIST test pass. 742 * | | |1 = CCAP BIST test fail. 743 * |[13] |RSABISTE |RSA SRAM BIST Fail Flag (Read Only) 744 * | | |0 = RSA SRAM BIST test pass. 745 * | | |1 = RSA SRAM BIST test fail. 746 * |[16] |SRBEND0 |System SRAM Bank0 BIST Test Finish (Read Only) 747 * | | |0 = System SRAM bank0 BIST active. 748 * | | |1 = System SRAM bank0 BIST finish. 749 * |[17] |SRBEND1 |System SRAM Bank1 BIST Test Finish (Read Only) 750 * | | |0 = System SRAM bank1 BIST is active. 751 * | | |1 = System SRAM bank1 BIST finish. 752 * |[18] |CRBEND |CACHE SRAM BIST Test Finish (Read Only) 753 * | | |0 = CACHE SRAM BIST is active. 754 * | | |1 = CACHE SRAM BIST test finish. 755 * |[19] |CANBEND |CAN SRAM BIST Test Finish (Read Only) 756 * | | |0 = CAN SRAM BIST is active. 757 * | | |1 = CAN SRAM BIST test finish. 758 * | | |Note: All of the CAN SRAM macros BIST finish, this flag is 1. 759 * |[20] |USBBEND |USB SRAM BIST Test Finish 760 * | | |0 = USB SRAM BIST is active. (Read Only) 761 * | | |1 = USB SRAM BIST test finish. 762 * |[21] |SPIMBEND |SPIM SRAM BIST Test Finish (Read Only) 763 * | | |0 = SPIM SRAM BIST is active. 764 * | | |1 = SPIM SRAM BIST test finish. 765 * |[22] |EMAC0BEND |EMAC0 SRAM BIST Test Finish (Read Only) 766 * | | |0 = EMAC0 SRAM BIST is active. 767 * | | |1 = EMAC0 SRAM BIST test finish. 768 * |[24] |HSUSBDBEND|HSUSBD BIST Test Finish (Read Only) 769 * | | |0 = HSUSBD SRAM BIST is active. 770 * | | |1 = HSUSBD SRAM BIST test finish. 771 * |[25] |HSUSBHBEND|HSUSBH BIST Test Finish (Read Only) 772 * | | |0 = HSUSBH SRAM BIST is active. 773 * | | |1 = HSUSBH SRAM BIST test finish. 774 * |[26] |SRBEND2 |System SRAM Bank2 BIST Test Finish (Read Only) 775 * | | |0 = System SRAM bank2 BIST is active. 776 * | | |1 = System SRAM bank2 BIST finish. 777 * |[27] |KSBEND |Key Store SRAM BIST Test Finish (Read Only) 778 * | | |0 = Key Store SRAM BIST is active. 779 * | | |1 = Key Store SRAM BIST test finish. 780 * |[28] |CCAPBEND |CCAP SRAM BIST Test Finish (Read Only) 781 * | | |0 = CCAP SRAM BIST is active. 782 * | | |1 = CCAP SRAM BIST test finish. 783 * |[29] |RSABEND |RSA SRAM BIST Test Finish (Read Only) 784 * | | |0 = RSA SRAM BIST is active. 785 * | | |1 = RSA SRAM BIST test finish. 786 * @var SYS_T::HIRCTCTL 787 * Offset: 0xE4 HIRC48M Trim Control Register 788 * --------------------------------------------------------------------------------------------------- 789 * |Bits |Field |Descriptions 790 * | :----: | :----: | :---- | 791 * |[1:0] |FREQSEL |Trim Frequency Selection 792 * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48M) auto trim. 793 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 794 * | | |00 = Disable HIRC auto trim function. 795 * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 796 * | | |10 = Reserved. 797 * | | |11 = Reserved. 798 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 799 * | | |This field defines that trim value calculation is based on how many reference clocks. 800 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 801 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 802 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 803 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 804 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 805 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 806 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 807 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 808 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still does not lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 809 * | | |00 = Trim retry count limitation is 64 loops. 810 * | | |01 = Trim retry count limitation is 128 loops. 811 * | | |10 = Trim retry count limitation is 256 loops. 812 * | | |11 = Trim retry count limitation is 512 loops. 813 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 814 * | | |0 = The trim operation is keep going if clock is inaccuracy. 815 * | | |1 = The trim operation is stopped if clock is inaccuracy. 816 * |[9] |BOUNDEN |Boundary Enable Bit 817 * | | |0 = Boundary function Disabled. 818 * | | |1 = Boundary function Enabled. 819 * |[10] |REFCKSEL |Reference Clock Selection 820 * | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). 821 * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. 822 * | | |Note: HIRC trim reference clock is 20 kHz in test mode. 823 * |[20:16] |BOUNDARY |Boundary Selection 824 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 825 * | | |Note: This field is effective only when the BOUNDEN(SYS_HIRCTCTL[9]) is enabled. 826 * @var SYS_T::HIRCTIEN 827 * Offset: 0xE8 HIRC48M Trim Interrupt Enable Register 828 * --------------------------------------------------------------------------------------------------- 829 * |Bits |Field |Descriptions 830 * | :----: | :----: | :---- | 831 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 832 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]). 833 * | | |If this bit is high and TFAILIF(SYS_HIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 834 * | | |0 = Disable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. 835 * | | |1 = Enable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. 836 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 837 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 838 * | | |If this bit is set to1, and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 839 * | | |0 = Disable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. 840 * | | |1 = Enable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. 841 * @var SYS_T::HIRCTISTS 842 * Offset: 0xEC HIRC48M Trim Interrupt Status Register 843 * --------------------------------------------------------------------------------------------------- 844 * |Bits |Field |Descriptions 845 * | :----: | :----: | :---- | 846 * |[0] |FREQLOCK |HIRC Frequency Lock Status 847 * | | |This bit indicates the HIRC frequency is locked. 848 * | | |This is a status bit and does not trigger any interrupt. 849 * | | |Write 1 to clear this to 0. 850 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 851 * | | |0 = The internal high-speed oscillator frequency does not lock at 48 MHz yet. 852 * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. 853 * |[1] |TFAILIF |Trim Failure Interrupt Status 854 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still does not be locked. 855 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 856 * | | |If this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 857 * | | |Write 1 to clear this to 0. 858 * | | |0 = Trim value update limitation count does not reach. 859 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 860 * |[2] |CLKERRIF |Clock Error Interrupt Status 861 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC48M) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. 862 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1. 863 * | | |If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 864 * | | |Write 1 to clear this to 0. 865 * | | |0 = Clock frequency is accuracy. 866 * | | |1 = Clock frequency is inaccuracy. 867 * |[3] |OVBDIF |Over Boundary Status 868 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 869 * | | |0 = Over boundary condition did not occur. 870 * | | |1 = Over boundary condition occurred. 871 * | | |Note: Write 1 to clear this flag. 872 * @var SYS_T::IRCTCTL 873 * Offset: 0xF0 HIRC Trim Control Register 874 * --------------------------------------------------------------------------------------------------- 875 * |Bits |Field |Descriptions 876 * | :----: | :----: | :---- | 877 * |[1:0] |FREQSEL |Trim Frequency Selection 878 * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. 879 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 880 * | | |00 = Disable HIRC auto trim function. 881 * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 882 * | | |10 = Reserved. 883 * | | |11 = Reserved. 884 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 885 * | | |This field defines that trim value calculation is based on how many reference clocks. 886 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 887 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 888 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 889 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 890 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 891 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 892 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 893 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 894 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still does not lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 895 * | | |00 = Trim retry count limitation is 64 loops. 896 * | | |01 = Trim retry count limitation is 128 loops. 897 * | | |10 = Trim retry count limitation is 256 loops. 898 * | | |11 = Trim retry count limitation is 512 loops. 899 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 900 * | | |0 = The trim operation is keep going if clock is inaccuracy. 901 * | | |1 = The trim operation is stopped if clock is inaccuracy. 902 * |[9] |BOUNDEN |Boundary Enable Bit 903 * | | |0 = Boundary function Disabled. 904 * | | |1 = Boundary function Enabled. 905 * |[10] |REFCKSEL |Reference Clock Selection 906 * | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). 907 * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. 908 * | | |Note: HIRC trim reference clock is 20 kHz in test mode. 909 * |[20:16] |BOUNDARY |Boundary Selection 910 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 911 * | | |Note: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled. 912 * @var SYS_T::IRCTIEN 913 * Offset: 0xF4 HIRC Trim Interrupt Enable Register 914 * --------------------------------------------------------------------------------------------------- 915 * |Bits |Field |Descriptions 916 * | :----: | :----: | :---- | 917 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 918 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). 919 * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 920 * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 921 * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 922 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 923 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 924 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 925 * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 926 * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 927 * @var SYS_T::IRCTISTS 928 * Offset: 0xF8 HIRC Trim Interrupt Status Register 929 * --------------------------------------------------------------------------------------------------- 930 * |Bits |Field |Descriptions 931 * | :----: | :----: | :---- | 932 * |[0] |FREQLOCK |HIRC Frequency Lock Status 933 * | | |This bit indicates the HIRC frequency is locked. 934 * | | |This is a status bit and does not trigger any interrupt. 935 * | | |Write 1 to clear this to 0. 936 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 937 * | | |0 = The internal high-speed oscillator frequency does not lock at 12 MHz yet. 938 * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. 939 * |[1] |TFAILIF |Trim Failure Interrupt Status 940 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still does not be locked. 941 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 942 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 943 * | | |Write 1 to clear this to 0. 944 * | | |0 = Trim value update limitation count does not reach. 945 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 946 * |[2] |CLKERRIF |Clock Error Interrupt Status 947 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. 948 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. 949 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 950 * | | |Write 1 to clear this to 0. 951 * | | |0 = Clock frequency is accuracy. 952 * | | |1 = Clock frequency is inaccuracy. 953 * |[3] |OVBDIF |Over Boundary Status 954 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 955 * | | |0 = Over boundary condition did not occur. 956 * | | |1 = Over boundary condition occurred. 957 * | | |Note: Write 1 to clear this flag. 958 * @var SYS_T::REGLCTL 959 * Offset: 0x100 Register Lock Control Register 960 * --------------------------------------------------------------------------------------------------- 961 * |Bits |Field |Descriptions 962 * | :----: | :----: | :---- | 963 * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) 964 * | | |Some registers have write-protection function. 965 * | | |Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. 966 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 967 * | | |REGLCTL[0] 968 * | | |Register Lock Control Disable Index (Read Only) 969 * | | |0 = Write-protection Enabled for writing protected registers. Any write to the protected register is ignored. 970 * | | |1 = Write-protection Disabled for writing protected registers. 971 * @var SYS_T::PORDISAN 972 * Offset: 0x1EC Analog POR Disable Control Register 973 * --------------------------------------------------------------------------------------------------- 974 * |Bits |Field |Descriptions 975 * | :----: | :----: | :---- | 976 * |[15:0] |POROFFAN |Power-on Reset Enable Bit (Write Protect) 977 * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. 978 * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: 979 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 980 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 981 * @var SYS_T::CSERVER 982 * Offset: 0x1F4 Chip Series Version Register 983 * --------------------------------------------------------------------------------------------------- 984 * |Bits |Field |Descriptions 985 * | :----: | :----: | :---- | 986 * |[7:0] |VERSION |Chip Series Version (Read Only) 987 * | | |These bits indicate the series version of chip. 988 * | | |0x02 = M46xxI/M46xxJ. 989 * | | |0x03 = M46xxG. 990 * | | |Others = Reserved. 991 * @var SYS_T::PLCTL 992 * Offset: 0x1F8 Power Level Control Register 993 * --------------------------------------------------------------------------------------------------- 994 * |Bits |Field |Descriptions 995 * | :----: | :----: | :---- | 996 * |[1:0] |PLSEL |Power Level Select (Write Protect) 997 * | | |These bits set power level status. 998 * | | |00 = Power level is PL0. 999 * | | |01 = Power level is PL1. 1000 * | | |Others = Reserved. 1001 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1002 * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect) 1003 * | | |The LVSSTEP value is LDO voltage rising step. 1004 * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV. 1005 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1006 * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect) 1007 * | | |The LVSPRD value is the period of each LDO voltage rising step. 1008 * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. 1009 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1010 * @var SYS_T::PLSTS 1011 * Offset: 0x1FC Power Level Status Register 1012 * --------------------------------------------------------------------------------------------------- 1013 * |Bits |Field |Descriptions 1014 * | :----: | :----: | :---- | 1015 * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) 1016 * | | |This bit is set by hardware when power level is changing. 1017 * | | |After power level change is completed, this bit will be cleared automatically by hardware. 1018 * | | |0 = Power level change is completed. 1019 * | | |1 = Power level change is ongoing. 1020 * |[9:8] |PLSTATUS |Power Level Status (Read Only) 1021 * | | |These bits indicate the status of power level. 1022 * | | |00 = Power level is PL0. 1023 * | | |01 = Power level is PL1. 1024 * | | |Others = Reserved. 1025 * @var SYS_T::AHBMCTL 1026 * Offset: 0x400 AHB Bus Matrix Priority Control Register 1027 * --------------------------------------------------------------------------------------------------- 1028 * |Bits |Field |Descriptions 1029 * | :----: | :----: | :---- | 1030 * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect) 1031 * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix. 1032 * | | |0 = Round-robin mode. 1033 * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. 1034 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1035 * @var SYS_T::GPA_MFP0 1036 * Offset: 0x500 GPIOA Multiple Function Control Register 0 1037 * --------------------------------------------------------------------------------------------------- 1038 * |Bits |Field |Descriptions 1039 * | :----: | :----: | :---- | 1040 * |[4:0] |PA0MFP |PA.0 Multi-function Pin Selection 1041 * | | |00 = GPIO 1042 * | | |02 = SPIM_MOSI 1043 * | | |03 = QSPI0_MOSI0 1044 * | | |04 = SPI0_MOSI 1045 * | | |05 = SD1_DAT0 1046 * | | |06 = SC0_CLK 1047 * | | |07 = UART0_RXD 1048 * | | |08 = UART1_nRTS 1049 * | | |09 = I2C2_SDA 1050 * | | |10 = CCAP_DATA6 1051 * | | |12 = BPWM0_CH0 1052 * | | |13 = EPWM0_CH5 1053 * | | |14 = EQEI3_B 1054 * | | |15 = DAC0_ST 1055 * | | |17 = PSIO0_CH7 1056 * | | |20 = BMC19 1057 * |[12:8] |PA1MFP |PA.1 Multi-function Pin Selection 1058 * | | |00 = GPIO 1059 * | | |02 = SPIM_MISO 1060 * | | |03 = QSPI0_MISO0 1061 * | | |04 = SPI0_MISO 1062 * | | |05 = SD1_DAT1 1063 * | | |06 = SC0_DAT 1064 * | | |07 = UART0_TXD 1065 * | | |08 = UART1_nCTS 1066 * | | |09 = I2C2_SCL 1067 * | | |10 = CCAP_DATA7 1068 * | | |12 = BPWM0_CH1 1069 * | | |13 = EPWM0_CH4 1070 * | | |14 = EQEI3_A 1071 * | | |15 = DAC1_ST 1072 * | | |17 = PSIO0_CH6 1073 * | | |20 = BMC18 1074 * |[20:16] |PA2MFP |PA.2 Multi-function Pin Selection 1075 * | | |00 = GPIO 1076 * | | |02 = SPIM_CLK 1077 * | | |03 = QSPI0_CLK 1078 * | | |04 = SPI0_CLK 1079 * | | |05 = SD1_DAT2 1080 * | | |06 = SC0_RST 1081 * | | |07 = UART4_RXD 1082 * | | |08 = UART1_RXD 1083 * | | |09 = I2C1_SDA 1084 * | | |10 = I2C0_SMBSUS 1085 * | | |12 = BPWM0_CH2 1086 * | | |13 = EPWM0_CH3 1087 * | | |14 = EQEI3_INDEX 1088 * | | |17 = PSIO0_CH5 1089 * | | |20 = BMC17 1090 * |[28:24] |PA3MFP |PA.3 Multi-function Pin Selection 1091 * | | |00 = GPIO 1092 * | | |02 = SPIM_SS 1093 * | | |03 = QSPI0_SS 1094 * | | |04 = SPI0_SS 1095 * | | |05 = SD1_DAT3 1096 * | | |06 = SC0_PWR 1097 * | | |07 = UART4_TXD 1098 * | | |08 = UART1_TXD 1099 * | | |09 = I2C1_SCL 1100 * | | |10 = I2C0_SMBAL 1101 * | | |12 = BPWM0_CH3 1102 * | | |13 = EPWM0_CH2 1103 * | | |14 = EQEI0_B 1104 * | | |15 = EPWM1_BRAKE1 1105 * | | |17 = PSIO0_CH4 1106 * | | |20 = BMC16 1107 * @var SYS_T::GPA_MFP1 1108 * Offset: 0x504 GPIOA Multiple Function Control Register 1 1109 * --------------------------------------------------------------------------------------------------- 1110 * |Bits |Field |Descriptions 1111 * | :----: | :----: | :---- | 1112 * |[4:0] |PA4MFP |PA.4 Multi-function Pin Selection 1113 * | | |00 = GPIO 1114 * | | |02 = SPIM_D3 1115 * | | |03 = QSPI0_MOSI1 1116 * | | |04 = SPI0_I2SMCLK 1117 * | | |05 = SD1_CLK 1118 * | | |06 = SC0_nCD 1119 * | | |07 = UART0_nRTS 1120 * | | |08 = UART5_RXD 1121 * | | |09 = I2C0_SDA 1122 * | | |10 = CAN0_RXD 1123 * | | |11 = UART0_RXD 1124 * | | |12 = BPWM0_CH4 1125 * | | |13 = EPWM0_CH1 1126 * | | |14 = EQEI0_A 1127 * |[12:8] |PA5MFP |PA.5 Multi-function Pin Selection 1128 * | | |00 = GPIO 1129 * | | |02 = SPIM_D2 1130 * | | |03 = QSPI0_MISO1 1131 * | | |04 = SPI1_I2SMCLK 1132 * | | |05 = SD1_CMD 1133 * | | |06 = SC2_nCD 1134 * | | |07 = UART0_nCTS 1135 * | | |08 = UART5_TXD 1136 * | | |09 = I2C0_SCL 1137 * | | |10 = CAN0_TXD 1138 * | | |11 = UART0_TXD 1139 * | | |12 = BPWM0_CH5 1140 * | | |13 = EPWM0_CH0 1141 * | | |14 = EQEI0_INDEX 1142 * |[20:16] |PA6MFP |PA.6 Multi-function Pin Selection 1143 * | | |00 = GPIO 1144 * | | |02 = EBI_AD6 1145 * | | |03 = EMAC0_RMII_RXERR 1146 * | | |04 = SPI1_SS 1147 * | | |05 = SD1_nCD 1148 * | | |06 = SC2_CLK 1149 * | | |07 = UART0_RXD 1150 * | | |08 = I2C1_SDA 1151 * | | |09 = QSPI1_MOSI1 1152 * | | |11 = EPWM1_CH5 1153 * | | |12 = BPWM1_CH3 1154 * | | |13 = ACMP1_WLAT 1155 * | | |14 = TM3 1156 * | | |15 = INT0 1157 * | | |17 = SPI5_CLK 1158 * | | |18 = KPI_COL0 1159 * | | |19 = SPI6_CLK 1160 * | | |20 = BMC15 1161 * |[28:24] |PA7MFP |PA.7 Multi-function Pin Selection 1162 * | | |00 = GPIO 1163 * | | |02 = EBI_AD7 1164 * | | |03 = EMAC0_RMII_CRSDV 1165 * | | |04 = SPI1_CLK 1166 * | | |06 = SC2_DAT 1167 * | | |07 = UART0_TXD 1168 * | | |08 = I2C1_SCL 1169 * | | |09 = QSPI1_MISO1 1170 * | | |11 = EPWM1_CH4 1171 * | | |12 = BPWM1_CH2 1172 * | | |13 = ACMP0_WLAT 1173 * | | |14 = TM2 1174 * | | |15 = INT1 1175 * | | |17 = SPI5_SS 1176 * | | |18 = KPI_COL1 1177 * | | |19 = SPI6_SS 1178 * | | |20 = BMC14 1179 * @var SYS_T::GPA_MFP2 1180 * Offset: 0x508 GPIOA Multiple Function Control Register 2 1181 * --------------------------------------------------------------------------------------------------- 1182 * |Bits |Field |Descriptions 1183 * | :----: | :----: | :---- | 1184 * |[4:0] |PA8MFP |PA.8 Multi-function Pin Selection 1185 * | | |00 = GPIO 1186 * | | |01 = EADC1_CH4, EADC2_CH4 1187 * | | |02 = EBI_ALE 1188 * | | |03 = SC2_CLK 1189 * | | |04 = SPI2_MOSI 1190 * | | |05 = SD1_DAT0 1191 * | | |06 = USCI0_CTL1 1192 * | | |07 = UART1_RXD 1193 * | | |08 = UART7_RXD 1194 * | | |09 = BPWM0_CH3 1195 * | | |10 = EQEI1_B 1196 * | | |11 = ECAP0_IC2 1197 * | | |12 = I2S1_DO 1198 * | | |13 = TM3_EXT 1199 * | | |15 = INT4 1200 * | | |20 = BMC9 1201 * |[12:8] |PA9MFP |PA.9 Multi-function Pin Selection 1202 * | | |00 = GPIO 1203 * | | |01 = EADC1_CH5, EADC2_CH5 1204 * | | |02 = EBI_MCLK 1205 * | | |03 = SC2_DAT 1206 * | | |04 = SPI2_MISO 1207 * | | |05 = SD1_DAT1 1208 * | | |06 = USCI0_DAT1 1209 * | | |07 = UART1_TXD 1210 * | | |08 = UART7_TXD 1211 * | | |09 = BPWM0_CH2 1212 * | | |10 = EQEI1_A 1213 * | | |11 = ECAP0_IC1 1214 * | | |12 = I2S1_DI 1215 * | | |13 = TM2_EXT 1216 * | | |15 = SWDH_DAT (for M46xxI/M46xxJ) 1217 * | | |20 = BMC8 1218 * |[20:16] |PA10MFP |PA.10 Multi-function Pin Selection 1219 * | | |00 = GPIO 1220 * | | |01 = EADC1_CH6, EADC2_CH6, ACMP1_P0 1221 * | | |02 = EBI_nWR 1222 * | | |03 = SC2_RST 1223 * | | |04 = SPI2_CLK 1224 * | | |05 = SD1_DAT2 1225 * | | |06 = USCI0_DAT0 1226 * | | |07 = I2C2_SDA 1227 * | | |08 = UART6_RXD 1228 * | | |09 = BPWM0_CH1 1229 * | | |10 = EQEI1_INDEX 1230 * | | |11 = ECAP0_IC0 1231 * | | |12 = I2S1_MCLK 1232 * | | |13 = TM1_EXT 1233 * | | |14 = DAC0_ST 1234 * | | |15 = SWDH_CLK (for M46xxI/M46xxJ) 1235 * | | |18 = KPI_ROW5 1236 * | | |20 = BMC7 1237 * |[28:24] |PA11MFP |PA.11 Multi-function Pin Selection 1238 * | | |00 = GPIO 1239 * | | |01 = EADC1_CH7, EADC2_CH7, ACMP0_P0 1240 * | | |02 = EBI_nRD 1241 * | | |03 = SC2_PWR 1242 * | | |04 = SPI2_SS 1243 * | | |05 = SD1_DAT3 1244 * | | |06 = USCI0_CLK 1245 * | | |07 = I2C2_SCL 1246 * | | |08 = UART6_TXD 1247 * | | |09 = BPWM0_CH0 1248 * | | |10 = EPWM0_SYNC_OUT 1249 * | | |12 = I2S1_BCLK 1250 * | | |13 = TM0_EXT 1251 * | | |14 = DAC1_ST 1252 * | | |18 = KPI_ROW4 1253 * | | |20 = BMC6 1254 * @var SYS_T::GPA_MFP3 1255 * Offset: 0x50C GPIOA Multiple Function Control Register 3 1256 * --------------------------------------------------------------------------------------------------- 1257 * |Bits |Field |Descriptions 1258 * | :----: | :----: | :---- | 1259 * |[4:0] |PA12MFP |PA.12 Multi-function Pin Selection 1260 * | | |00 = GPIO 1261 * | | |02 = I2S0_BCLK 1262 * | | |03 = UART4_TXD 1263 * | | |04 = I2C1_SCL 1264 * | | |05 = SPI2_SS 1265 * | | |06 = CAN0_TXD 1266 * | | |07 = SC2_PWR 1267 * | | |08 = SD1_nCD 1268 * | | |09 = SPI0_SS (for M46xxG) 1269 * | | |10 = QSPI1_MISO0 1270 * | | |11 = BPWM1_CH2 1271 * | | |12 = EQEI1_INDEX 1272 * | | |13 = ECAP3_IC0 1273 * | | |14 = USB_VBUS 1274 * | | |17 = PSIO0_CH4 1275 * | | |19 = SPI10_SS 1276 * | | |20 = BMC12 1277 * |[12:8] |PA13MFP |PA.13 Multi-function Pin Selection 1278 * | | |00 = GPIO 1279 * | | |02 = I2S0_MCLK 1280 * | | |03 = UART4_RXD 1281 * | | |04 = I2C1_SDA 1282 * | | |05 = SPI2_CLK 1283 * | | |06 = CAN0_RXD 1284 * | | |07 = SC2_RST 1285 * | | |09 = SPI0_CLK (for M46xxG) 1286 * | | |10 = QSPI1_MOSI0 1287 * | | |11 = BPWM1_CH3 1288 * | | |12 = EQEI1_A 1289 * | | |13 = ECAP3_IC1 1290 * | | |14 = USB_D- 1291 * | | |17 = PSIO0_CH5 1292 * | | |19 = SPI10_CLK 1293 * | | |20 = BMC13 1294 * |[20:16] |PA14MFP |PA.14 Multi-function Pin Selection 1295 * | | |00 = GPIO 1296 * | | |02 = I2S0_DI 1297 * | | |03 = UART0_TXD 1298 * | | |04 = EBI_AD5 1299 * | | |05 = SPI2_MISO 1300 * | | |06 = I2C2_SCL 1301 * | | |07 = SC2_DAT 1302 * | | |09 = SPI0_MISO (for M46xxG) 1303 * | | |11 = BPWM1_CH4 1304 * | | |12 = EQEI1_B 1305 * | | |13 = ECAP3_IC2 1306 * | | |14 = USB_D+ 1307 * | | |16 = I2C0_SCL (for M46xxG) 1308 * | | |17 = PSIO0_CH6 1309 * | | |19 = SPI10_MISO 1310 * | | |20 = BMC14 1311 * |[28:24] |PA15MFP |PA.15 Multi-function Pin Selection 1312 * | | |00 = GPIO 1313 * | | |02 = I2S0_DO 1314 * | | |03 = UART0_RXD 1315 * | | |04 = SPIM_MOSI 1316 * | | |05 = SPI2_MOSI 1317 * | | |06 = I2C2_SDA 1318 * | | |07 = SC2_CLK 1319 * | | |09 = SPI0_MOSI (for M46xxG) 1320 * | | |11 = BPWM1_CH5 1321 * | | |12 = EPWM0_SYNC_IN 1322 * | | |13 = EQEI3_INDEX 1323 * | | |14 = USB_OTG_ID 1324 * | | |16 = I2C0_SDA (for M46xxG) 1325 * | | |17 = PSIO0_CH7 1326 * | | |19 = SPI10_MOSI 1327 * | | |20 = BMC15 1328 * @var SYS_T::GPB_MFP0 1329 * Offset: 0x510 GPIOB Multiple Function Control Register 0 1330 * --------------------------------------------------------------------------------------------------- 1331 * |Bits |Field |Descriptions 1332 * | :----: | :----: | :---- | 1333 * |[4:0] |PB0MFP |PB.0 Multi-function Pin Selection 1334 * | | |00 = GPIO 1335 * | | |01 = EADC0_CH0, EADC1_CH8, EADC2_CH8, ACMP3_N 1336 * | | |02 = EBI_ADR9 1337 * | | |03 = SD0_CMD 1338 * | | |04 = SPI2_I2SMCLK 1339 * | | |06 = USCI0_CTL0 1340 * | | |07 = UART2_RXD 1341 * | | |08 = SPI0_I2SMCLK 1342 * | | |09 = I2C1_SDA 1343 * | | |10 = I2S1_LRCK 1344 * | | |11 = EPWM0_CH5 1345 * | | |12 = EPWM1_CH5 1346 * | | |13 = EPWM0_BRAKE1 1347 * | | |14 = ACMP3_O 1348 * | | |15 = QSPI0_MOSI1 1349 * | | |18 = KPI_ROW3 1350 * | | |19 = SPI4_MOSI 1351 * | | |20 = BMC5 1352 * |[12:8] |PB1MFP |PB.1 Multi-function Pin Selection 1353 * | | |00 = GPIO 1354 * | | |01 = EADC0_CH1, EADC1_CH9, EADC2_CH9, ACMP3_P0 1355 * | | |02 = EBI_ADR8 1356 * | | |03 = SD0_CLK 1357 * | | |04 = EMAC_RMII_RXERR 1358 * | | |05 = SPI1_I2SMCLK 1359 * | | |06 = SPI3_I2SMCLK 1360 * | | |07 = UART2_TXD 1361 * | | |09 = I2C1_SCL 1362 * | | |10 = I2S0_LRCK 1363 * | | |11 = EPWM0_CH4 1364 * | | |12 = EPWM1_CH4 1365 * | | |13 = EPWM0_BRAKE0 1366 * | | |14 = ACMP2_O 1367 * | | |15 = QSPI0_MISO1 1368 * | | |18 = KPI_ROW2 1369 * | | |19 = SPI4_MISO 1370 * | | |20 = BMC4 1371 * |[20:16] |PB2MFP |PB.2 Multi-function Pin Selection 1372 * | | |00 = GPIO 1373 * | | |01 = EADC0_CH2, EADC1_CH10, ACMP0_P1 1374 * | | |02 = EBI_ADR3 1375 * | | |03 = SD0_DAT0 1376 * | | |04 = EMAC0_RMII_CRSDV 1377 * | | |05 = SPI1_SS 1378 * | | |06 = UART1_RXD 1379 * | | |07 = UART5_nCTS 1380 * | | |09 = SC0_PWR 1381 * | | |10 = I2S0_DO 1382 * | | |11 = EPWM0_CH3 1383 * | | |12 = I2C1_SDA 1384 * | | |14 = TM3 1385 * | | |15 = INT3 1386 * | | |17 = PSIO0_CH7 1387 * | | |18 = KPI_ROW1 1388 * | | |19 = SPI4_CLK 1389 * | | |20 = BMC3 1390 * |[28:24] |PB3MFP |PB.3 Multi-function Pin Selection 1391 * | | |00 = GPIO 1392 * | | |01 = EADC0_CH3, EADC1_CH11, ACMP0_N 1393 * | | |02 = EBI_ADR2 1394 * | | |03 = SD0_DAT1 1395 * | | |04 = EMAC0_RMII_RXD1 1396 * | | |05 = SPI1_CLK 1397 * | | |06 = UART1_TXD 1398 * | | |07 = UART5_nRTS 1399 * | | |09 = SC0_RST 1400 * | | |10 = I2S0_DI 1401 * | | |11 = EPWM0_CH2 1402 * | | |12 = I2C1_SCL 1403 * | | |14 = TM2 1404 * | | |15 = INT2 1405 * | | |17 = PSIO0_CH6 1406 * | | |18 = KPI_ROW0 1407 * | | |19 = SPI4_SS 1408 * | | |20 = BMC2 1409 * @var SYS_T::GPB_MFP1 1410 * Offset: 0x514 GPIOB Multiple Function Control Register 1 1411 * --------------------------------------------------------------------------------------------------- 1412 * |Bits |Field |Descriptions 1413 * | :----: | :----: | :---- | 1414 * |[4:0] |PB4MFP |PB.4 Multi-function Pin Selection 1415 * | | |00 = GPIO 1416 * | | |01 = EADC0_CH4, ACMP1_P1 1417 * | | |02 = EBI_ADR1 1418 * | | |03 = SD0_DAT2 1419 * | | |04 = EMAC0_RMII_RXD0 1420 * | | |05 = SPI1_MOSI 1421 * | | |06 = I2C0_SDA 1422 * | | |07 = UART5_RXD 1423 * | | |09 = SC0_DAT 1424 * | | |10 = I2S0_MCLK 1425 * | | |11 = EPWM0_CH1 1426 * | | |12 = UART2_RXD 1427 * | | |14 = TM1 1428 * | | |15 = INT1 1429 * | | |17 = PSIO0_CH5 1430 * | | |18 = KPI_COL7 1431 * | | |20 = BMC1 1432 * |[12:8] |PB5MFP |PB.5 Multi-function Pin Selection 1433 * | | |00 = GPIO 1434 * | | |01 = EADC0_CH5, ACMP1_N 1435 * | | |02 = EBI_ADR0 1436 * | | |03 = SD0_DAT3 1437 * | | |04 = EMAC0_RMII_REFCLK 1438 * | | |05 = SPI1_MISO 1439 * | | |06 = I2C0_SCL 1440 * | | |07 = UART5_TXD 1441 * | | |09 = SC0_CLK 1442 * | | |10 = I2S0_BCLK 1443 * | | |11 = EPWM0_CH0 1444 * | | |12 = UART2_TXD 1445 * | | |14 = TM0 1446 * | | |15 = INT0 1447 * | | |17 = PSIO0_CH4 1448 * | | |18 = KPI_COL6 1449 * | | |20 = BMC0 1450 * |[20:16] |PB6MFP |PB.6 Multi-function Pin Selection 1451 * | | |00 = GPIO 1452 * | | |01 = EADC0_CH6, EADC2_CH14, ACMP2_N 1453 * | | |02 = EBI_nWRH 1454 * | | |03 = EMAC0_PPS 1455 * | | |05 = CAN1_RXD 1456 * | | |06 = UART1_RXD 1457 * | | |07 = SD1_CLK 1458 * | | |08 = EBI_nCS1 1459 * | | |10 = BPWM1_CH5 1460 * | | |11 = EPWM1_BRAKE1 1461 * | | |12 = EPWM1_CH5 1462 * | | |13 = INT4 1463 * | | |14 = USB_VBUS_EN 1464 * | | |15 = ACMP1_O 1465 * | | |16 = SPI3_MOSI (for M46xxG) 1466 * | | |18 = KPI_COL5 1467 * | | |19 = SPI1_SS 1468 * | | |20 = BMC31 1469 * |[28:24] |PB7MFP |PB.7 Multi-function Pin Selection 1470 * | | |00 = GPIO 1471 * | | |01 = EADC0_CH7, EADC2_CH15, ACMP2_P0 1472 * | | |02 = EBI_nWRL 1473 * | | |03 = EMAC0_RMII_TXEN 1474 * | | |05 = CAN1_TXD 1475 * | | |06 = UART1_TXD 1476 * | | |07 = SD1_CMD 1477 * | | |08 = EBI_nCS0 1478 * | | |10 = BPWM1_CH4 1479 * | | |11 = EPWM1_BRAKE0 1480 * | | |12 = EPWM1_CH4 1481 * | | |13 = INT5 1482 * | | |14 = USB_VBUS_ST 1483 * | | |15 = ACMP0_O 1484 * | | |16 = SPI3_MISO (for M46xxG) 1485 * | | |18 = KPI_COL4 1486 * | | |19 = SPI1_CLK (for M46xxG) 1487 * | | |20 = BMC30 1488 * @var SYS_T::GPB_MFP2 1489 * Offset: 0x518 GPIOB Multiple Function Control Register 2 1490 * --------------------------------------------------------------------------------------------------- 1491 * |Bits |Field |Descriptions 1492 * | :----: | :----: | :---- | 1493 * |[4:0] |PB8MFP |PB.8 Multi-function Pin Selection 1494 * | | |00 = GPIO 1495 * | | |01 = EADC0_CH8, ACMP2_P1 1496 * | | |02 = EBI_ADR19 1497 * | | |03 = EMAC0_RMII_TXD1 1498 * | | |05 = UART0_RXD 1499 * | | |06 = UART1_nRTS 1500 * | | |07 = I2C1_SMBSUS 1501 * | | |08 = UART7_RXD 1502 * | | |09 = I2C0_SDA 1503 * | | |10 = BPWM1_CH3 1504 * | | |11 = SPI3_MOSI 1505 * | | |12 = CAN2_RXD 1506 * | | |13 = INT6 1507 * | | |14 = EADC2_ST 1508 * | | |20 = BMC23 1509 * |[12:8] |PB9MFP |PB.9 Multi-function Pin Selection 1510 * | | |00 = GPIO 1511 * | | |01 = EADC0_CH9, ACMP2_P2 1512 * | | |02 = EBI_ADR18 1513 * | | |03 = EMAC0_RMII_TXD0 1514 * | | |05 = UART0_TXD 1515 * | | |06 = UART1_nCTS 1516 * | | |07 = I2C1_SMBAL 1517 * | | |08 = UART7_TXD 1518 * | | |09 = I2C0_SCL 1519 * | | |10 = BPWM1_CH2 1520 * | | |11 = SPI3_MISO 1521 * | | |12 = CAN2_TXD 1522 * | | |13 = INT7 1523 * | | |14 = CCAP_HSYNC 1524 * | | |20 = BMC22 1525 * |[20:16] |PB10MFP |PB.10 Multi-function Pin Selection 1526 * | | |00 = GPIO 1527 * | | |01 = EADC0_CH10, ACMP2_P3 1528 * | | |02 = EBI_ADR17 1529 * | | |03 = EMAC0_RMII_MDIO 1530 * | | |05 = UART0_nRTS 1531 * | | |06 = UART4_RXD 1532 * | | |07 = I2C1_SDA 1533 * | | |08 = CAN0_RXD 1534 * | | |10 = BPWM1_CH1 1535 * | | |11 = SPI3_SS 1536 * | | |12 = CCAP_VSYNC 1537 * | | |14 = HSUSB_VBUS_EN 1538 * | | |20 = BMC21 1539 * |[28:24] |PB11MFP |PB.11 Multi-function Pin Selection 1540 * | | |00 = GPIO 1541 * | | |01 = EADC0_CH11 1542 * | | |02 = EBI_ADR16 1543 * | | |03 = EMAC0_RMII_MDC 1544 * | | |05 = UART0_nCTS 1545 * | | |06 = UART4_TXD 1546 * | | |07 = I2C1_SCL 1547 * | | |08 = CAN0_TXD 1548 * | | |09 = SPI0_I2SMCLK 1549 * | | |10 = BPWM1_CH0 1550 * | | |11 = SPI3_CLK 1551 * | | |12 = CCAP_SFIELD 1552 * | | |14 = HSUSB_VBUS_ST 1553 * | | |20 = BMC20 1554 * @var SYS_T::GPB_MFP3 1555 * Offset: 0x51C GPIOB Multiple Function Control Register 3 1556 * --------------------------------------------------------------------------------------------------- 1557 * |Bits |Field |Descriptions 1558 * | :----: | :----: | :---- | 1559 * |[4:0] |PB12MFP |PB.12 Multi-function Pin Selection 1560 * | | |00 = GPIO 1561 * | | |01 = EADC0_CH12, EADC1_CH12, DAC0_OUT, ACMP0_P2, ACMP1_P2 1562 * | | |02 = EBI_AD15 1563 * | | |03 = SC1_CLK 1564 * | | |04 = SPI0_MOSI 1565 * | | |05 = USCI0_CLK 1566 * | | |06 = UART0_RXD 1567 * | | |07 = UART3_nCTS 1568 * | | |08 = I2C2_SDA 1569 * | | |09 = SD0_nCD 1570 * | | |10 = CCAP_SCLK 1571 * | | |11 = EPWM1_CH3 1572 * | | |12 = ETMC_TRACE_DATA3 (for M46xxI/M46xxJ) 1573 * | | |13 = TM3_EXT 1574 * | | |14 = CAN3_RXD 1575 * | | |16 = SPI3_SS (for M46xxG) 1576 * | | |17 = PSIO0_CH3 1577 * | | |18 = KPI_COL3 1578 * | | |20 = BMC29 1579 * |[12:8] |PB13MFP |PB.13 Multi-function Pin Selection 1580 * | | |00 = GPIO 1581 * | | |01 = EADC0_CH13, EADC1_CH13, DAC1_OUT, ACMP0_P3, ACMP1_P3 1582 * | | |02 = EBI_AD14 1583 * | | |03 = SC1_DAT 1584 * | | |04 = SPI0_MISO 1585 * | | |05 = USCI0_DAT0 1586 * | | |06 = UART0_TXD 1587 * | | |07 = UART3_nRTS 1588 * | | |08 = I2C2_SCL 1589 * | | |10 = CCAP_PIXCLK 1590 * | | |11 = EPWM1_CH2 1591 * | | |12 = ETMC_TRACE_DATA2 (for M46xxI/M46xxJ) 1592 * | | |13 = TM2_EXT 1593 * | | |14 = CAN3_TXD 1594 * | | |16 = SPI3_CLK (for M46xxG) 1595 * | | |17 = PSIO0_CH2 1596 * | | |18 = KPI_COL2 1597 * | | |19 = SPI9_MISO 1598 * | | |20 = BMC28 1599 * |[20:16] |PB14MFP |PB.14 Multi-function Pin Selection 1600 * | | |00 = GPIO 1601 * | | |01 = EADC0_CH14, EADC1_CH14 1602 * | | |02 = EBI_AD13 1603 * | | |03 = SC1_RST 1604 * | | |04 = SPI0_CLK 1605 * | | |05 = USCI0_DAT1 1606 * | | |06 = UART0_nRTS 1607 * | | |07 = UART3_RXD 1608 * | | |08 = I2C2_SMBSUS 1609 * | | |09 = CCAP_DATA0 1610 * | | |11 = EPWM1_CH1 1611 * | | |12 = ETMC_TRACE_DATA1 (for M46xxI/M46xxJ) 1612 * | | |13 = TM1_EXT 1613 * | | |14 = CLKO 1614 * | | |15 = USB_VBUS_ST 1615 * | | |17 = PSIO0_CH1 1616 * | | |18 = KPI_COL1 1617 * | | |19 = SPI9_SS 1618 * |[28:24] |PB15MFP |PB.15 Multi-function Pin Selection 1619 * | | |00 = GPIO 1620 * | | |01 = EADC0_CH15, EADC1_CH15 1621 * | | |02 = EBI_AD12 1622 * | | |03 = SC1_PWR 1623 * | | |04 = SPI0_SS 1624 * | | |05 = USCI0_CTL1 1625 * | | |06 = UART0_nCTS 1626 * | | |07 = UART3_TXD 1627 * | | |08 = I2C2_SMBAL 1628 * | | |09 = CCAP_DATA1 1629 * | | |10 = EPWM0_BRAKE1 1630 * | | |11 = EPWM1_CH0 1631 * | | |12 = ETMC_TRACE_DATA0 (for M46xxI/M46xxJ) 1632 * | | |13 = TM0_EXT 1633 * | | |14 = USB_VBUS_EN 1634 * | | |15 = HSUSB_VBUS_EN (for M46xxI/M46xxJ) 1635 * | | |17 = PSIO0_CH0 1636 * | | |18 = KPI_COL0 1637 * | | |19 = SPI9_CLK 1638 * | | |20 = BMC27 1639 * @var SYS_T::GPC_MFP0 1640 * Offset: 0x520 GPIOC Multiple Function Control Register 0 1641 * --------------------------------------------------------------------------------------------------- 1642 * |Bits |Field |Descriptions 1643 * | :----: | :----: | :---- | 1644 * |[4:0] |PC0MFP |PC.0 Multi-function Pin Selection 1645 * | | |00 = GPIO 1646 * | | |02 = EBI_AD0 1647 * | | |03 = SPIM_MOSI 1648 * | | |04 = QSPI0_MOSI0 1649 * | | |05 = SC1_CLK 1650 * | | |06 = I2S0_LRCK 1651 * | | |07 = SPI1_SS 1652 * | | |08 = UART2_RXD 1653 * | | |09 = I2C0_SDA 1654 * | | |10 = CAN2_RXD 1655 * | | |12 = EPWM1_CH5 1656 * | | |13 = CCAP_DATA0 1657 * | | |14 = ACMP1_O 1658 * | | |15 = EADC1_ST 1659 * | | |16 = HBI_D2 1660 * | | |17 = QSPI1_CLK (for M46xxG) 1661 * | | |18 = KPI_ROW5 1662 * | | |19 = SPI7_MOSI 1663 * | | |20 = BMC25 1664 * |[12:8] |PC1MFP |PC.1 Multi-function Pin Selection 1665 * | | |00 = GPIO 1666 * | | |02 = EBI_AD1 1667 * | | |03 = SPIM_MISO 1668 * | | |04 = QSPI0_MISO0 1669 * | | |05 = SC1_DAT 1670 * | | |06 = I2S0_DO 1671 * | | |07 = SPI1_CLK 1672 * | | |08 = UART2_TXD 1673 * | | |09 = I2C0_SCL 1674 * | | |10 = CAN2_TXD 1675 * | | |12 = EPWM1_CH4 1676 * | | |13 = CCAP_DATA1 1677 * | | |14 = ACMP0_O 1678 * | | |15 = EADC0_ST 1679 * | | |16 = HBI_RWDS 1680 * | | |17 = QSPI1_SS (for M46xxG) 1681 * | | |18 = KPI_ROW4 1682 * | | |19 = SPI7_MISO 1683 * | | |20 = BMC24 1684 * |[20:16] |PC2MFP |PC.2 Multi-function Pin Selection 1685 * | | |00 = GPIO 1686 * | | |02 = EBI_AD2 1687 * | | |03 = SPIM_CLK 1688 * | | |04 = QSPI0_CLK 1689 * | | |05 = SC1_RST 1690 * | | |06 = I2S0_DI 1691 * | | |07 = SPI1_MOSI 1692 * | | |08 = UART2_nCTS 1693 * | | |09 = I2C0_SMBSUS 1694 * | | |10 = CAN1_RXD 1695 * | | |11 = UART3_RXD 1696 * | | |12 = EPWM1_CH3 1697 * | | |13 = CCAP_DATA2 1698 * | | |14 = QSPI1_MOSI0 1699 * | | |15 = I2C3_SDA 1700 * | | |16 = HBI_nRESET 1701 * | | |17 = PSIO0_CH3 1702 * | | |18 = KPI_ROW3 1703 * | | |19 = SPI7_CLK 1704 * | | |20 = BMC23 1705 * |[28:24] |PC3MFP |PC.3 Multi-function Pin Selection 1706 * | | |00 = GPIO 1707 * | | |02 = EBI_AD3 1708 * | | |03 = SPIM_SS 1709 * | | |04 = QSPI0_SS 1710 * | | |05 = SC1_PWR 1711 * | | |06 = I2S0_MCLK 1712 * | | |07 = SPI1_MISO 1713 * | | |08 = UART2_nRTS 1714 * | | |09 = I2C0_SMBAL 1715 * | | |10 = CAN1_TXD 1716 * | | |11 = UART3_TXD 1717 * | | |12 = EPWM1_CH2 1718 * | | |13 = CCAP_DATA3 1719 * | | |14 = QSPI1_MISO0 1720 * | | |15 = I2C3_SCL 1721 * | | |16 = HBI_nCS 1722 * | | |17 = PSIO0_CH2 1723 * | | |18 = KPI_ROW2 1724 * | | |19 = SPI7_SS 1725 * | | |20 = BMC22 1726 * @var SYS_T::GPC_MFP1 1727 * Offset: 0x524 GPIOC Multiple Function Control Register 1 1728 * --------------------------------------------------------------------------------------------------- 1729 * |Bits |Field |Descriptions 1730 * | :----: | :----: | :---- | 1731 * |[4:0] |PC4MFP |PC.4 Multi-function Pin Selection 1732 * | | |00 = GPIO 1733 * | | |02 = EBI_AD4 1734 * | | |03 = SPIM_D3 1735 * | | |04 = QSPI0_MOSI1 1736 * | | |05 = SC1_nCD 1737 * | | |06 = I2S0_BCLK 1738 * | | |07 = SPI1_I2SMCLK 1739 * | | |08 = UART2_RXD 1740 * | | |09 = I2C1_SDA 1741 * | | |10 = CAN0_RXD 1742 * | | |11 = UART4_RXD 1743 * | | |12 = EPWM1_CH1 1744 * | | |13 = CCAP_DATA4 1745 * | | |14 = QSPI1_CLK 1746 * | | |15 = I2C3_SMBSUS 1747 * | | |16 = HBI_CK 1748 * | | |17 = PSIO0_CH1 1749 * | | |18 = KPI_ROW1 1750 * | | |20 = BMC21 1751 * |[12:8] |PC5MFP |PC.5 Multi-function Pin Selection 1752 * | | |00 = GPIO 1753 * | | |02 = EBI_AD5 1754 * | | |03 = SPIM_D2 1755 * | | |04 = QSPI0_MISO1 1756 * | | |08 = UART2_TXD 1757 * | | |09 = I2C1_SCL 1758 * | | |10 = CAN0_TXD 1759 * | | |11 = UART4_TXD 1760 * | | |12 = EPWM1_CH0 1761 * | | |13 = CCAP_DATA5 1762 * | | |14 = QSPI1_SS 1763 * | | |15 = I2C3_SMBAL 1764 * | | |16 = HBI_nCK 1765 * | | |17 = PSIO0_CH0 1766 * | | |18 = KPI_ROW0 1767 * | | |20 = BMC20 1768 * |[20:16] |PC6MFP |PC.6 Multi-function Pin Selection 1769 * | | |00 = GPIO 1770 * | | |02 = EBI_AD8 1771 * | | |03 = EMAC0_RMII_RXD1 1772 * | | |04 = SPI1_MOSI 1773 * | | |05 = UART4_RXD 1774 * | | |06 = SC2_RST 1775 * | | |07 = UART0_nRTS 1776 * | | |08 = I2C1_SMBSUS 1777 * | | |09 = UART6_RXD 1778 * | | |10 = ACMP3_WLAT 1779 * | | |11 = EPWM1_CH3 1780 * | | |12 = BPWM1_CH1 1781 * | | |13 = CAN3_RXD 1782 * | | |14 = TM1 1783 * | | |15 = INT2 1784 * | | |18 = KPI_COL2 1785 * | | |19 = SPI6_MOSI 1786 * | | |20 = BMC25 1787 * |[28:24] |PC7MFP |PC.7 Multi-function Pin Selection 1788 * | | |00 = GPIO 1789 * | | |02 = EBI_AD9 1790 * | | |03 = EMAC0_RMII_RXD0 1791 * | | |04 = SPI1_MISO 1792 * | | |05 = UART4_TXD 1793 * | | |06 = SC2_PWR 1794 * | | |07 = UART0_nCTS 1795 * | | |08 = I2C1_SMBAL 1796 * | | |09 = UART6_TXD 1797 * | | |10 = ACMP2_WLAT 1798 * | | |11 = EPWM1_CH2 1799 * | | |12 = BPWM1_CH0 1800 * | | |13 = CAN3_TXD 1801 * | | |14 = TM0 1802 * | | |15 = INT3 1803 * | | |18 = KPI_COL3 1804 * | | |19 = SPI6_MISO 1805 * | | |20 = BMC24 1806 * @var SYS_T::GPC_MFP2 1807 * Offset: 0x528 GPIOC Multiple Function Control Register 2 1808 * --------------------------------------------------------------------------------------------------- 1809 * |Bits |Field |Descriptions 1810 * | :----: | :----: | :---- | 1811 * |[4:0] |PC8MFP |PC.8 Multi-function Pin Selection 1812 * | | |00 = GPIO 1813 * | | |02 = EBI_ADR16 1814 * | | |03 = EMAC0_RMII_REFCLK 1815 * | | |04 = I2C0_SDA 1816 * | | |05 = UART4_nCTS 1817 * | | |08 = UART1_RXD 1818 * | | |11 = EPWM1_CH1 1819 * | | |12 = BPWM1_CH4 1820 * | | |18 = KPI_COL4 1821 * |[12:8] |PC9MFP |PC.9 Multi-function Pin Selection 1822 * | | |00 = GPIO 1823 * | | |01 = EADC2_CH10, ACMP3_P1 1824 * | | |02 = EBI_ADR7 1825 * | | |05 = UART6_nCTS 1826 * | | |06 = SPI3_SS 1827 * | | |07 = UART3_RXD 1828 * | | |09 = CAN1_RXD 1829 * | | |10 = I2C4_SMBSUS 1830 * | | |12 = EPWM1_CH3 1831 * | | |14 = EADC1_ST 1832 * |[20:16] |PC10MFP |PC.10 Multi-function Pin Selection 1833 * | | |00 = GPIO 1834 * | | |01 = EADC2_CH11, ACMP3_P2 1835 * | | |02 = EBI_ADR6 1836 * | | |05 = UART6_nRTS 1837 * | | |06 = SPI3_CLK 1838 * | | |07 = UART3_TXD 1839 * | | |09 = CAN1_TXD 1840 * | | |10 = I2C4_SMBAL 1841 * | | |11 = ECAP1_IC0 1842 * | | |12 = EPWM1_CH2 1843 * | | |14 = EADC1_ST 1844 * |[28:24] |PC11MFP |PC.11 Multi-function Pin Selection 1845 * | | |00 = GPIO 1846 * | | |01 = EADC2_CH12, ACMP3_P3 1847 * | | |02 = EBI_ADR5 1848 * | | |03 = UART0_RXD 1849 * | | |04 = I2C0_SDA 1850 * | | |05 = UART6_RXD 1851 * | | |06 = SPI3_MOSI 1852 * | | |10 = I2C4_SDA 1853 * | | |11 = ECAP1_IC1 1854 * | | |12 = EPWM1_CH1 1855 * | | |14 = ACMP1_O 1856 * @var SYS_T::GPC_MFP3 1857 * Offset: 0x52C GPIOC Multiple Function Control Register 3 1858 * --------------------------------------------------------------------------------------------------- 1859 * |Bits |Field |Descriptions 1860 * | :----: | :----: | :---- | 1861 * |[4:0] |PC12MFP |PC.12 Multi-function Pin Selection 1862 * | | |00 = GPIO 1863 * | | |01 = EADC2_CH13 1864 * | | |02 = EBI_ADR4 1865 * | | |03 = UART0_TXD 1866 * | | |04 = I2C0_SCL 1867 * | | |05 = UART6_TXD 1868 * | | |06 = SPI3_MISO 1869 * | | |09 = SC0_nCD 1870 * | | |10 = I2C4_SCL 1871 * | | |11 = ECAP1_IC2 1872 * | | |12 = EPWM1_CH0 1873 * | | |14 = ACMP0_O 1874 * |[12:8] |PC13MFP |PC.13 Multi-function Pin Selection 1875 * | | |00 = GPIO 1876 * | | |01 = EADC1_CH3, EADC2_CH3 1877 * | | |02 = EBI_ADR10 1878 * | | |03 = SC2_nCD 1879 * | | |04 = SPI2_I2SMCLK 1880 * | | |05 = CAN1_TXD 1881 * | | |06 = USCI0_CTL0 1882 * | | |07 = UART2_TXD 1883 * | | |08 = UART8_nCTS 1884 * | | |09 = BPWM0_CH4 1885 * | | |13 = CLKO 1886 * | | |14 = EADC0_ST 1887 * | | |19 = SPI9_SS 1888 * |[20:16] |PC14MFP |PC.14 Multi-function Pin Selection 1889 * | | |00 = GPIO 1890 * | | |02 = EBI_AD11 1891 * | | |03 = SC1_nCD 1892 * | | |04 = SPI0_I2SMCLK 1893 * | | |05 = USCI0_CTL0 1894 * | | |06 = QSPI0_CLK 1895 * | | |10 = TRACE_SWO 1896 * | | |11 = EPWM0_SYNC_IN 1897 * | | |12 = ETMC_TRACE_CLK (for M46xxI/M46xxJ) 1898 * | | |13 = TM1 1899 * | | |14 = USB_VBUS_ST 1900 * | | |15 = HSUSB_VBUS_ST (for M46xxI/M46xxJ) 1901 * | | |19 = SPI9_MOSI 1902 * | | |20 = BMC26 1903 * |[28:24] |PC15MFP |PC.15 Multi-function Pin Selection 1904 * @var SYS_T::GPD_MFP0 1905 * Offset: 0x530 GPIOD Multiple Function Control Register 0 1906 * --------------------------------------------------------------------------------------------------- 1907 * |Bits |Field |Descriptions 1908 * | :----: | :----: | :---- | 1909 * |[4:0] |PD0MFP |PD.0 Multi-function Pin Selection 1910 * | | |00 = GPIO 1911 * | | |02 = EBI_AD13 1912 * | | |03 = USCI0_CLK 1913 * | | |04 = SPI0_MOSI 1914 * | | |05 = UART3_RXD 1915 * | | |06 = I2C2_SDA 1916 * | | |07 = SC2_CLK 1917 * | | |10 = I2S1_DO 1918 * | | |12 = EQEI2_A 1919 * | | |13 = ECAP2_IC1 1920 * | | |14 = TM2 1921 * |[12:8] |PD1MFP |PD.1 Multi-function Pin Selection 1922 * | | |00 = GPIO 1923 * | | |02 = EBI_AD12 1924 * | | |03 = USCI0_DAT0 1925 * | | |04 = SPI0_MISO 1926 * | | |05 = UART3_TXD 1927 * | | |06 = I2C2_SCL 1928 * | | |07 = SC2_DAT 1929 * | | |10 = I2S1_DI 1930 * | | |12 = EQEI2_INDEX 1931 * | | |13 = ECAP2_IC0 1932 * |[20:16] |PD2MFP |PD.2 Multi-function Pin Selection 1933 * | | |00 = GPIO 1934 * | | |02 = EBI_AD11 1935 * | | |03 = USCI0_DAT1 1936 * | | |04 = SPI0_CLK 1937 * | | |05 = UART3_nCTS 1938 * | | |07 = SC2_RST 1939 * | | |09 = UART0_RXD 1940 * | | |10 = I2S1_MCLK 1941 * | | |13 = EQEI3_B 1942 * |[28:24] |PD3MFP |PD.3 Multi-function Pin Selection 1943 * | | |00 = GPIO 1944 * | | |02 = EBI_AD10 1945 * | | |03 = USCI0_CTL1 1946 * | | |04 = SPI0_SS 1947 * | | |05 = UART3_nRTS 1948 * | | |07 = SC2_PWR 1949 * | | |08 = SC1_nCD 1950 * | | |09 = UART0_TXD 1951 * | | |10 = I2S1_BCLK 1952 * | | |13 = EQEI3_A 1953 * @var SYS_T::GPD_MFP1 1954 * Offset: 0x534 GPIOD Multiple Function Control Register 1 1955 * --------------------------------------------------------------------------------------------------- 1956 * |Bits |Field |Descriptions 1957 * | :----: | :----: | :---- | 1958 * |[4:0] |PD4MFP |PD.4 Multi-function Pin Selection 1959 * | | |00 = GPIO 1960 * | | |03 = USCI0_CTL0 1961 * | | |04 = I2C1_SDA 1962 * | | |05 = SPI1_SS 1963 * | | |08 = SC1_CLK 1964 * | | |14 = USB_VBUS_ST 1965 * | | |17 = PSIO0_CH7 1966 * |[12:8] |PD5MFP |PD.5 Multi-function Pin Selection 1967 * | | |00 = GPIO 1968 * | | |04 = I2C1_SCL 1969 * | | |05 = SPI1_CLK 1970 * | | |08 = SC1_DAT 1971 * | | |14 = ACMP1_O 1972 * | | |15 = EADC1_ST 1973 * | | |16 = HBI_D7 1974 * | | |17 = PSIO0_CH6 1975 * |[20:16] |PD6MFP |PD.6 Multi-function Pin Selection 1976 * | | |00 = GPIO 1977 * | | |02 = EBI_AD5 1978 * | | |03 = UART1_RXD 1979 * | | |04 = I2C0_SDA 1980 * | | |05 = SPI1_MOSI 1981 * | | |06 = QSPI1_MOSI0 1982 * | | |08 = SC1_RST 1983 * | | |14 = ACMP0_O 1984 * | | |15 = EADC0_ST 1985 * | | |16 = HBI_D6 1986 * | | |17 = PSIO0_CH5 1987 * |[28:24] |PD7MFP |PD.7 Multi-function Pin Selection 1988 * | | |00 = GPIO 1989 * | | |02 = EBI_AD4 1990 * | | |03 = UART1_TXD 1991 * | | |04 = I2C0_SCL 1992 * | | |05 = SPI1_MISO 1993 * | | |06 = QSPI1_MISO0 1994 * | | |07 = CCAP_HSYNC 1995 * | | |08 = SC1_PWR 1996 * | | |16 = HBI_D5 1997 * | | |17 = PSIO0_CH4 1998 * @var SYS_T::GPD_MFP2 1999 * Offset: 0x538 GPIOD Multiple Function Control Register 2 2000 * --------------------------------------------------------------------------------------------------- 2001 * |Bits |Field |Descriptions 2002 * | :----: | :----: | :---- | 2003 * |[4:0] |PD8MFP |PD.8 Multi-function Pin Selection 2004 * | | |00 = GPIO 2005 * | | |02 = EBI_AD6 2006 * | | |03 = I2C2_SDA 2007 * | | |04 = UART2_nRTS 2008 * | | |05 = UART7_RXD 2009 * | | |06 = CAN2_RXD 2010 * | | |17 = PSIO0_CH3 2011 * |[12:8] |PD9MFP |PD.9 Multi-function Pin Selection 2012 * | | |00 = GPIO 2013 * | | |02 = EBI_AD7 2014 * | | |03 = I2C2_SCL 2015 * | | |04 = UART2_nCTS 2016 * | | |05 = UART7_TXD 2017 * | | |06 = CAN2_TXD 2018 * | | |17 = PSIO0_CH2 2019 * |[20:16] |PD10MFP |PD.10 Multi-function Pin Selection 2020 * | | |00 = GPIO 2021 * | | |01 = EADC1_CH0, EADC2_CH0 2022 * | | |02 = EBI_nCS2 2023 * | | |03 = UART1_RXD 2024 * | | |04 = CAN0_RXD 2025 * | | |08 = UART8_RXD 2026 * | | |10 = EQEI0_B 2027 * | | |11 = ECAP3_IC2 2028 * | | |15 = INT7 2029 * | | |19 = SPI9_MOSI 2030 * |[28:24] |PD11MFP |PD.11 Multi-function Pin Selection 2031 * | | |00 = GPIO 2032 * | | |01 = EADC1_CH1, EADC2_CH1 2033 * | | |02 = EBI_nCS1 2034 * | | |03 = UART1_TXD 2035 * | | |04 = CAN0_TXD 2036 * | | |08 = UART8_TXD 2037 * | | |10 = EQEI0_A 2038 * | | |11 = ECAP3_IC1 2039 * | | |15 = INT6 2040 * | | |19 = SPI9_MISO 2041 * @var SYS_T::GPD_MFP3 2042 * Offset: 0x53C GPIOD Multiple Function Control Register 3 2043 * --------------------------------------------------------------------------------------------------- 2044 * |Bits |Field |Descriptions 2045 * | :----: | :----: | :---- | 2046 * |[4:0] |PD12MFP |PD.12 Multi-function Pin Selection 2047 * | | |00 = GPIO 2048 * | | |01 = EADC1_CH2, EADC2_CH2 2049 * | | |02 = EBI_nCS0 2050 * | | |05 = CAN1_RXD 2051 * | | |07 = UART2_RXD 2052 * | | |08 = UART8_nRTS 2053 * | | |09 = BPWM0_CH5 2054 * | | |10 = EQEI0_INDEX 2055 * | | |11 = ECAP3_IC0 2056 * | | |13 = CLKO 2057 * | | |14 = EADC0_ST 2058 * | | |15 = INT5 2059 * | | |19 = SPI9_CLK 2060 * |[12:8] |PD13MFP |PD.13 Multi-function Pin Selection 2061 * | | |00 = GPIO 2062 * | | |02 = EBI_AD10 2063 * | | |03 = SD0_nCD 2064 * | | |04 = SPI0_I2SMCLK 2065 * | | |05 = SPI1_I2SMCLK 2066 * | | |06 = QSPI1_MOSI0 2067 * | | |07 = SC2_nCD 2068 * | | |08 = SD1_CLK 2069 * | | |09 = UART6_RXD 2070 * | | |10 = I2S1_LRCK 2071 * | | |11 = BPWM0_CH0 2072 * | | |12 = EQEI2_B 2073 * | | |13 = ECAP2_IC2 2074 * | | |14 = CLKO 2075 * | | |15 = EADC0_ST 2076 * | | |19 = QSPI1_MOSI1 (for M46xxG) 2077 * |[20:16] |PD14MFP |PD.14 Multi-function Pin Selection 2078 * | | |00 = GPIO 2079 * | | |02 = EBI_nCS0 2080 * | | |03 = SPI3_I2SMCLK 2081 * | | |04 = SC1_nCD 2082 * | | |05 = SPI0_I2SMCLK 2083 * | | |10 = I2S1_BCLK 2084 * | | |11 = EPWM0_CH4 2085 * |[28:24] |PD15MFP |PD.15 Multi-function Pin Selection 2086 * @var SYS_T::GPE_MFP0 2087 * Offset: 0x540 GPIOE Multiple Function Control Register 0 2088 * --------------------------------------------------------------------------------------------------- 2089 * |Bits |Field |Descriptions 2090 * | :----: | :----: | :---- | 2091 * |[4:0] |PE0MFP |PE.0 Multi-function Pin Selection 2092 * | | |00 = GPIO 2093 * | | |02 = EBI_AD11 2094 * | | |03 = QSPI0_MOSI0 2095 * | | |04 = SC2_CLK 2096 * | | |05 = I2S0_MCLK 2097 * | | |06 = SPI1_MOSI 2098 * | | |07 = UART3_RXD 2099 * | | |08 = I2C1_SDA 2100 * | | |09 = UART4_nRTS 2101 * | | |10 = UART8_RXD 2102 * |[12:8] |PE1MFP |PE.1 Multi-function Pin Selection 2103 * | | |00 = GPIO 2104 * | | |02 = EBI_AD10 2105 * | | |03 = QSPI0_MISO0 2106 * | | |04 = SC2_DAT 2107 * | | |05 = I2S0_BCLK 2108 * | | |06 = SPI1_MISO 2109 * | | |07 = UART3_TXD 2110 * | | |08 = I2C1_SCL 2111 * | | |09 = UART4_nCTS 2112 * | | |10 = UART8_TXD 2113 * |[20:16] |PE2MFP |PE.2 Multi-function Pin Selection 2114 * | | |00 = GPIO 2115 * | | |02 = EBI_ALE 2116 * | | |03 = SD0_DAT0 2117 * | | |04 = SPIM_MOSI 2118 * | | |05 = SPI3_MOSI 2119 * | | |06 = SC0_CLK 2120 * | | |07 = USCI0_CLK 2121 * | | |08 = UART6_nCTS 2122 * | | |09 = UART7_RXD 2123 * | | |10 = UART8_nRTS 2124 * | | |11 = EQEI0_B 2125 * | | |12 = EPWM0_CH5 2126 * | | |13 = BPWM0_CH0 2127 * |[28:24] |PE3MFP |PE.3 Multi-function Pin Selection 2128 * | | |00 = GPIO 2129 * | | |02 = EBI_MCLK 2130 * | | |03 = SD0_DAT1 2131 * | | |04 = SPIM_MISO 2132 * | | |05 = SPI3_MISO 2133 * | | |06 = SC0_DAT 2134 * | | |07 = USCI0_DAT0 2135 * | | |08 = UART6_nRTS 2136 * | | |09 = UART7_TXD 2137 * | | |10 = UART8_nCTS 2138 * | | |11 = EQEI0_A 2139 * | | |12 = EPWM0_CH4 2140 * | | |13 = BPWM0_CH1 2141 * @var SYS_T::GPE_MFP1 2142 * Offset: 0x544 GPIOE Multiple Function Control Register 1 2143 * --------------------------------------------------------------------------------------------------- 2144 * |Bits |Field |Descriptions 2145 * | :----: | :----: | :---- | 2146 * |[4:0] |PE4MFP |PE.4 Multi-function Pin Selection 2147 * | | |00 = GPIO 2148 * | | |02 = EBI_nWR 2149 * | | |03 = SD0_DAT2 2150 * | | |04 = SPIM_CLK 2151 * | | |05 = SPI3_CLK 2152 * | | |06 = SC0_RST 2153 * | | |07 = USCI0_DAT1 2154 * | | |08 = UART6_RXD 2155 * | | |09 = UART7_nCTS 2156 * | | |10 = UART9_RXD 2157 * | | |11 = EQEI0_INDEX 2158 * | | |12 = EPWM0_CH3 2159 * | | |13 = BPWM0_CH2 2160 * | | |17 = PSIO0_CH3 2161 * |[12:8] |PE5MFP |PE.5 Multi-function Pin Selection 2162 * | | |00 = GPIO 2163 * | | |02 = EBI_nRD 2164 * | | |03 = SD0_DAT3 2165 * | | |04 = SPIM_SS 2166 * | | |05 = SPI3_SS 2167 * | | |06 = SC0_PWR 2168 * | | |07 = USCI0_CTL1 2169 * | | |08 = UART6_TXD 2170 * | | |09 = UART7_nRTS 2171 * | | |10 = UART9_TXD 2172 * | | |11 = EQEI1_B 2173 * | | |12 = EPWM0_CH2 2174 * | | |13 = BPWM0_CH3 2175 * | | |17 = PSIO0_CH2 2176 * |[20:16] |PE6MFP |PE.6 Multi-function Pin Selection 2177 * | | |00 = GPIO 2178 * | | |03 = SD0_CLK 2179 * | | |04 = SPIM_D3 2180 * | | |05 = SPI3_I2SMCLK 2181 * | | |06 = SC0_nCD 2182 * | | |07 = USCI0_CTL0 2183 * | | |08 = UART5_RXD 2184 * | | |09 = CAN1_RXD 2185 * | | |10 = UART9_nRTS 2186 * | | |11 = EQEI1_A 2187 * | | |12 = EPWM0_CH1 2188 * | | |13 = BPWM0_CH4 2189 * | | |14 = ACMP3_O 2190 * | | |17 = PSIO0_CH1 2191 * |[28:24] |PE7MFP |PE.7 Multi-function Pin Selection 2192 * | | |00 = GPIO 2193 * | | |03 = SD0_CMD 2194 * | | |04 = SPIM_D2 2195 * | | |08 = UART5_TXD 2196 * | | |09 = CAN1_TXD 2197 * | | |10 = UART9_nCTS 2198 * | | |11 = EQEI1_INDEX 2199 * | | |12 = EPWM0_CH0 2200 * | | |13 = BPWM0_CH5 2201 * | | |14 = ACMP2_O 2202 * | | |17 = PSIO0_CH0 2203 * @var SYS_T::GPE_MFP2 2204 * Offset: 0x548 GPIOE Multiple Function Control Register 2 2205 * --------------------------------------------------------------------------------------------------- 2206 * |Bits |Field |Descriptions 2207 * | :----: | :----: | :---- | 2208 * |[4:0] |PE8MFP |PE.8 Multi-function Pin Selection 2209 * | | |00 = GPIO 2210 * | | |02 = EBI_ADR10 2211 * | | |03 = EMAC0_RMII_MDC 2212 * | | |04 = I2S0_BCLK 2213 * | | |05 = SPI2_CLK 2214 * | | |07 = UART2_TXD 2215 * | | |10 = EPWM0_CH0 2216 * | | |11 = EPWM0_BRAKE0 2217 * | | |12 = ECAP0_IC0 2218 * | | |13 = EQEI2_INDEX 2219 * | | |14 = TRACE_DATA3 2220 * | | |15 = ECAP3_IC0 2221 * |[12:8] |PE9MFP |PE.9 Multi-function Pin Selection 2222 * | | |00 = GPIO 2223 * | | |02 = EBI_ADR11 2224 * | | |03 = EMAC0_RMII_MDIO 2225 * | | |04 = I2S0_MCLK 2226 * | | |05 = SPI2_MISO 2227 * | | |07 = UART2_RXD 2228 * | | |10 = EPWM0_CH1 2229 * | | |11 = EPWM0_BRAKE1 2230 * | | |12 = ECAP0_IC1 2231 * | | |13 = EQEI2_A 2232 * | | |14 = TRACE_DATA2 2233 * | | |15 = ECAP3_IC1 2234 * |[20:16] |PE10MFP |PE.10 Multi-function Pin Selection 2235 * | | |00 = GPIO 2236 * | | |02 = EBI_ADR12 2237 * | | |03 = EMAC_RMII_TXD0 2238 * | | |04 = I2S0_DI 2239 * | | |05 = SPI2_MOSI 2240 * | | |07 = UART3_TXD 2241 * | | |10 = EPWM0_CH2 2242 * | | |11 = EPWM1_BRAKE0 2243 * | | |12 = ECAP0_IC2 2244 * | | |13 = EQEI2_B 2245 * | | |14 = TRACE_DATA1 2246 * | | |15 = ECAP3_IC2 2247 * |[28:24] |PE11MFP |PE.11 Multi-function Pin Selection 2248 * | | |00 = GPIO 2249 * | | |02 = EBI_ADR13 2250 * | | |03 = EMAC0_RMII_TXD1 2251 * | | |04 = I2S0_DO 2252 * | | |05 = SPI2_SS 2253 * | | |07 = UART3_RXD 2254 * | | |08 = UART1_nCTS 2255 * | | |10 = EPWM0_CH3 2256 * | | |11 = EPWM1_BRAKE1 2257 * | | |13 = ECAP1_IC2 2258 * | | |14 = TRACE_DATA0 2259 * | | |18 = KPI_COL7 2260 * @var SYS_T::GPE_MFP3 2261 * Offset: 0x54C GPIOE Multiple Function Control Register 3 2262 * --------------------------------------------------------------------------------------------------- 2263 * |Bits |Field |Descriptions 2264 * | :----: | :----: | :---- | 2265 * |[4:0] |PE12MFP |PE.12 Multi-function Pin Selection 2266 * | | |00 = GPIO 2267 * | | |02 = EBI_ADR14 2268 * | | |03 = EMAC0_RMII_TXEN 2269 * | | |04 = I2S0_LRCK 2270 * | | |05 = SPI2_I2SMCLK 2271 * | | |08 = UART1_nRTS 2272 * | | |10 = EPWM0_CH4 2273 * | | |13 = ECAP1_IC1 2274 * | | |14 = TRACE_CLK 2275 * | | |18 = KPI_COL6 2276 * |[12:8] |PE13MFP |PE.13 Multi-function Pin Selection 2277 * | | |00 = GPIO 2278 * | | |02 = EBI_ADR15 2279 * | | |03 = EMAC0_PPS 2280 * | | |04 = I2C0_SCL 2281 * | | |05 = UART4_nRTS 2282 * | | |08 = UART1_TXD 2283 * | | |10 = EPWM0_CH5 2284 * | | |11 = EPWM1_CH0 2285 * | | |12 = BPWM1_CH5 2286 * | | |13 = ECAP1_IC0 2287 * | | |14 = TRACE_SWO 2288 * | | |18 = KPI_COL5 2289 * |[20:16] |PE14MFP |PE.14 Multi-function Pin Selection 2290 * | | |00 = GPIO 2291 * | | |02 = EBI_AD8 2292 * | | |03 = UART2_TXD 2293 * | | |04 = CAN0_TXD 2294 * | | |05 = SD1_nCD 2295 * | | |06 = UART6_TXD 2296 * | | |17 = PSIO0_CH0 2297 * |[28:24] |PE15MFP |PE.15 Multi-function Pin Selection 2298 * | | |00 = GPIO 2299 * | | |02 = EBI_AD9 2300 * | | |03 = UART2_RXD 2301 * | | |04 = CAN0_RXD 2302 * | | |06 = UART6_RXD 2303 * | | |17 = PSIO0_CH1 2304 * @var SYS_T::GPF_MFP0 2305 * Offset: 0x550 GPIOF Multiple Function Control Register 0 2306 * --------------------------------------------------------------------------------------------------- 2307 * |Bits |Field |Descriptions 2308 * | :----: | :----: | :---- | 2309 * |[4:0] |PF0MFP |PF.0 Multi-function Pin Selection 2310 * | | |00 = GPIO 2311 * | | |02 = UART1_TXD 2312 * | | |03 = I2C1_SCL 2313 * | | |04 = UART0_TXD 2314 * | | |05 = SC1_DAT 2315 * | | |06 = I2S0_DO 2316 * | | |08 = UART2_TXD 2317 * | | |09 = I2C0_SCL 2318 * | | |10 = CAN2_TXD 2319 * | | |11 = EPWM1_CH4 2320 * | | |12 = BPWM1_CH0 2321 * | | |13 = ACMP0_O 2322 * | | |14 = ICE_DAT 2323 * | | |15 = EADC0_ST 2324 * | | |19 = QSPI1_MISO0 (for M46xxG) 2325 * |[12:8] |PF1MFP |PF.1 Multi-function Pin Selection 2326 * | | |00 = GPIO 2327 * | | |02 = UART1_RXD 2328 * | | |03 = I2C1_SDA 2329 * | | |04 = UART0_RXD 2330 * | | |05 = SC1_CLK 2331 * | | |06 = I2S0_LRCK 2332 * | | |08 = UART2_RXD 2333 * | | |09 = I2C0_SDA 2334 * | | |10 = CAN2_RXD 2335 * | | |11 = EPWM1_CH5 2336 * | | |12 = BPWM1_CH1 2337 * | | |13 = ACMP1_O 2338 * | | |14 = ICE_CLK 2339 * | | |15 = EADC1_ST 2340 * | | |19 = QSPI1_MOSI0 (for M46xxG) 2341 * |[20:16] |PF2MFP |PF.2 Multi-function Pin Selection 2342 * | | |00 = GPIO 2343 * | | |02 = EBI_nCS1 2344 * | | |03 = UART0_RXD 2345 * | | |04 = I2C0_SDA 2346 * | | |05 = QSPI0_CLK 2347 * | | |07 = UART9_RXD 2348 * | | |10 = XT1_OUT 2349 * | | |11 = BPWM1_CH1 2350 * | | |12 = I2C4_SMBSUS 2351 * | | |13 = ACMP3_O 2352 * | | |20 = BMC13 2353 * |[28:24] |PF3MFP |PF.3 Multi-function Pin Selection 2354 * | | |00 = GPIO 2355 * | | |02 = EBI_nCS0 2356 * | | |03 = UART0_TXD 2357 * | | |04 = I2C0_SCL 2358 * | | |07 = UART9_TXD 2359 * | | |10 = XT1_IN 2360 * | | |11 = BPWM1_CH0 2361 * | | |12 = I2C4_SMBAL 2362 * | | |13 = ACMP2_O 2363 * | | |15 = EADC2_ST 2364 * | | |20 = BMC12 2365 * @var SYS_T::GPF_MFP1 2366 * Offset: 0x554 GPIOF Multiple Function Control Register 1 2367 * --------------------------------------------------------------------------------------------------- 2368 * |Bits |Field |Descriptions 2369 * | :----: | :----: | :---- | 2370 * |[4:0] |PF4MFP |PF.4 Multi-function Pin Selection 2371 * | | |00 = GPIO 2372 * | | |02 = UART2_TXD 2373 * | | |03 = EBI_AD0 2374 * | | |04 = UART2_nRTS 2375 * | | |07 = EPWM0_CH1 2376 * | | |08 = BPWM0_CH5 2377 * | | |10 = X32_OUT 2378 * | | |11 = EADC1_ST 2379 * | | |12 = I2C4_SDA 2380 * | | |13 = EQEI2_B 2381 * | | |19 = SPI5_MISO 2382 * | | |20 = BMC11 2383 * |[12:8] |PF5MFP |PF.5 Multi-function Pin Selection 2384 * | | |00 = GPIO 2385 * | | |02 = UART2_RXD 2386 * | | |03 = EBI_AD1 2387 * | | |04 = UART2_nCTS 2388 * | | |07 = EPWM0_CH0 2389 * | | |08 = BPWM0_CH4 2390 * | | |09 = EPWM0_SYNC_OUT 2391 * | | |10 = X32_IN 2392 * | | |11 = EADC0_ST 2393 * | | |12 = I2C4_SCL 2394 * | | |13 = EQEI2_A 2395 * | | |19 = SPI5_MOSI 2396 * | | |20 = BMC10 2397 * |[20:16] |PF6MFP |PF.6 Multi-function Pin Selection 2398 * | | |00 = GPIO 2399 * | | |02 = EBI_ADR19 2400 * | | |03 = SC0_CLK 2401 * | | |04 = I2S0_LRCK 2402 * | | |05 = SPI0_MOSI 2403 * | | |06 = UART4_RXD 2404 * | | |07 = EBI_nCS0 2405 * | | |08 = CAN2_RXD 2406 * | | |09 = SPI3_I2SMCLK 2407 * | | |10 = TAMPER0 2408 * | | |13 = EQEI2_INDEX 2409 * | | |14 = TRACE_SWO 2410 * | | |19 = SPI5_CLK 2411 * |[28:24] |PF7MFP |PF.7 Multi-function Pin Selection 2412 * | | |00 = GPIO 2413 * | | |02 = EBI_ADR18 2414 * | | |03 = SC0_DAT 2415 * | | |04 = I2S0_DO 2416 * | | |05 = SPI0_MISO 2417 * | | |06 = UART4_TXD 2418 * | | |07 = CCAP_DATA0 2419 * | | |08 = CAN2_TXD 2420 * | | |10 = TAMPER1 2421 * | | |19 = SPI5_SS 2422 2423 * @var SYS_T::GPF_MFP2 2424 * Offset: 0x558 GPIOF Multiple Function Control Register 2 2425 * --------------------------------------------------------------------------------------------------- 2426 * |Bits |Field |Descriptions 2427 * | :----: | :----: | :---- | 2428 * |[4:0] |PF8MFP |PF.8 Multi-function Pin Selection 2429 * | | |00 = GPIO 2430 * | | |02 = EBI_ADR17 2431 * | | |03 = SC0_RST 2432 * | | |04 = I2S0_DI 2433 * | | |05 = SPI0_CLK 2434 * | | |06 = UART5_nCTS 2435 * | | |07 = CCAP_DATA1 2436 * | | |08 = CAN1_RXD 2437 * | | |10 = TAMPER2 2438 * | | |11 = UART9_RXD 2439 * |[12:8] |PF9MFP |PF.9 Multi-function Pin Selection 2440 * | | |00 = GPIO 2441 * | | |02 = EBI_ADR16 2442 * | | |03 = SC0_PWR 2443 * | | |04 = I2S0_MCLK 2444 * | | |05 = SPI0_SS 2445 * | | |06 = UART5_nRTS 2446 * | | |07 = CCAP_DATA2 2447 * | | |08 = CAN1_TXD 2448 * | | |10 = TAMPER3 2449 * | | |11 = UART9_TXD 2450 * |[20:16] |PF10MFP |PF.10 Multi-function Pin Selection 2451 * | | |00 = GPIO 2452 * | | |02 = EBI_ADR15 2453 * | | |03 = SC0_nCD 2454 * | | |04 = I2S0_BCLK 2455 * | | |05 = SPI0_I2SMCLK 2456 * | | |06 = UART5_RXD 2457 * | | |07 = CCAP_DATA3 2458 * | | |08 = CAN3_RXD 2459 * | | |10 = TAMPER4 2460 * | | |11 = UART9_nRTS 2461 * |[28:24] |PF11MFP |PF.11 Multi-function Pin Selection 2462 * | | |00 = GPIO 2463 * | | |02 = EBI_ADR14 2464 * | | |03 = SPI2_MOSI 2465 * | | |06 = UART5_TXD 2466 * | | |07 = CCAP_DATA4 2467 * | | |08 = CAN3_TXD 2468 * | | |10 = TAMPER5 2469 * | | |11 = UART9_nCTS 2470 * | | |13 = TM3 2471 * @var SYS_T::GPF_MFP3 2472 * Offset: 0x55C GPIOF Multiple Function Control Register 3 2473 * --------------------------------------------------------------------------------------------------- 2474 * |Bits |Field |Descriptions 2475 * | :----: | :----: | :---- | 2476 * |[4:0] |PF12MFP |PF.12 Multi-function Pin Selection 2477 * |[12:8] |PF13MFP |PF.13 Multi-function Pin Selection 2478 * |[20:16] |PF14MFP |PF.14 Multi-function Pin Selection 2479 * |[28:24] |PF15MFP |PF.15 Multi-function Pin Selection 2480 * @var SYS_T::GPG_MFP0 2481 * Offset: 0x560 GPIOG Multiple Function Control Register 0 2482 * --------------------------------------------------------------------------------------------------- 2483 * |Bits |Field |Descriptions 2484 * | :----: | :----: | :---- | 2485 * |[4:0] |PG0MFP |PG.0 Multi-function Pin Selection 2486 * | | |00 = GPIO 2487 * | | |02 = EBI_ADR8 2488 * | | |04 = I2C0_SCL 2489 * | | |05 = I2C1_SMBAL 2490 * | | |06 = UART2_RXD 2491 * | | |07 = CAN1_TXD 2492 * | | |08 = UART1_TXD 2493 * | | |09 = I2C3_SCL 2494 * |[12:8] |PG1MFP |PG.1 Multi-function Pin Selection 2495 * | | |00 = GPIO 2496 * | | |02 = EBI_ADR9 2497 * | | |03 = SPI2_I2SMCLK 2498 * | | |04 = I2C0_SDA 2499 * | | |05 = I2C1_SMBSUS 2500 * | | |06 = UART2_TXD 2501 * | | |07 = CAN1_RXD 2502 * | | |08 = UART1_RXD 2503 * | | |09 = I2C3_SDA 2504 * |[20:16] |PG2MFP |PG.2 Multi-function Pin Selection 2505 * | | |00 = GPIO 2506 * | | |02 = EBI_ADR11 2507 * | | |03 = SPI2_SS 2508 * | | |04 = I2C0_SMBAL 2509 * | | |05 = I2C1_SCL 2510 * | | |07 = CCAP_DATA7 2511 * | | |09 = I2C3_SMBAL 2512 * | | |13 = TM0 2513 * |[28:24] |PG3MFP |PG.3 Multi-function Pin Selection 2514 * | | |00 = GPIO 2515 * | | |02 = EBI_ADR12 2516 * | | |03 = SPI2_CLK 2517 * | | |04 = I2C0_SMBSUS 2518 * | | |05 = I2C1_SDA 2519 * | | |07 = CCAP_DATA6 2520 * | | |09 = I2C3_SMBSUS 2521 * | | |13 = TM1 2522 * @var SYS_T::GPG_MFP1 2523 * Offset: 0x564 GPIOG Multiple Function Control Register 1 2524 * --------------------------------------------------------------------------------------------------- 2525 * |Bits |Field |Descriptions 2526 * | :----: | :----: | :---- | 2527 * |[4:0] |PG4MFP |PG.4 Multi-function Pin Selection 2528 * | | |00 = GPIO 2529 * | | |02 = EBI_ADR13 2530 * | | |03 = SPI2_MISO 2531 * | | |07 = CCAP_DATA5 2532 * | | |13 = TM2 2533 * |[12:8] |PG5MFP |PG.5 Multi-function Pin Selection 2534 * | | |00 = GPIO 2535 * | | |02 = EBI_nCS1 2536 * | | |03 = SPI3_SS 2537 * | | |04 = SC1_PWR 2538 * | | |08 = I2C3_SMBAL 2539 * | | |10 = I2S1_MCLK 2540 * | | |11 = EPWM0_CH3 2541 * |[20:16] |PG6MFP |PG.6 Multi-function Pin Selection 2542 * | | |00 = GPIO 2543 * | | |02 = EBI_nCS2 2544 * | | |03 = SPI3_CLK 2545 * | | |04 = SC1_RST 2546 * | | |08 = I2C3_SMBSUS 2547 * | | |10 = I2S1_DI 2548 * | | |11 = EPWM0_CH2 2549 * |[28:24] |PG7MFP |PG.7 Multi-function Pin Selection 2550 * | | |00 = GPIO 2551 * | | |02 = EBI_nWRL 2552 * | | |03 = SPI3_MISO 2553 * | | |04 = SC1_DAT 2554 * | | |08 = I2C3_SCL 2555 * | | |10 = I2S1_DO 2556 * | | |11 = EPWM0_CH1 2557 * @var SYS_T::GPG_MFP2 2558 * Offset: 0x568 GPIOG Multiple Function Control Register 2 2559 * --------------------------------------------------------------------------------------------------- 2560 * |Bits |Field |Descriptions 2561 * | :----: | :----: | :---- | 2562 * |[4:0] |PG8MFP |PG.8 Multi-function Pin Selection 2563 * | | |00 = GPIO 2564 * | | |02 = EBI_nWRH 2565 * | | |03 = SPI3_MOSI 2566 * | | |04 = SC1_CLK 2567 * | | |08 = I2C3_SDA 2568 * | | |10 = I2S1_LRCK 2569 * | | |11 = EPWM0_CH0 2570 * |[12:8] |PG9MFP |PG.9 Multi-function Pin Selection 2571 * | | |00 = GPIO 2572 * | | |02 = EBI_AD0 2573 * | | |03 = SD1_DAT3 2574 * | | |04 = SPIM_D2 2575 * | | |05 = QSPI1_MISO1 2576 * | | |07 = CCAP_PIXCLK 2577 * | | |08 = I2C4_SCL 2578 * | | |09 = ECAP2_IC0 2579 * | | |12 = BPWM0_CH5 2580 * | | |16 = HBI_D4 2581 * | | |19 = SPI8_SS 2582 * | | |20 = BMC16 2583 * |[20:16] |PG10MFP |PG.10 Multi-function Pin Selection 2584 * | | |00 = GPIO 2585 * | | |02 = EBI_AD1 2586 * | | |03 = SD1_DAT2 2587 * | | |04 = SPIM_D3 2588 * | | |05 = QSPI1_MOSI1 2589 * | | |07 = CCAP_SCLK 2590 * | | |08 = I2C4_SDA 2591 * | | |09 = ECAP2_IC1 2592 * | | |12 = BPWM0_CH4 2593 * | | |16 = HBI_D3 2594 * | | |19 = SPI8_CLK 2595 * | | |20 = BMC17 2596 * |[28:24] |PG11MFP |PG.11 Multi-function Pin Selection 2597 * | | |00 = GPIO 2598 * | | |02 = EBI_AD2 2599 * | | |03 = SD1_DAT1 2600 * | | |04 = SPIM_SS 2601 * | | |05 = QSPI1_SS 2602 * | | |06 = UART7_TXD 2603 * | | |07 = CCAP_SFIELD 2604 * | | |08 = I2C4_SMBAL 2605 * | | |09 = ECAP2_IC2 2606 * | | |12 = BPWM0_CH3 2607 * | | |16 = HBI_D0 2608 * | | |19 = SPI8_MOSI 2609 * | | |20 = BMC18 2610 * @var SYS_T::GPG_MFP3 2611 * Offset: 0x56C GPIOG Multiple Function Control Register 3 2612 * --------------------------------------------------------------------------------------------------- 2613 * |Bits |Field |Descriptions 2614 * | :----: | :----: | :---- | 2615 * |[4:0] |PG12MFP |PG.12 Multi-function Pin Selection 2616 * | | |00 = GPIO 2617 * | | |02 = EBI_AD3 2618 * | | |03 = SD1_DAT0 2619 * | | |04 = SPIM_CLK 2620 * | | |05 = QSPI1_CLK 2621 * | | |06 = UART7_RXD 2622 * | | |07 = CCAP_VSYNC 2623 * | | |08 = I2C4_SMBSUS 2624 * | | |12 = BPWM0_CH2 2625 * | | |16 = HBI_D1 2626 * | | |19 = SPI8_MISO 2627 * | | |20 = BMC19 2628 * |[12:8] |PG13MFP |PG.13 Multi-function Pin Selection 2629 * | | |00 = GPIO 2630 * | | |02 = EBI_AD4 2631 * | | |03 = SD1_CMD 2632 * | | |04 = SPIM_MISO 2633 * | | |05 = QSPI1_MISO0 2634 * | | |06 = UART6_TXD 2635 * | | |07 = CCAP_HSYNC 2636 * | | |12 = BPWM0_CH1 2637 * | | |16 = HBI_D5 2638 * |[20:16] |PG14MFP |PG.14 Multi-function Pin Selection 2639 * | | |00 = GPIO 2640 * | | |02 = EBI_AD5 2641 * | | |03 = SD1_CLK 2642 * | | |04 = SPIM_MOSI 2643 * | | |05 = QSPI1_MOSI0 2644 * | | |06 = UART6_RXD 2645 * | | |12 = BPWM0_CH0 2646 * | | |16 = HBI_D6 2647 * |[28:24] |PG15MFP |PG.15 Multi-function Pin Selection 2648 * | | |00 = GPIO 2649 * | | |03 = SD1_nCD 2650 * | | |14 = CLKO 2651 * | | |15 = EADC0_ST 2652 * | | |16 = HBI_D7 2653 * | | |19 = QSPI1_MISO1 (for M46xxG) 2654 * @var SYS_T::GPH_MFP0 2655 * Offset: 0x570 GPIOH Multiple Function Control Register 0 2656 * --------------------------------------------------------------------------------------------------- 2657 * |Bits |Field |Descriptions 2658 * | :----: | :----: | :---- | 2659 * |[4:0] |PH0MFP |PH.0 Multi-function Pin Selection 2660 * | | |00 = GPIO 2661 * | | |02 = EBI_ADR7 2662 * | | |04 = UART5_TXD 2663 * | | |13 = TM0_EXT 2664 * |[12:8] |PH1MFP |PH.1 Multi-function Pin Selection 2665 * | | |00 = GPIO 2666 * | | |02 = EBI_ADR6 2667 * | | |04 = UART5_RXD 2668 * | | |13 = TM1_EXT 2669 * |[20:16] |PH2MFP |PH.2 Multi-function Pin Selection 2670 * | | |00 = GPIO 2671 * | | |02 = EBI_ADR5 2672 * | | |04 = UART5_nRTS 2673 * | | |05 = UART4_TXD 2674 * | | |06 = I2C0_SCL 2675 * | | |13 = TM2_EXT 2676 * |[28:24] |PH3MFP |PH.3 Multi-function Pin Selection 2677 * | | |00 = GPIO 2678 * | | |02 = EBI_ADR4 2679 * | | |03 = SPI1_I2SMCLK 2680 * | | |04 = UART5_nCTS 2681 * | | |05 = UART4_RXD 2682 * | | |06 = I2C0_SDA 2683 * | | |13 = TM3_EXT 2684 * @var SYS_T::GPH_MFP1 2685 * Offset: 0x574 GPIOH Multiple Function Control Register 1 2686 * --------------------------------------------------------------------------------------------------- 2687 * |Bits |Field |Descriptions 2688 * | :----: | :----: | :---- | 2689 * |[4:0] |PH4MFP |PH.4 Multi-function Pin Selection 2690 * | | |00 = GPIO 2691 * | | |02 = EBI_ADR3 2692 * | | |03 = SPI1_MISO 2693 * | | |04 = UART7_nRTS 2694 * | | |05 = UART6_TXD 2695 * |[12:8] |PH5MFP |PH.5 Multi-function Pin Selection 2696 * | | |00 = GPIO 2697 * | | |02 = EBI_ADR2 2698 * | | |03 = SPI1_MOSI 2699 * | | |04 = UART7_nCTS 2700 * | | |05 = UART6_RXD 2701 * |[20:16] |PH6MFP |PH.6 Multi-function Pin Selection 2702 * | | |00 = GPIO 2703 * | | |02 = EBI_ADR1 2704 * | | |03 = SPI1_CLK 2705 * | | |04 = UART7_TXD 2706 * | | |07 = UART9_nCTS 2707 * |[28:24] |PH7MFP |PH.7 Multi-function Pin Selection 2708 * | | |00 = GPIO 2709 * | | |02 = EBI_ADR0 2710 * | | |03 = SPI1_SS 2711 * | | |04 = UART7_RXD 2712 * | | |07 = UART9_nRTS 2713 * @var SYS_T::GPH_MFP2 2714 * Offset: 0x578 GPIOH Multiple Function Control Register 2 2715 * --------------------------------------------------------------------------------------------------- 2716 * |Bits |Field |Descriptions 2717 * | :----: | :----: | :---- | 2718 * |[4:0] |PH8MFP |PH.8 Multi-function Pin Selection 2719 * | | |00 = GPIO 2720 * | | |02 = EBI_AD12 2721 * | | |03 = QSPI0_CLK 2722 * | | |04 = SC2_PWR 2723 * | | |05 = I2S0_DI 2724 * | | |06 = SPI1_CLK 2725 * | | |07 = UART3_nRTS 2726 * | | |08 = I2C1_SMBAL 2727 * | | |09 = I2C2_SCL 2728 * | | |10 = UART1_TXD 2729 * | | |13 = UART9_nCTS 2730 * |[12:8] |PH9MFP |PH.9 Multi-function Pin Selection 2731 * | | |00 = GPIO 2732 * | | |02 = EBI_AD13 2733 * | | |03 = QSPI0_SS 2734 * | | |04 = SC2_RST 2735 * | | |05 = I2S0_DO 2736 * | | |06 = SPI1_SS 2737 * | | |07 = UART3_nCTS 2738 * | | |08 = I2C1_SMBSUS 2739 * | | |09 = I2C2_SDA 2740 * | | |10 = UART1_RXD 2741 * | | |13 = UART9_nRTS 2742 * |[20:16] |PH10MFP |PH.10 Multi-function Pin Selection 2743 * | | |00 = GPIO 2744 * | | |02 = EBI_AD14 2745 * | | |03 = QSPI0_MISO1 2746 * | | |04 = SC2_nCD 2747 * | | |05 = I2S0_LRCK 2748 * | | |06 = SPI1_I2SMCLK 2749 * | | |07 = UART4_TXD 2750 * | | |08 = UART0_TXD 2751 * | | |13 = UART9_TXD 2752 * |[28:24] |PH11MFP |PH.11 Multi-function Pin Selection 2753 * | | |00 = GPIO 2754 * | | |02 = EBI_AD15 2755 * | | |03 = QSPI0_MOSI1 2756 * | | |07 = UART4_RXD 2757 * | | |08 = UART0_RXD 2758 * | | |11 = EPWM0_CH5 2759 * | | |13 = UART9_RXD 2760 * @var SYS_T::GPH_MFP3 2761 * Offset: 0x57C GPIOH Multiple Function Control Register 3 2762 * --------------------------------------------------------------------------------------------------- 2763 * |Bits |Field |Descriptions 2764 * | :----: | :----: | :---- | 2765 * |[4:0] |PH12MFP |PH.12 Multi-function Pin Selection 2766 * | | |00 = GPIO 2767 * | | |02 = EBI_AD0 2768 * | | |03 = UART9_TXD 2769 * | | |06 = QSPI1_MISO1 2770 * | | |07 = CCAP_PIXCLK 2771 * | | |10 = CAN3_TXD 2772 * | | |16 = HBI_nCK 2773 * |[12:8] |PH13MFP |PH.13 Multi-function Pin Selection 2774 * | | |00 = GPIO 2775 * | | |02 = EBI_AD1 2776 * | | |03 = UART9_RXD 2777 * | | |06 = QSPI1_MOSI1 2778 * | | |07 = CCAP_SCLK 2779 * | | |10 = CAN3_RXD 2780 * | | |16 = HBI_CK 2781 * |[20:16] |PH14MFP |PH.14 Multi-function Pin Selection 2782 * | | |00 = GPIO 2783 * | | |02 = EBI_AD2 2784 * | | |06 = QSPI1_SS 2785 * | | |07 = CCAP_SFIELD 2786 * | | |16 = HBI_RWDS 2787 * |[28:24] |PH15MFP |PH.15 Multi-function Pin Selection 2788 * | | |00 = GPIO 2789 * | | |02 = EBI_AD3 2790 * | | |06 = QSPI1_CLK 2791 * | | |07 = CCAP_VSYNC 2792 * | | |16 = HBI_D4 2793 * @var SYS_T::GPI_MFP0 2794 * Offset: 0x580 GPIOI Multiple Function Control Register 0 2795 * --------------------------------------------------------------------------------------------------- 2796 * |Bits |Field |Descriptions 2797 * | :----: | :----: | :---- | 2798 * |[4:0] |PI0MFP |PI.0 Multi-function Pin Selection 2799 * |[12:8] |PI1MFP |PI.1 Multi-function Pin Selection 2800 * |[20:16] |PI2MFP |PI.2 Multi-function Pin Selection 2801 * |[28:24] |PI3MFP |PI.3 Multi-function Pin Selection 2802 * @var SYS_T::GPI_MFP1 2803 * Offset: 0x584 GPIOI Multiple Function Control Register 1 2804 * --------------------------------------------------------------------------------------------------- 2805 * |Bits |Field |Descriptions 2806 * | :----: | :----: | :---- | 2807 * |[4:0] |PI4MFP |PI.4 Multi-function Pin Selection 2808 * |[12:8] |PI5MFP |PI.5 Multi-function Pin Selection 2809 * |[20:16] |PI6MFP |PI.6 Multi-function Pin Selection 2810 * | | |00 = GPIO 2811 * | | |05 = SC1_nCD 2812 * | | |06 = I2S0_BCLK 2813 * | | |07 = SPI1_I2SMCLK 2814 * | | |08 = UART2_TXD 2815 * | | |09 = I2C1_SCL 2816 * | | |13 = CAN3_TXD 2817 * | | |15 = USB_VBUS_ST 2818 * |[28:24] |PI7MFP |PI.7 Multi-function Pin Selection 2819 * | | |00 = GPIO 2820 * | | |05 = SC1_PWR 2821 * | | |06 = I2S0_MCLK 2822 * | | |07 = SPI1_MISO 2823 * | | |08 = UART2_RXD 2824 * | | |09 = I2C1_SDA 2825 * | | |13 = CAN3_RXD 2826 * | | |15 = USB_VBUS_EN 2827 * @var SYS_T::GPI_MFP2 2828 * Offset: 0x588 GPIOI Multiple Function Control Register 2 2829 * --------------------------------------------------------------------------------------------------- 2830 * |Bits |Field |Descriptions 2831 * | :----: | :----: | :---- | 2832 * |[4:0] |PI8MFP |PI.8 Multi-function Pin Selection 2833 * | | |00 = GPIO 2834 * | | |05 = SC1_RST 2835 * | | |06 = I2S0_DI 2836 * | | |07 = SPI1_MOSI 2837 * | | |08 = UART2_nRTS 2838 * | | |09 = I2C0_SMBAL 2839 * | | |13 = CAN2_TXD 2840 * |[12:8] |PI9MFP |PI.9 Multi-function Pin Selection 2841 * | | |00 = GPIO 2842 * | | |05 = SC1_DAT 2843 * | | |06 = I2S0_DO 2844 * | | |07 = SPI1_CLK 2845 * | | |08 = UART2_nCTS 2846 * | | |09 = I2C0_SMBSUS 2847 * | | |13 = CAN2_RXD 2848 * |[20:16] |PI10MFP |PI.10 Multi-function Pin Selection 2849 * | | |00 = GPIO 2850 * | | |05 = SC1_CLK 2851 * | | |06 = I2S0_LRCK 2852 * | | |07 = SPI1_SS 2853 * | | |08 = UART2_TXD 2854 * | | |09 = I2C0_SCL 2855 * | | |13 = CAN3_TXD 2856 * |[28:24] |PI11MFP |PI.11 Multi-function Pin Selection 2857 * | | |00 = GPIO 2858 * | | |08 = UART2_RXD 2859 * | | |09 = I2C0_SDA 2860 * | | |13 = CAN3_RXD 2861 * @var SYS_T::GPI_MFP3 2862 * Offset: 0x58C GPIOI Multiple Function Control Register 3 2863 * --------------------------------------------------------------------------------------------------- 2864 * |Bits |Field |Descriptions 2865 * | :----: | :----: | :---- | 2866 * |[4:0] |PI12MFP |PI.12 Multi-function Pin Selection 2867 * | | |00 = GPIO 2868 * | | |03 = SPIM_SS 2869 * | | |04 = QSPI0_MISO1 2870 * | | |10 = CAN0_TXD 2871 * | | |11 = UART4_TXD 2872 * | | |12 = EPWM1_CH0 2873 * | | |15 = I2C3_SMBAL 2874 * |[12:8] |PI13MFP |PI.13 Multi-function Pin Selection 2875 * | | |00 = GPIO 2876 * | | |03 = SPIM_MISO 2877 * | | |04 = QSPI0_MOSI1 2878 * | | |10 = CAN0_RXD 2879 * | | |11 = UART4_RXD 2880 * | | |12 = EPWM1_CH1 2881 * | | |15 = I2C3_SMBSUS 2882 * |[20:16] |PI14MFP |PI.14 Multi-function Pin Selection 2883 * | | |00 = GPIO 2884 * | | |03 = SPIM_D2 2885 * | | |04 = QSPI0_SS 2886 * | | |07 = UART8_nCTS 2887 * | | |10 = CAN1_TXD 2888 * | | |11 = UART3_TXD 2889 * | | |12 = EPWM1_CH2 2890 * | | |15 = I2C3_SCL 2891 * |[28:24] |PI15MFP |PI.15 Multi-function Pin Selection 2892 * | | |00 = GPIO 2893 * | | |03 = SPIM_D3 2894 * | | |04 = QSPI0_CLK 2895 * | | |07 = UART8_nRTS 2896 * | | |10 = CAN1_RXD 2897 * | | |11 = UART3_RXD 2898 * | | |12 = EPWM1_CH3 2899 * | | |15 = I2C3_SDA 2900 * @var SYS_T::GPJ_MFP0 2901 * Offset: 0x590 GPIOJ Multiple Function Control Register 0 2902 * --------------------------------------------------------------------------------------------------- 2903 * |Bits |Field |Descriptions 2904 * | :----: | :----: | :---- | 2905 * |[4:0] |PJ0MFP |PJ.0 Multi-function Pin Selection 2906 * | | |00 = GPIO 2907 * | | |03 = SPIM_CLK 2908 * | | |04 = QSPI0_MISO0 2909 * | | |07 = UART8_TXD 2910 * | | |10 = CAN2_TXD 2911 * | | |12 = EPWM1_CH4 2912 * |[12:8] |PJ1MFP |PJ.1 Multi-function Pin Selection 2913 * | | |00 = GPIO 2914 * | | |03 = SPIM_MOSI 2915 * | | |04 = QSPI0_MOSI0 2916 * | | |07 = UART8_RXD 2917 * | | |10 = CAN2_RXD 2918 * | | |12 = EPWM1_CH5 2919 * |[20:16] |PJ2MFP |PJ.2 Multi-function Pin Selection 2920 * | | |00 = GPIO 2921 * | | |02 = EBI_AD5 2922 * | | |03 = UART8_nCTS 2923 * | | |06 = QSPI1_SS 2924 * | | |07 = CCAP_DATA5 2925 * | | |10 = CAN0_TXD 2926 * | | |16 = HBI_nRESET 2927 * |[28:24] |PJ3MFP |PJ.3 Multi-function Pin Selection 2928 * | | |00 = GPIO 2929 * | | |02 = EBI_AD4 2930 * | | |03 = UART8_nRTS 2931 * | | |06 = QSPI1_CLK 2932 * | | |07 = CCAP_DATA4 2933 * | | |10 = CAN0_RXD 2934 * | | |16 = HBI_D7 2935 * @var SYS_T::GPJ_MFP1 2936 * Offset: 0x594 GPIOJ Multiple Function Control Register 1 2937 * --------------------------------------------------------------------------------------------------- 2938 * |Bits |Field |Descriptions 2939 * | :----: | :----: | :---- | 2940 * |[4:0] |PJ4MFP |PJ.4 Multi-function Pin Selection 2941 * | | |00 = GPIO 2942 * | | |02 = EBI_AD3 2943 * | | |03 = UART8_TXD 2944 * | | |06 = QSPI1_MISO0 2945 * | | |07 = CCAP_DATA3 2946 * | | |10 = CAN1_TXD 2947 * | | |16 = HBI_D2 2948 * |[12:8] |PJ5MFP |PJ.5 Multi-function Pin Selection 2949 * | | |00 = GPIO 2950 * | | |02 = EBI_AD2 2951 * | | |03 = UART8_RXD 2952 * | | |06 = QSPI1_MOSI0 2953 * | | |07 = CCAP_DATA2 2954 * | | |10 = CAN1_RXD 2955 * | | |16 = HBI_D1 2956 * |[20:16] |PJ6MFP |PJ.6 Multi-function Pin Selection 2957 * | | |00 = GPIO 2958 * | | |02 = EBI_AD1 2959 * | | |03 = UART9_nCTS 2960 * | | |07 = CCAP_DATA1 2961 * | | |10 = CAN2_TXD 2962 * | | |16 = HBI_D0 2963 * |[28:24] |PJ7MFP |PJ.7 Multi-function Pin Selection 2964 * | | |00 = GPIO 2965 * | | |02 = EBI_AD0 2966 * | | |03 = UART9_nRTS 2967 * | | |07 = CCAP_DATA0 2968 * | | |10 = CAN2_RXD 2969 * | | |16 = HBI_nCS 2970 * @var SYS_T::GPJ_MFP2 2971 * Offset: 0x598 GPIOJ Multiple Function Control Register 2 2972 * --------------------------------------------------------------------------------------------------- 2973 * |Bits |Field |Descriptions 2974 * | :----: | :----: | :---- | 2975 * |[4:0] |PJ8MFP |PJ.8 Multi-function Pin Selection 2976 * | | |00 = GPIO 2977 * | | |02 = EBI_nRD 2978 * | | |03 = SD1_DAT3 2979 * | | |04 = SPIM_SS 2980 * | | |06 = UART7_TXD 2981 * | | |11 = CAN2_TXD 2982 * | | |12 = BPWM0_CH5 2983 * |[12:8] |PJ9MFP |PJ.9 Multi-function Pin Selection 2984 * | | |00 = GPIO 2985 * | | |02 = EBI_nWR 2986 * | | |03 = SD1_DAT2 2987 * | | |04 = SPIM_MISO 2988 * | | |06 = UART7_RXD 2989 * | | |11 = CAN2_RXD 2990 * | | |12 = BPWM0_CH4 2991 * |[20:16] |PJ10MFP |PJ.10 Multi-function Pin Selection 2992 * | | |00 = GPIO 2993 * | | |02 = EBI_MCLK 2994 * | | |03 = SD1_DAT1 2995 * | | |04 = SPIM_D2 2996 * | | |06 = UART6_TXD 2997 * | | |08 = I2C4_SCL 2998 * | | |09 = ECAP2_IC0 2999 * | | |11 = CAN0_TXD 3000 * | | |12 = BPWM0_CH3 3001 * |[28:24] |PJ11MFP |PJ.11 Multi-function Pin Selection 3002 * | | |00 = GPIO 3003 * | | |02 = EBI_ALE 3004 * | | |03 = SD1_DAT0 3005 * | | |04 = SPIM_D3 3006 * | | |06 = UART6_RXD 3007 * | | |08 = I2C4_SDA 3008 * | | |09 = ECAP2_IC1 3009 * | | |11 = CAN0_RXD 3010 * | | |12 = BPWM0_CH2 3011 * @var SYS_T::GPJ_MFP3 3012 * Offset: 0x59C GPIOJ Multiple Function Control Register 3 3013 * --------------------------------------------------------------------------------------------------- 3014 * |Bits |Field |Descriptions 3015 * | :----: | :----: | :---- | 3016 * |[4:0] |PJ12MFP |PJ.12 Multi-function Pin Selection 3017 * | | |00 = GPIO 3018 * | | |02 = EBI_nCS0 3019 * | | |03 = SD1_CMD 3020 * | | |04 = SPIM_CLK 3021 * | | |08 = I2C4_SMBAL 3022 * | | |09 = ECAP2_IC2 3023 * | | |11 = CAN1_TXD 3024 * | | |12 = BPWM0_CH1 3025 * | | |15 = HSUSB_VBUS_ST 3026 * |[12:8] |PJ13MFP |PJ.13 Multi-function Pin Selection 3027 * | | |00 = GPIO 3028 * | | |03 = SD1_CLK 3029 * | | |04 = SPIM_MOSI 3030 * | | |08 = I2C4_SMBSUS 3031 * | | |11 = CAN1_RXD 3032 * | | |12 = BPWM0_CH0 3033 * | | |15 = HSUSB_VBUS_EN 3034 */ 3035 __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ 3036 __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ 3037 __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ 3038 __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ 3039 __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ 3040 __I uint32_t RESERVE0[1]; 3041 __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ 3042 __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ 3043 __IO uint32_t IPRST3; /*!< [0x0020] Peripheral Reset Control Register 3 */ 3044 __IO uint32_t PORCTL; /*!< [0x0024] Power-On-reset Controller Register */ 3045 __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ 3046 __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ 3047 __I uint32_t RESERVE1[20]; 3048 __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ 3049 __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ 3050 __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ 3051 __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ 3052 __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ 3053 __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ 3054 __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ 3055 __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ 3056 __IO uint32_t GPI_MFOS; /*!< [0x00A0] GPIOI Multiple Function Output Select Register */ 3057 __IO uint32_t GPJ_MFOS; /*!< [0x00A4] GPIOJ Multiple Function Output Select Register */ 3058 __I uint32_t RESERVE2[2]; 3059 __I uint32_t RESERVE3[4]; 3060 __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ 3061 __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ 3062 __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ 3063 __I uint32_t RESERVE4[1]; 3064 __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ 3065 __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ 3066 __I uint32_t RESERVE5[3]; 3067 __IO uint32_t HIRCTCTL; /*!< [0x00e4] HIRC48M Trim Control Register */ 3068 __IO uint32_t HIRCTIEN; /*!< [0x00e8] HIRC48M Trim Interrupt Enable Register */ 3069 __IO uint32_t HIRCTISTS; /*!< [0x00ec] HIRC48M Trim Interrupt Status Register */ 3070 __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ 3071 __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ 3072 __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ 3073 __I uint32_t RESERVE6[1]; 3074 __O uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ 3075 __I uint32_t RESERVE7[58]; 3076 __IO uint32_t PORDISAN; /*!< [0x01ec] Analog POR Disable Control Register */ 3077 __I uint32_t RESERVE8[1]; 3078 __I uint32_t CSERVER; /*!< [0x01f4] Chip Series Version Register */ 3079 __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ 3080 __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ 3081 __I uint32_t RESERVE9[128]; 3082 __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ 3083 __I uint32_t RESERVE10[63]; 3084 __IO uint32_t GPA_MFP0; /*!< [0x0500] GPIOA Multiple Function Control Register 0 */ 3085 __IO uint32_t GPA_MFP1; /*!< [0x0504] GPIOA Multiple Function Control Register 1 */ 3086 __IO uint32_t GPA_MFP2; /*!< [0x0508] GPIOA Multiple Function Control Register 2 */ 3087 __IO uint32_t GPA_MFP3; /*!< [0x050c] GPIOA Multiple Function Control Register 3 */ 3088 __IO uint32_t GPB_MFP0; /*!< [0x0510] GPIOB Multiple Function Control Register 0 */ 3089 __IO uint32_t GPB_MFP1; /*!< [0x0514] GPIOB Multiple Function Control Register 1 */ 3090 __IO uint32_t GPB_MFP2; /*!< [0x0518] GPIOB Multiple Function Control Register 2 */ 3091 __IO uint32_t GPB_MFP3; /*!< [0x051c] GPIOB Multiple Function Control Register 3 */ 3092 __IO uint32_t GPC_MFP0; /*!< [0x0520] GPIOC Multiple Function Control Register 0 */ 3093 __IO uint32_t GPC_MFP1; /*!< [0x0524] GPIOC Multiple Function Control Register 1 */ 3094 __IO uint32_t GPC_MFP2; /*!< [0x0528] GPIOC Multiple Function Control Register 2 */ 3095 __IO uint32_t GPC_MFP3; /*!< [0x052c] GPIOC Multiple Function Control Register 3 */ 3096 __IO uint32_t GPD_MFP0; /*!< [0x0530] GPIOD Multiple Function Control Register 0 */ 3097 __IO uint32_t GPD_MFP1; /*!< [0x0534] GPIOD Multiple Function Control Register 1 */ 3098 __IO uint32_t GPD_MFP2; /*!< [0x0538] GPIOD Multiple Function Control Register 2 */ 3099 __IO uint32_t GPD_MFP3; /*!< [0x053c] GPIOD Multiple Function Control Register 3 */ 3100 __IO uint32_t GPE_MFP0; /*!< [0x0540] GPIOE Multiple Function Control Register 0 */ 3101 __IO uint32_t GPE_MFP1; /*!< [0x0544] GPIOE Multiple Function Control Register 1 */ 3102 __IO uint32_t GPE_MFP2; /*!< [0x0548] GPIOE Multiple Function Control Register 2 */ 3103 __IO uint32_t GPE_MFP3; /*!< [0x054c] GPIOE Multiple Function Control Register 3 */ 3104 __IO uint32_t GPF_MFP0; /*!< [0x0550] GPIOF Multiple Function Control Register 0 */ 3105 __IO uint32_t GPF_MFP1; /*!< [0x0554] GPIOF Multiple Function Control Register 1 */ 3106 __IO uint32_t GPF_MFP2; /*!< [0x0558] GPIOF Multiple Function Control Register 2 */ 3107 __IO uint32_t GPF_MFP3; /*!< [0x055c] GPIOF Multiple Function Control Register 3 */ 3108 __IO uint32_t GPG_MFP0; /*!< [0x0560] GPIOG Multiple Function Control Register 0 */ 3109 __IO uint32_t GPG_MFP1; /*!< [0x0564] GPIOG Multiple Function Control Register 1 */ 3110 __IO uint32_t GPG_MFP2; /*!< [0x0568] GPIOG Multiple Function Control Register 2 */ 3111 __IO uint32_t GPG_MFP3; /*!< [0x056c] GPIOG Multiple Function Control Register 3 */ 3112 __IO uint32_t GPH_MFP0; /*!< [0x0570] GPIOH Multiple Function Control Register 0 */ 3113 __IO uint32_t GPH_MFP1; /*!< [0x0574] GPIOH Multiple Function Control Register 1 */ 3114 __IO uint32_t GPH_MFP2; /*!< [0x0578] GPIOH Multiple Function Control Register 2 */ 3115 __IO uint32_t GPH_MFP3; /*!< [0x057c] GPIOH Multiple Function Control Register 3 */ 3116 __IO uint32_t GPI_MFP0; /*!< [0x0580] GPIOI Multiple Function Control Register 0 */ 3117 __IO uint32_t GPI_MFP1; /*!< [0x0584] GPIOI Multiple Function Control Register 1 */ 3118 __IO uint32_t GPI_MFP2; /*!< [0x0588] GPIOI Multiple Function Control Register 2 */ 3119 __IO uint32_t GPI_MFP3; /*!< [0x058c] GPIOI Multiple Function Control Register 3 */ 3120 __IO uint32_t GPJ_MFP0; /*!< [0x0590] GPIOJ Multiple Function Control Register 0 */ 3121 __IO uint32_t GPJ_MFP1; /*!< [0x0594] GPIOJ Multiple Function Control Register 1 */ 3122 __IO uint32_t GPJ_MFP2; /*!< [0x0598] GPIOJ Multiple Function Control Register 2 */ 3123 __IO uint32_t GPJ_MFP3; /*!< [0x059c] GPIOJ Multiple Function Control Register 3 */ 3124 3125 } SYS_T; 3126 3127 /** 3128 @addtogroup SYS_CONST SYS Bit Field Definition 3129 Constant Definitions for SYS Controller 3130 @{ */ 3131 3132 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ 3133 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ 3134 3135 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ 3136 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ 3137 3138 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ 3139 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ 3140 3141 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ 3142 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ 3143 3144 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ 3145 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ 3146 3147 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ 3148 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ 3149 3150 #define SYS_RSTSTS_MCURF_Pos (5) /*!< SYS_T::RSTSTS: MCURF Position */ 3151 #define SYS_RSTSTS_MCURF_Msk (0x1ul << SYS_RSTSTS_MCURF_Pos) /*!< SYS_T::RSTSTS: MCURF Mask */ 3152 3153 #define SYS_RSTSTS_HRESETRF_Pos (6) /*!< SYS_T::RSTSTS: HRESETRF Position */ 3154 #define SYS_RSTSTS_HRESETRF_Msk (0x1ul << SYS_RSTSTS_HRESETRF_Pos) /*!< SYS_T::RSTSTS: HRESETRF Mask */ 3155 3156 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ 3157 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ 3158 3159 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ 3160 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ 3161 3162 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ 3163 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ 3164 3165 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ 3166 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ 3167 3168 #define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ 3169 #define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ 3170 3171 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ 3172 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ 3173 3174 #define SYS_IPRST0_EMAC0RST_Pos (5) /*!< SYS_T::IPRST0: EMAC0RST Position */ 3175 #define SYS_IPRST0_EMAC0RST_Msk (0x1ul << SYS_IPRST0_EMAC0RST_Pos) /*!< SYS_T::IPRST0: EMAC0RST Mask */ 3176 3177 #define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ 3178 #define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ 3179 3180 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ 3181 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ 3182 3183 #define SYS_IPRST0_CCAPRST_Pos (8) /*!< SYS_T::IPRST0: CCAPRST Position */ 3184 #define SYS_IPRST0_CCAPRST_Msk (0x1ul << SYS_IPRST0_CCAPRST_Pos) /*!< SYS_T::IPRST0: CCAPRST Mask */ 3185 3186 #define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ 3187 #define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ 3188 3189 #define SYS_IPRST0_HBIRST_Pos (11) /*!< SYS_T::IPRST0: HBIRST Position */ 3190 #define SYS_IPRST0_HBIRST_Msk (0x1ul << SYS_IPRST0_HBIRST_Pos) /*!< SYS_T::IPRST0: HBIRST Mask */ 3191 3192 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ 3193 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ 3194 3195 #define SYS_IPRST0_KSRST_Pos (13) /*!< SYS_T::IPRST0: KSRST Position */ 3196 #define SYS_IPRST0_KSRST_Msk (0x1ul << SYS_IPRST0_KSRST_Pos) /*!< SYS_T::IPRST0: KSRST Mask */ 3197 3198 #define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ 3199 #define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ 3200 3201 #define SYS_IPRST0_HSUSBHRST_Pos (16) /*!< SYS_T::IPRST0: HSUSBHRST Position */ 3202 #define SYS_IPRST0_HSUSBHRST_Msk (0x1ul << SYS_IPRST0_HSUSBHRST_Pos) /*!< SYS_T::IPRST0: HSUSBHRST Mask */ 3203 3204 #define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ 3205 #define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ 3206 3207 #define SYS_IPRST0_PDMA1RST_Pos (18) /*!< SYS_T::IPRST0: PDMA1RST Position */ 3208 #define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ 3209 3210 #define SYS_IPRST0_CANFD0RST_Pos (20) /*!< SYS_T::IPRST0: CANFD0RST Position */ 3211 #define SYS_IPRST0_CANFD0RST_Msk (0x1ul << SYS_IPRST0_CANFD0RST_Pos) /*!< SYS_T::IPRST0: CANFD0RST Mask */ 3212 3213 #define SYS_IPRST0_CANFD1RST_Pos (21) /*!< SYS_T::IPRST0: CANFD1RST Position */ 3214 #define SYS_IPRST0_CANFD1RST_Msk (0x1ul << SYS_IPRST0_CANFD1RST_Pos) /*!< SYS_T::IPRST0: CANFD1RST Mask */ 3215 3216 #define SYS_IPRST0_CANFD2RST_Pos (22) /*!< SYS_T::IPRST0: CANFD2RST Position */ 3217 #define SYS_IPRST0_CANFD2RST_Msk (0x1ul << SYS_IPRST0_CANFD2RST_Pos) /*!< SYS_T::IPRST0: CANFD2RST Mask */ 3218 3219 #define SYS_IPRST0_CANFD3RST_Pos (23) /*!< SYS_T::IPRST0: CANFD3RST Position */ 3220 #define SYS_IPRST0_CANFD3RST_Msk (0x1ul << SYS_IPRST0_CANFD3RST_Pos) /*!< SYS_T::IPRST0: CANFD3RST Mask */ 3221 3222 #define SYS_IPRST0_BMCRST_Pos (28) /*!< SYS_T::IPRST0: BMCRST Position */ 3223 #define SYS_IPRST0_BMCRST_Msk (0x1ul << SYS_IPRST0_BMCRST_Pos) /*!< SYS_T::IPRST0: BMCRST Mask */ 3224 3225 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ 3226 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ 3227 3228 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ 3229 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ 3230 3231 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ 3232 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ 3233 3234 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ 3235 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ 3236 3237 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ 3238 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ 3239 3240 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ 3241 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ 3242 3243 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ 3244 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ 3245 3246 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ 3247 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ 3248 3249 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ 3250 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ 3251 3252 #define SYS_IPRST1_I2C3RST_Pos (11) /*!< SYS_T::IPRST1: I2C3RST Position */ 3253 #define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /*!< SYS_T::IPRST1: I2C3RST Mask */ 3254 3255 #define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ 3256 #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ 3257 3258 #define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ 3259 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ 3260 3261 #define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ 3262 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ 3263 3264 #define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ 3265 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ 3266 3267 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ 3268 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ 3269 3270 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ 3271 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ 3272 3273 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ 3274 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ 3275 3276 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ 3277 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ 3278 3279 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ 3280 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ 3281 3282 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ 3283 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ 3284 3285 #define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */ 3286 #define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */ 3287 3288 #define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */ 3289 #define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */ 3290 3291 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ 3292 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ 3293 3294 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ 3295 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ 3296 3297 #define SYS_IPRST1_EADC0RST_Pos (28) /*!< SYS_T::IPRST1: EADC0RST Position */ 3298 #define SYS_IPRST1_EADC0RST_Msk (0x1ul << SYS_IPRST1_EADC0RST_Pos) /*!< SYS_T::IPRST1: EADC0RST Mask */ 3299 3300 #define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ 3301 #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ 3302 3303 #define SYS_IPRST1_HSOTGRST_Pos (30) /*!< SYS_T::IPRST1: HSOTGRST Position */ 3304 #define SYS_IPRST1_HSOTGRST_Msk (0x1ul << SYS_IPRST1_HSOTGRST_Pos) /*!< SYS_T::IPRST1: HSOTGRST Mask */ 3305 3306 #define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ 3307 #define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ 3308 3309 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ 3310 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ 3311 3312 #define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ 3313 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ 3314 3315 #define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ 3316 #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ 3317 3318 #define SYS_IPRST2_I2C4RST_Pos (3) /*!< SYS_T::IPRST2: I2C4RST Position */ 3319 #define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) /*!< SYS_T::IPRST2: I2C4RST Mask */ 3320 3321 #define SYS_IPRST2_QSPI1RST_Pos (4) /*!< SYS_T::IPRST2: QSPI1RST Position */ 3322 #define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) /*!< SYS_T::IPRST2: QSPI1RST Mask */ 3323 3324 #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ 3325 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ 3326 3327 #define SYS_IPRST2_SPI4RST_Pos (7) /*!< SYS_T::IPRST2: SPI4RST Position */ 3328 #define SYS_IPRST2_SPI4RST_Msk (0x1ul << SYS_IPRST2_SPI4RST_Pos) /*!< SYS_T::IPRST2: SPI4RST Mask */ 3329 3330 #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ 3331 #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ 3332 3333 #define SYS_IPRST2_PSIORST_Pos (10) /*!< SYS_T::IPRST2: PSIORST Position */ 3334 #define SYS_IPRST2_PSIORST_Msk (0x1ul << SYS_IPRST2_PSIORST_Pos) /*!< SYS_T::IPRST2: PSIORST Mask */ 3335 3336 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ 3337 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ 3338 3339 #define SYS_IPRST2_ECAP2RST_Pos (13) /*!< SYS_T::IPRST2: ECAP2RST Position */ 3340 #define SYS_IPRST2_ECAP2RST_Msk (0x1ul << SYS_IPRST2_ECAP2RST_Pos) /*!< SYS_T::IPRST2: ECAP2RST Mask */ 3341 3342 #define SYS_IPRST2_ECAP3RST_Pos (14) /*!< SYS_T::IPRST2: ECAP3RST Position */ 3343 #define SYS_IPRST2_ECAP3RST_Msk (0x1ul << SYS_IPRST2_ECAP3RST_Pos) /*!< SYS_T::IPRST2: ECAP3RST Mask */ 3344 3345 #define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ 3346 #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ 3347 3348 #define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ 3349 #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ 3350 3351 #define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ 3352 #define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ 3353 3354 #define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ 3355 #define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ 3356 3357 #define SYS_IPRST2_EQEI2RST_Pos (20) /*!< SYS_T::IPRST2: EQEI2RST Position */ 3358 #define SYS_IPRST2_EQEI2RST_Msk (0x1ul << SYS_IPRST2_EQEI2RST_Pos) /*!< SYS_T::IPRST2: EQEI2RST Mask */ 3359 3360 #define SYS_IPRST2_EQEI3RST_Pos (21) /*!< SYS_T::IPRST2: EQEI3RST Position */ 3361 #define SYS_IPRST2_EQEI3RST_Msk (0x1ul << SYS_IPRST2_EQEI3RST_Pos) /*!< SYS_T::IPRST2: EQEI3RST Mask */ 3362 3363 #define SYS_IPRST2_EQEI0RST_Pos (22) /*!< SYS_T::IPRST2: EQEI0RST Position */ 3364 #define SYS_IPRST2_EQEI0RST_Msk (0x1ul << SYS_IPRST2_EQEI0RST_Pos) /*!< SYS_T::IPRST2: EQEI0RST Mask */ 3365 3366 #define SYS_IPRST2_EQEI1RST_Pos (23) /*!< SYS_T::IPRST2: EQEI1RST Position */ 3367 #define SYS_IPRST2_EQEI1RST_Msk (0x1ul << SYS_IPRST2_EQEI1RST_Pos) /*!< SYS_T::IPRST2: EQEI1RST Mask */ 3368 3369 #define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ 3370 #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ 3371 3372 #define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ 3373 #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ 3374 3375 #define SYS_IPRST2_I2S1RST_Pos (29) /*!< SYS_T::IPRST2: I2S1RST Position */ 3376 #define SYS_IPRST2_I2S1RST_Msk (0x1ul << SYS_IPRST2_I2S1RST_Pos) /*!< SYS_T::IPRST2: I2S1RST Mask */ 3377 3378 #define SYS_IPRST2_EADC1RST_Pos (31) /*!< SYS_T::IPRST2: EADC1RST Position */ 3379 #define SYS_IPRST2_EADC1RST_Msk (0x1ul << SYS_IPRST2_EADC1RST_Pos) /*!< SYS_T::IPRST2: EADC1RST Mask */ 3380 3381 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ 3382 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ 3383 3384 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ 3385 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ 3386 3387 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ 3388 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ 3389 3390 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ 3391 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ 3392 3393 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ 3394 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ 3395 3396 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ 3397 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ 3398 3399 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ 3400 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ 3401 3402 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ 3403 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ 3404 3405 #define SYS_BODCTL_LVRRDY_Pos (15) /*!< SYS_T::BODCTL: LVRRDY Position */ 3406 #define SYS_BODCTL_LVRRDY_Msk (0x1ul << SYS_BODCTL_LVRRDY_Pos) /*!< SYS_T::BODCTL: LVRRDY Mask */ 3407 3408 #define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ 3409 #define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ 3410 3411 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ 3412 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ 3413 3414 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ 3415 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ 3416 3417 #define SYS_IPRST3_KPIRST_Pos (0) /*!< SYS_T::IPRST3: KPIRST Position */ 3418 #define SYS_IPRST3_KPIRST_Msk (0x1ul << SYS_IPRST3_KPIRST_Pos) /*!< SYS_T::IPRST3: KPIRST Mask */ 3419 3420 #define SYS_IPRST3_EADC2RST_Pos (6) /*!< SYS_T::IPRST3: EADC2RST Position */ 3421 #define SYS_IPRST3_EADC2RST_Msk (0x1ul << SYS_IPRST3_EADC2RST_Pos) /*!< SYS_T::IPRST3: EADC2RST Mask */ 3422 3423 #define SYS_IPRST3_ACMP23RST_Pos (7) /*!< SYS_T::IPRST3: ACMP23RST Position */ 3424 #define SYS_IPRST3_ACMP23RST_Msk (0x1ul << SYS_IPRST3_ACMP23RST_Pos) /*!< SYS_T::IPRST3: ACMP23RST Mask */ 3425 3426 #define SYS_IPRST3_SPI5RST_Pos (8) /*!< SYS_T::IPRST3: SPI5RST Position */ 3427 #define SYS_IPRST3_SPI5RST_Msk (0x1ul << SYS_IPRST3_SPI5RST_Pos) /*!< SYS_T::IPRST3: SPI5RST Mask */ 3428 3429 #define SYS_IPRST3_SPI6RST_Pos (9) /*!< SYS_T::IPRST3: SPI6RST Position */ 3430 #define SYS_IPRST3_SPI6RST_Msk (0x1ul << SYS_IPRST3_SPI6RST_Pos) /*!< SYS_T::IPRST3: SPI6RST Mask */ 3431 3432 #define SYS_IPRST3_SPI7RST_Pos (10) /*!< SYS_T::IPRST3: SPI7RST Position */ 3433 #define SYS_IPRST3_SPI7RST_Msk (0x1ul << SYS_IPRST3_SPI7RST_Pos) /*!< SYS_T::IPRST3: SPI7RST Mask */ 3434 3435 #define SYS_IPRST3_SPI8RST_Pos (11) /*!< SYS_T::IPRST3: SPI8RST Position */ 3436 #define SYS_IPRST3_SPI8RST_Msk (0x1ul << SYS_IPRST3_SPI8RST_Pos) /*!< SYS_T::IPRST3: SPI8RST Mask */ 3437 3438 #define SYS_IPRST3_SPI9RST_Pos (12) /*!< SYS_T::IPRST3: SPI9RST Position */ 3439 #define SYS_IPRST3_SPI9RST_Msk (0x1ul << SYS_IPRST3_SPI9RST_Pos) /*!< SYS_T::IPRST3: SPI9RST Mask */ 3440 3441 #define SYS_IPRST3_SPI10RST_Pos (13) /*!< SYS_T::IPRST3: SPI10RST Position */ 3442 #define SYS_IPRST3_SPI10RST_Msk (0x1ul << SYS_IPRST3_SPI10RST_Pos) /*!< SYS_T::IPRST3: SPI10RST Mask */ 3443 3444 #define SYS_IPRST3_UART8RST_Pos (16) /*!< SYS_T::IPRST3: UART8RST Position */ 3445 #define SYS_IPRST3_UART8RST_Msk (0x1ul << SYS_IPRST3_UART8RST_Pos) /*!< SYS_T::IPRST3: UART8RST Mask */ 3446 3447 #define SYS_IPRST3_UART9RST_Pos (17) /*!< SYS_T::IPRST3: UART9RST Position */ 3448 #define SYS_IPRST3_UART9RST_Msk (0x1ul << SYS_IPRST3_UART9RST_Pos) /*!< SYS_T::IPRST3: UART9RST Mask */ 3449 3450 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ 3451 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ 3452 3453 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ 3454 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ 3455 3456 #define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */ 3457 #define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */ 3458 3459 #define SYS_VREFCTL_VBGFEN_Pos (24) /*!< SYS_T::VREFCTL: VBGFEN Position */ 3460 #define SYS_VREFCTL_VBGFEN_Msk (0x1ul << SYS_VREFCTL_VBGFEN_Pos) /*!< SYS_T::VREFCTL: VBGFEN Mask */ 3461 3462 #define SYS_VREFCTL_VBGISEL_Pos (25) /*!< SYS_T::VREFCTL: VBGISEL Position */ 3463 #define SYS_VREFCTL_VBGISEL_Msk (0x3ul << SYS_VREFCTL_VBGISEL_Pos) /*!< SYS_T::VREFCTL: VBGISEL Mask */ 3464 3465 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ 3466 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ 3467 3468 #define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ 3469 #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ 3470 3471 #define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ 3472 #define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ 3473 3474 #define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ 3475 #define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ 3476 3477 #define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ 3478 #define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ 3479 3480 #define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ 3481 #define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ 3482 3483 #define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ 3484 #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ 3485 3486 #define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ 3487 #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ 3488 3489 #define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ 3490 #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ 3491 3492 #define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ 3493 #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ 3494 3495 #define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ 3496 #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ 3497 3498 #define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ 3499 #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ 3500 3501 #define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ 3502 #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ 3503 3504 #define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ 3505 #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ 3506 3507 #define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ 3508 #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ 3509 3510 #define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ 3511 #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ 3512 3513 #define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ 3514 #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ 3515 3516 #define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ 3517 #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ 3518 3519 #define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ 3520 #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ 3521 3522 #define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ 3523 #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ 3524 3525 #define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ 3526 #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ 3527 3528 #define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ 3529 #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ 3530 3531 #define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ 3532 #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ 3533 3534 #define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ 3535 #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ 3536 3537 #define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ 3538 #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ 3539 3540 #define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ 3541 #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ 3542 3543 #define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ 3544 #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ 3545 3546 #define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ 3547 #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ 3548 3549 #define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ 3550 #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ 3551 3552 #define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ 3553 #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ 3554 3555 #define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ 3556 #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ 3557 3558 #define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ 3559 #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ 3560 3561 #define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ 3562 #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ 3563 3564 #define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ 3565 #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ 3566 3567 #define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ 3568 #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ 3569 3570 #define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ 3571 #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ 3572 3573 #define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ 3574 #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ 3575 3576 #define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ 3577 #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ 3578 3579 #define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ 3580 #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ 3581 3582 #define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ 3583 #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ 3584 3585 #define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ 3586 #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ 3587 3588 #define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ 3589 #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ 3590 3591 #define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ 3592 #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ 3593 3594 #define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ 3595 #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ 3596 3597 #define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ 3598 #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ 3599 3600 #define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ 3601 #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ 3602 3603 #define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ 3604 #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ 3605 3606 #define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ 3607 #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ 3608 3609 #define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ 3610 #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ 3611 3612 #define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ 3613 #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ 3614 3615 #define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ 3616 #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ 3617 3618 #define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ 3619 #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ 3620 3621 #define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ 3622 #define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ 3623 3624 #define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ 3625 #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ 3626 3627 #define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ 3628 #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ 3629 3630 #define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ 3631 #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ 3632 3633 #define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ 3634 #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ 3635 3636 #define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ 3637 #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ 3638 3639 #define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ 3640 #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ 3641 3642 #define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ 3643 #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ 3644 3645 #define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ 3646 #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ 3647 3648 #define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ 3649 #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ 3650 3651 #define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ 3652 #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ 3653 3654 #define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ 3655 #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ 3656 3657 #define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ 3658 #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ 3659 3660 #define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ 3661 #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ 3662 3663 #define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ 3664 #define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ 3665 3666 #define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ 3667 #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ 3668 3669 #define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ 3670 #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ 3671 3672 #define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ 3673 #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ 3674 3675 #define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ 3676 #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ 3677 3678 #define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ 3679 #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ 3680 3681 #define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ 3682 #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ 3683 3684 #define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ 3685 #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ 3686 3687 #define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ 3688 #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ 3689 3690 #define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ 3691 #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ 3692 3693 #define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ 3694 #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ 3695 3696 #define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ 3697 #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ 3698 3699 #define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ 3700 #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ 3701 3702 #define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ 3703 #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ 3704 3705 #define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ 3706 #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ 3707 3708 #define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ 3709 #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ 3710 3711 #define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ 3712 #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ 3713 3714 #define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ 3715 #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ 3716 3717 #define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ 3718 #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ 3719 3720 #define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ 3721 #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ 3722 3723 #define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ 3724 #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ 3725 3726 #define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ 3727 #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ 3728 3729 #define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ 3730 #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ 3731 3732 #define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ 3733 #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ 3734 3735 #define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ 3736 #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ 3737 3738 #define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ 3739 #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ 3740 3741 #define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ 3742 #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ 3743 3744 #define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ 3745 #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ 3746 3747 #define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ 3748 #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ 3749 3750 #define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ 3751 #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ 3752 3753 #define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ 3754 #define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ 3755 3756 #define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ 3757 #define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ 3758 3759 #define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ 3760 #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ 3761 3762 #define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ 3763 #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ 3764 3765 #define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ 3766 #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ 3767 3768 #define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ 3769 #define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ 3770 3771 #define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ 3772 #define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ 3773 3774 #define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ 3775 #define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ 3776 3777 #define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ 3778 #define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ 3779 3780 #define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ 3781 #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ 3782 3783 #define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ 3784 #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ 3785 3786 #define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ 3787 #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ 3788 3789 #define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ 3790 #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ 3791 3792 #define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ 3793 #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ 3794 3795 #define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ 3796 #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ 3797 3798 #define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ 3799 #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ 3800 3801 #define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ 3802 #define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ 3803 3804 #define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ 3805 #define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ 3806 3807 #define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ 3808 #define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ 3809 3810 #define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ 3811 #define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ 3812 3813 #define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ 3814 #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ 3815 3816 #define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ 3817 #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ 3818 3819 #define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ 3820 #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ 3821 3822 #define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ 3823 #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ 3824 3825 #define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ 3826 #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ 3827 3828 #define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ 3829 #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ 3830 3831 #define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ 3832 #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ 3833 3834 #define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ 3835 #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ 3836 3837 #define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ 3838 #define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ 3839 3840 #define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ 3841 #define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ 3842 3843 #define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ 3844 #define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ 3845 3846 #define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ 3847 #define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ 3848 3849 #define SYS_GPI_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPI_MFOS: MFOS6 Position */ 3850 #define SYS_GPI_MFOS_MFOS6_Msk (0x1ul << SYS_GPI_MFOS_MFOS6_Pos) /*!< SYS_T::GPI_MFOS: MFOS6 Mask */ 3851 3852 #define SYS_GPI_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPI_MFOS: MFOS7 Position */ 3853 #define SYS_GPI_MFOS_MFOS7_Msk (0x1ul << SYS_GPI_MFOS_MFOS7_Pos) /*!< SYS_T::GPI_MFOS: MFOS7 Mask */ 3854 3855 #define SYS_GPI_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPI_MFOS: MFOS8 Position */ 3856 #define SYS_GPI_MFOS_MFOS8_Msk (0x1ul << SYS_GPI_MFOS_MFOS8_Pos) /*!< SYS_T::GPI_MFOS: MFOS8 Mask */ 3857 3858 #define SYS_GPI_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPI_MFOS: MFOS9 Position */ 3859 #define SYS_GPI_MFOS_MFOS9_Msk (0x1ul << SYS_GPI_MFOS_MFOS9_Pos) /*!< SYS_T::GPI_MFOS: MFOS9 Mask */ 3860 3861 #define SYS_GPI_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPI_MFOS: MFOS10 Position */ 3862 #define SYS_GPI_MFOS_MFOS10_Msk (0x1ul << SYS_GPI_MFOS_MFOS10_Pos) /*!< SYS_T::GPI_MFOS: MFOS10 Mask */ 3863 3864 #define SYS_GPI_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPI_MFOS: MFOS11 Position */ 3865 #define SYS_GPI_MFOS_MFOS11_Msk (0x1ul << SYS_GPI_MFOS_MFOS11_Pos) /*!< SYS_T::GPI_MFOS: MFOS11 Mask */ 3866 3867 #define SYS_GPI_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPI_MFOS: MFOS12 Position */ 3868 #define SYS_GPI_MFOS_MFOS12_Msk (0x1ul << SYS_GPI_MFOS_MFOS12_Pos) /*!< SYS_T::GPI_MFOS: MFOS12 Mask */ 3869 3870 #define SYS_GPI_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPI_MFOS: MFOS13 Position */ 3871 #define SYS_GPI_MFOS_MFOS13_Msk (0x1ul << SYS_GPI_MFOS_MFOS13_Pos) /*!< SYS_T::GPI_MFOS: MFOS13 Mask */ 3872 3873 #define SYS_GPI_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPI_MFOS: MFOS14 Position */ 3874 #define SYS_GPI_MFOS_MFOS14_Msk (0x1ul << SYS_GPI_MFOS_MFOS14_Pos) /*!< SYS_T::GPI_MFOS: MFOS14 Mask */ 3875 3876 #define SYS_GPI_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPI_MFOS: MFOS15 Position */ 3877 #define SYS_GPI_MFOS_MFOS15_Msk (0x1ul << SYS_GPI_MFOS_MFOS15_Pos) /*!< SYS_T::GPI_MFOS: MFOS15 Mask */ 3878 3879 #define SYS_GPJ_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPJ_MFOS: MFOS0 Position */ 3880 #define SYS_GPJ_MFOS_MFOS0_Msk (0x1ul << SYS_GPJ_MFOS_MFOS0_Pos) /*!< SYS_T::GPJ_MFOS: MFOS0 Mask */ 3881 3882 #define SYS_GPJ_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPJ_MFOS: MFOS1 Position */ 3883 #define SYS_GPJ_MFOS_MFOS1_Msk (0x1ul << SYS_GPJ_MFOS_MFOS1_Pos) /*!< SYS_T::GPJ_MFOS: MFOS1 Mask */ 3884 3885 #define SYS_GPJ_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPJ_MFOS: MFOS2 Position */ 3886 #define SYS_GPJ_MFOS_MFOS2_Msk (0x1ul << SYS_GPJ_MFOS_MFOS2_Pos) /*!< SYS_T::GPJ_MFOS: MFOS2 Mask */ 3887 3888 #define SYS_GPJ_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPJ_MFOS: MFOS3 Position */ 3889 #define SYS_GPJ_MFOS_MFOS3_Msk (0x1ul << SYS_GPJ_MFOS_MFOS3_Pos) /*!< SYS_T::GPJ_MFOS: MFOS3 Mask */ 3890 3891 #define SYS_GPJ_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPJ_MFOS: MFOS4 Position */ 3892 #define SYS_GPJ_MFOS_MFOS4_Msk (0x1ul << SYS_GPJ_MFOS_MFOS4_Pos) /*!< SYS_T::GPJ_MFOS: MFOS4 Mask */ 3893 3894 #define SYS_GPJ_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPJ_MFOS: MFOS5 Position */ 3895 #define SYS_GPJ_MFOS_MFOS5_Msk (0x1ul << SYS_GPJ_MFOS_MFOS5_Pos) /*!< SYS_T::GPJ_MFOS: MFOS5 Mask */ 3896 3897 #define SYS_GPJ_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPJ_MFOS: MFOS6 Position */ 3898 #define SYS_GPJ_MFOS_MFOS6_Msk (0x1ul << SYS_GPJ_MFOS_MFOS6_Pos) /*!< SYS_T::GPJ_MFOS: MFOS6 Mask */ 3899 3900 #define SYS_GPJ_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPJ_MFOS: MFOS7 Position */ 3901 #define SYS_GPJ_MFOS_MFOS7_Msk (0x1ul << SYS_GPJ_MFOS_MFOS7_Pos) /*!< SYS_T::GPJ_MFOS: MFOS7 Mask */ 3902 3903 #define SYS_GPJ_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPJ_MFOS: MFOS8 Position */ 3904 #define SYS_GPJ_MFOS_MFOS8_Msk (0x1ul << SYS_GPJ_MFOS_MFOS8_Pos) /*!< SYS_T::GPJ_MFOS: MFOS8 Mask */ 3905 3906 #define SYS_GPJ_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPJ_MFOS: MFOS9 Position */ 3907 #define SYS_GPJ_MFOS_MFOS9_Msk (0x1ul << SYS_GPJ_MFOS_MFOS9_Pos) /*!< SYS_T::GPJ_MFOS: MFOS9 Mask */ 3908 3909 #define SYS_GPJ_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPJ_MFOS: MFOS10 Position */ 3910 #define SYS_GPJ_MFOS_MFOS10_Msk (0x1ul << SYS_GPJ_MFOS_MFOS10_Pos) /*!< SYS_T::GPJ_MFOS: MFOS10 Mask */ 3911 3912 #define SYS_GPJ_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPJ_MFOS: MFOS11 Position */ 3913 #define SYS_GPJ_MFOS_MFOS11_Msk (0x1ul << SYS_GPJ_MFOS_MFOS11_Pos) /*!< SYS_T::GPJ_MFOS: MFOS11 Mask */ 3914 3915 #define SYS_GPJ_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPJ_MFOS: MFOS12 Position */ 3916 #define SYS_GPJ_MFOS_MFOS12_Msk (0x1ul << SYS_GPJ_MFOS_MFOS12_Pos) /*!< SYS_T::GPJ_MFOS: MFOS12 Mask */ 3917 3918 #define SYS_GPJ_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPJ_MFOS: MFOS13 Position */ 3919 #define SYS_GPJ_MFOS_MFOS13_Msk (0x1ul << SYS_GPJ_MFOS_MFOS13_Pos) /*!< SYS_T::GPJ_MFOS: MFOS13 Mask */ 3920 3921 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ 3922 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ 3923 3924 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ 3925 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ 3926 3927 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ 3928 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ 3929 3930 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ 3931 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ 3932 3933 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ 3934 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ 3935 3936 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ 3937 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ 3938 3939 #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ 3940 #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ 3941 3942 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ 3943 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ 3944 3945 #define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ 3946 #define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ 3947 3948 #define SYS_SRAM_BISTCTL_EMAC0BIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMAC0BIST Position*/ 3949 #define SYS_SRAM_BISTCTL_EMAC0BIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMAC0BIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMAC0BIST Mask */ 3950 3951 #define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ 3952 #define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ 3953 3954 #define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ 3955 #define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ 3956 3957 #define SYS_SRAM_BISTCTL_SRBIST2_Pos (10) /*!< SYS_T::SRAM_BISTCTL: SRBIST2 Position */ 3958 #define SYS_SRAM_BISTCTL_SRBIST2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST2 Mask */ 3959 3960 #define SYS_SRAM_BISTCTL_KSBIST_Pos (11) /*!< SYS_T::SRAM_BISTCTL: KSBIST Position */ 3961 #define SYS_SRAM_BISTCTL_KSBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_KSBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: KSBIST Mask */ 3962 3963 #define SYS_SRAM_BISTCTL_CCAPBIST_Pos (12) /*!< SYS_T::SRAM_BISTCTL: CCAPBIST Position */ 3964 #define SYS_SRAM_BISTCTL_CCAPBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CCAPBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CCAPBIST Mask */ 3965 3966 #define SYS_SRAM_BISTCTL_RSABIST_Pos (13) /*!< SYS_T::SRAM_BISTCTL: RSABIST Position */ 3967 #define SYS_SRAM_BISTCTL_RSABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_RSABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: RSABIST Mask */ 3968 3969 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ 3970 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ 3971 3972 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ 3973 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ 3974 3975 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ 3976 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ 3977 3978 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ 3979 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ 3980 3981 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ 3982 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ 3983 3984 #define SYS_SRAM_BISTSTS_SPIMBEF_Pos (5) /*!< SYS_T::SRAM_BISTSTS: SPIMBEF Position */ 3985 #define SYS_SRAM_BISTSTS_SPIMBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_SPIMBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: SPIMBEF Mask */ 3986 3987 #define SYS_SRAM_BISTSTS_EMAC0BEF_Pos (6) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEF Position */ 3988 #define SYS_SRAM_BISTSTS_EMAC0BEF_Msk (0x1ul << SYS_SRAM_BISTSTS_EMAC0BEF_Pos) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEF Mask */ 3989 3990 #define SYS_SRAM_BISTSTS_HSUSBDBEF_Pos (8) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEF Position*/ 3991 #define SYS_SRAM_BISTSTS_HSUSBDBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBDBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEF Mask */ 3992 3993 #define SYS_SRAM_BISTSTS_HSUSBHBEF_Pos (9) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEF Position*/ 3994 #define SYS_SRAM_BISTSTS_HSUSBHBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBHBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEF Mask */ 3995 3996 #define SYS_SRAM_BISTSTS_SRBISTEF2_Pos (10) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF2 Position*/ 3997 #define SYS_SRAM_BISTSTS_SRBISTEF2_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF2_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF2 Mask */ 3998 3999 #define SYS_SRAM_BISTSTS_KSBISTEF_Pos (11) /*!< SYS_T::SRAM_BISTSTS: KSBISTEF Position */ 4000 #define SYS_SRAM_BISTSTS_KSBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_KSBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: KSBISTEF Mask */ 4001 4002 #define SYS_SRAM_BISTSTS_CCAPBISTEF_Pos (12) /*!< SYS_T::SRAM_BISTSTS: CCAPBISTEF Position*/ 4003 #define SYS_SRAM_BISTSTS_CCAPBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CCAPBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CCAPBISTEF Mask */ 4004 4005 #define SYS_SRAM_BISTSTS_RSABISTE_Pos (13) /*!< SYS_T::SRAM_BISTSTS: RSABISTE Position */ 4006 #define SYS_SRAM_BISTSTS_RSABISTE_Msk (0x1ul << SYS_SRAM_BISTSTS_RSABISTE_Pos) /*!< SYS_T::SRAM_BISTSTS: RSABISTE Mask */ 4007 4008 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ 4009 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ 4010 4011 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ 4012 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ 4013 4014 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ 4015 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ 4016 4017 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ 4018 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ 4019 4020 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ 4021 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ 4022 4023 #define SYS_SRAM_BISTSTS_SPIMBEND_Pos (21) /*!< SYS_T::SRAM_BISTSTS: SPIMBEND Position */ 4024 #define SYS_SRAM_BISTSTS_SPIMBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_SPIMBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: SPIMBEND Mask */ 4025 4026 #define SYS_SRAM_BISTSTS_EMAC0BEND_Pos (22) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEND Position*/ 4027 #define SYS_SRAM_BISTSTS_EMAC0BEND_Msk (0x1ul << SYS_SRAM_BISTSTS_EMAC0BEND_Pos) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEND Mask */ 4028 4029 #define SYS_SRAM_BISTSTS_HSUSBDBEND_Pos (24) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEND Position*/ 4030 #define SYS_SRAM_BISTSTS_HSUSBDBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBDBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEND Mask */ 4031 4032 #define SYS_SRAM_BISTSTS_HSUSBHBEND_Pos (25) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEND Position*/ 4033 #define SYS_SRAM_BISTSTS_HSUSBHBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBHBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEND Mask */ 4034 4035 #define SYS_SRAM_BISTSTS_SRBEND2_Pos (26) /*!< SYS_T::SRAM_BISTSTS: SRBEND2 Position */ 4036 #define SYS_SRAM_BISTSTS_SRBEND2_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND2_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND2 Mask */ 4037 4038 #define SYS_SRAM_BISTSTS_KSBEND_Pos (27) /*!< SYS_T::SRAM_BISTSTS: KSBEND Position */ 4039 #define SYS_SRAM_BISTSTS_KSBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_KSBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: KSBEND Mask */ 4040 4041 #define SYS_SRAM_BISTSTS_CCAPBEND_Pos (28) /*!< SYS_T::SRAM_BISTSTS: CCAPBEND Position */ 4042 #define SYS_SRAM_BISTSTS_CCAPBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CCAPBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CCAPBEND Mask */ 4043 4044 #define SYS_SRAM_BISTSTS_RSABEND_Pos (29) /*!< SYS_T::SRAM_BISTSTS: RSABEND Position */ 4045 #define SYS_SRAM_BISTSTS_RSABEND_Msk (0x1ul << SYS_SRAM_BISTSTS_RSABEND_Pos) /*!< SYS_T::SRAM_BISTSTS: RSABEND Mask */ 4046 4047 #define SYS_HIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTCTL: FREQSEL Position */ 4048 #define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTCTL: FREQSEL Mask */ 4049 4050 #define SYS_HIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTCTL: LOOPSEL Position */ 4051 #define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTCTL: LOOPSEL Mask */ 4052 4053 #define SYS_HIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTCTL: RETRYCNT Position */ 4054 #define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTCTL: RETRYCNT Mask */ 4055 4056 #define SYS_HIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTCTL: CESTOPEN Position */ 4057 #define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */ 4058 4059 #define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */ 4060 #define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */ 4061 4062 #define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */ 4063 #define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */ 4064 4065 #define SYS_HIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTCTL: BOUNDARY Position */ 4066 #define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTCTL: BOUNDARY Mask */ 4067 4068 #define SYS_HIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::HIRCTIEN: TFAILIEN Position */ 4069 #define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::HIRCTIEN: TFAILIEN Mask */ 4070 4071 #define SYS_HIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTIEN: CLKEIEN Position */ 4072 #define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTIEN: CLKEIEN Mask */ 4073 4074 #define SYS_HIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTISTS: FREQLOCK Position */ 4075 #define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTISTS: FREQLOCK Mask */ 4076 4077 #define SYS_HIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTISTS: TFAILIF Position */ 4078 #define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) /*!< SYS_T::HIRCTISTS: TFAILIF Mask */ 4079 4080 #define SYS_HIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::HIRCTISTS: CLKERRIF Position */ 4081 #define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::HIRCTISTS: CLKERRIF Mask */ 4082 4083 #define SYS_HIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTISTS: OVBDIF Position */ 4084 #define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) /*!< SYS_T::HIRCTISTS: OVBDIF Mask */ 4085 4086 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ 4087 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ 4088 4089 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ 4090 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ 4091 4092 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ 4093 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ 4094 4095 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ 4096 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ 4097 4098 #define SYS_IRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::IRCTCTL: BOUNDEN Position */ 4099 #define SYS_IRCTCTL_BOUNDEN_Msk (0x1ul << SYS_IRCTCTL_BOUNDEN_Pos) /*!< SYS_T::IRCTCTL: BOUNDEN Mask */ 4100 4101 #define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ 4102 #define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ 4103 4104 #define SYS_IRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::IRCTCTL: BOUNDARY Position */ 4105 #define SYS_IRCTCTL_BOUNDARY_Msk (0x1ful << SYS_IRCTCTL_BOUNDARY_Pos) /*!< SYS_T::IRCTCTL: BOUNDARY Mask */ 4106 4107 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ 4108 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ 4109 4110 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ 4111 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ 4112 4113 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ 4114 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ 4115 4116 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ 4117 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ 4118 4119 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ 4120 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ 4121 4122 #define SYS_IRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::IRCTISTS: OVBDIF Position */ 4123 #define SYS_IRCTISTS_OVBDIF_Msk (0x1ul << SYS_IRCTISTS_OVBDIF_Pos) /*!< SYS_T::IRCTISTS: OVBDIF Mask */ 4124 4125 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ 4126 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ 4127 4128 #define SYS_PORDISAN_POROFFAN_Pos (0) /*!< SYS_T::PORDISAN: POROFFAN Position */ 4129 #define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) /*!< SYS_T::PORDISAN: POROFFAN Mask */ 4130 4131 #define SYS_CSERVER_VERSION_Pos (0) /*!< SYS_T::CSERVER: VERSION Position */ 4132 #define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) /*!< SYS_T::CSERVER: VERSION Mask */ 4133 4134 #define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ 4135 #define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ 4136 4137 #define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ 4138 #define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ 4139 4140 #define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ 4141 #define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ 4142 4143 #define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ 4144 #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ 4145 4146 #define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ 4147 #define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ 4148 4149 #define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ 4150 #define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ 4151 4152 #define SYS_GPA_MFP0_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFP0: PA0MFP Position */ 4153 #define SYS_GPA_MFP0_PA0MFP_Msk (0x1ful << SYS_GPA_MFP0_PA0MFP_Pos) /*!< SYS_T::GPA_MFP0: PA0MFP Mask */ 4154 4155 #define SYS_GPA_MFP0_PA1MFP_Pos (8) /*!< SYS_T::GPA_MFP0: PA1MFP Position */ 4156 #define SYS_GPA_MFP0_PA1MFP_Msk (0x1ful << SYS_GPA_MFP0_PA1MFP_Pos) /*!< SYS_T::GPA_MFP0: PA1MFP Mask */ 4157 4158 #define SYS_GPA_MFP0_PA2MFP_Pos (16) /*!< SYS_T::GPA_MFP0: PA2MFP Position */ 4159 #define SYS_GPA_MFP0_PA2MFP_Msk (0x1ful << SYS_GPA_MFP0_PA2MFP_Pos) /*!< SYS_T::GPA_MFP0: PA2MFP Mask */ 4160 4161 #define SYS_GPA_MFP0_PA3MFP_Pos (24) /*!< SYS_T::GPA_MFP0: PA3MFP Position */ 4162 #define SYS_GPA_MFP0_PA3MFP_Msk (0x1ful << SYS_GPA_MFP0_PA3MFP_Pos) /*!< SYS_T::GPA_MFP0: PA3MFP Mask */ 4163 4164 #define SYS_GPA_MFP1_PA4MFP_Pos (0) /*!< SYS_T::GPA_MFP1: PA4MFP Position */ 4165 #define SYS_GPA_MFP1_PA4MFP_Msk (0x1ful << SYS_GPA_MFP1_PA4MFP_Pos) /*!< SYS_T::GPA_MFP1: PA4MFP Mask */ 4166 4167 #define SYS_GPA_MFP1_PA5MFP_Pos (8) /*!< SYS_T::GPA_MFP1: PA5MFP Position */ 4168 #define SYS_GPA_MFP1_PA5MFP_Msk (0x1ful << SYS_GPA_MFP1_PA5MFP_Pos) /*!< SYS_T::GPA_MFP1: PA5MFP Mask */ 4169 4170 #define SYS_GPA_MFP1_PA6MFP_Pos (16) /*!< SYS_T::GPA_MFP1: PA6MFP Position */ 4171 #define SYS_GPA_MFP1_PA6MFP_Msk (0x1ful << SYS_GPA_MFP1_PA6MFP_Pos) /*!< SYS_T::GPA_MFP1: PA6MFP Mask */ 4172 4173 #define SYS_GPA_MFP1_PA7MFP_Pos (24) /*!< SYS_T::GPA_MFP1: PA7MFP Position */ 4174 #define SYS_GPA_MFP1_PA7MFP_Msk (0x1ful << SYS_GPA_MFP1_PA7MFP_Pos) /*!< SYS_T::GPA_MFP1: PA7MFP Mask */ 4175 4176 #define SYS_GPA_MFP2_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFP2: PA8MFP Position */ 4177 #define SYS_GPA_MFP2_PA8MFP_Msk (0x1ful << SYS_GPA_MFP2_PA8MFP_Pos) /*!< SYS_T::GPA_MFP2: PA8MFP Mask */ 4178 4179 #define SYS_GPA_MFP2_PA9MFP_Pos (8) /*!< SYS_T::GPA_MFP2: PA9MFP Position */ 4180 #define SYS_GPA_MFP2_PA9MFP_Msk (0x1ful << SYS_GPA_MFP2_PA9MFP_Pos) /*!< SYS_T::GPA_MFP2: PA9MFP Mask */ 4181 4182 #define SYS_GPA_MFP2_PA10MFP_Pos (16) /*!< SYS_T::GPA_MFP2: PA10MFP Position */ 4183 #define SYS_GPA_MFP2_PA10MFP_Msk (0x1ful << SYS_GPA_MFP2_PA10MFP_Pos) /*!< SYS_T::GPA_MFP2: PA10MFP Mask */ 4184 4185 #define SYS_GPA_MFP2_PA11MFP_Pos (24) /*!< SYS_T::GPA_MFP2: PA11MFP Position */ 4186 #define SYS_GPA_MFP2_PA11MFP_Msk (0x1ful << SYS_GPA_MFP2_PA11MFP_Pos) /*!< SYS_T::GPA_MFP2: PA11MFP Mask */ 4187 4188 #define SYS_GPA_MFP3_PA12MFP_Pos (0) /*!< SYS_T::GPA_MFP3: PA12MFP Position */ 4189 #define SYS_GPA_MFP3_PA12MFP_Msk (0x1ful << SYS_GPA_MFP3_PA12MFP_Pos) /*!< SYS_T::GPA_MFP3: PA12MFP Mask */ 4190 4191 #define SYS_GPA_MFP3_PA13MFP_Pos (8) /*!< SYS_T::GPA_MFP3: PA13MFP Position */ 4192 #define SYS_GPA_MFP3_PA13MFP_Msk (0x1ful << SYS_GPA_MFP3_PA13MFP_Pos) /*!< SYS_T::GPA_MFP3: PA13MFP Mask */ 4193 4194 #define SYS_GPA_MFP3_PA14MFP_Pos (16) /*!< SYS_T::GPA_MFP3: PA14MFP Position */ 4195 #define SYS_GPA_MFP3_PA14MFP_Msk (0x1ful << SYS_GPA_MFP3_PA14MFP_Pos) /*!< SYS_T::GPA_MFP3: PA14MFP Mask */ 4196 4197 #define SYS_GPA_MFP3_PA15MFP_Pos (24) /*!< SYS_T::GPA_MFP3: PA15MFP Position */ 4198 #define SYS_GPA_MFP3_PA15MFP_Msk (0x1ful << SYS_GPA_MFP3_PA15MFP_Pos) /*!< SYS_T::GPA_MFP3: PA15MFP Mask */ 4199 4200 #define SYS_GPB_MFP0_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFP0: PB0MFP Position */ 4201 #define SYS_GPB_MFP0_PB0MFP_Msk (0x1ful << SYS_GPB_MFP0_PB0MFP_Pos) /*!< SYS_T::GPB_MFP0: PB0MFP Mask */ 4202 4203 #define SYS_GPB_MFP0_PB1MFP_Pos (8) /*!< SYS_T::GPB_MFP0: PB1MFP Position */ 4204 #define SYS_GPB_MFP0_PB1MFP_Msk (0x1ful << SYS_GPB_MFP0_PB1MFP_Pos) /*!< SYS_T::GPB_MFP0: PB1MFP Mask */ 4205 4206 #define SYS_GPB_MFP0_PB2MFP_Pos (16) /*!< SYS_T::GPB_MFP0: PB2MFP Position */ 4207 #define SYS_GPB_MFP0_PB2MFP_Msk (0x1ful << SYS_GPB_MFP0_PB2MFP_Pos) /*!< SYS_T::GPB_MFP0: PB2MFP Mask */ 4208 4209 #define SYS_GPB_MFP0_PB3MFP_Pos (24) /*!< SYS_T::GPB_MFP0: PB3MFP Position */ 4210 #define SYS_GPB_MFP0_PB3MFP_Msk (0x1ful << SYS_GPB_MFP0_PB3MFP_Pos) /*!< SYS_T::GPB_MFP0: PB3MFP Mask */ 4211 4212 #define SYS_GPB_MFP1_PB4MFP_Pos (0) /*!< SYS_T::GPB_MFP1: PB4MFP Position */ 4213 #define SYS_GPB_MFP1_PB4MFP_Msk (0x1ful << SYS_GPB_MFP1_PB4MFP_Pos) /*!< SYS_T::GPB_MFP1: PB4MFP Mask */ 4214 4215 #define SYS_GPB_MFP1_PB5MFP_Pos (8) /*!< SYS_T::GPB_MFP1: PB5MFP Position */ 4216 #define SYS_GPB_MFP1_PB5MFP_Msk (0x1ful << SYS_GPB_MFP1_PB5MFP_Pos) /*!< SYS_T::GPB_MFP1: PB5MFP Mask */ 4217 4218 #define SYS_GPB_MFP1_PB6MFP_Pos (16) /*!< SYS_T::GPB_MFP1: PB6MFP Position */ 4219 #define SYS_GPB_MFP1_PB6MFP_Msk (0x1ful << SYS_GPB_MFP1_PB6MFP_Pos) /*!< SYS_T::GPB_MFP1: PB6MFP Mask */ 4220 4221 #define SYS_GPB_MFP1_PB7MFP_Pos (24) /*!< SYS_T::GPB_MFP1: PB7MFP Position */ 4222 #define SYS_GPB_MFP1_PB7MFP_Msk (0x1ful << SYS_GPB_MFP1_PB7MFP_Pos) /*!< SYS_T::GPB_MFP1: PB7MFP Mask */ 4223 4224 #define SYS_GPB_MFP2_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFP2: PB8MFP Position */ 4225 #define SYS_GPB_MFP2_PB8MFP_Msk (0x1ful << SYS_GPB_MFP2_PB8MFP_Pos) /*!< SYS_T::GPB_MFP2: PB8MFP Mask */ 4226 4227 #define SYS_GPB_MFP2_PB9MFP_Pos (8) /*!< SYS_T::GPB_MFP2: PB9MFP Position */ 4228 #define SYS_GPB_MFP2_PB9MFP_Msk (0x1ful << SYS_GPB_MFP2_PB9MFP_Pos) /*!< SYS_T::GPB_MFP2: PB9MFP Mask */ 4229 4230 #define SYS_GPB_MFP2_PB10MFP_Pos (16) /*!< SYS_T::GPB_MFP2: PB10MFP Position */ 4231 #define SYS_GPB_MFP2_PB10MFP_Msk (0x1ful << SYS_GPB_MFP2_PB10MFP_Pos) /*!< SYS_T::GPB_MFP2: PB10MFP Mask */ 4232 4233 #define SYS_GPB_MFP2_PB11MFP_Pos (24) /*!< SYS_T::GPB_MFP2: PB11MFP Position */ 4234 #define SYS_GPB_MFP2_PB11MFP_Msk (0x1ful << SYS_GPB_MFP2_PB11MFP_Pos) /*!< SYS_T::GPB_MFP2: PB11MFP Mask */ 4235 4236 #define SYS_GPB_MFP3_PB12MFP_Pos (0) /*!< SYS_T::GPB_MFP3: PB12MFP Position */ 4237 #define SYS_GPB_MFP3_PB12MFP_Msk (0x1ful << SYS_GPB_MFP3_PB12MFP_Pos) /*!< SYS_T::GPB_MFP3: PB12MFP Mask */ 4238 4239 #define SYS_GPB_MFP3_PB13MFP_Pos (8) /*!< SYS_T::GPB_MFP3: PB13MFP Position */ 4240 #define SYS_GPB_MFP3_PB13MFP_Msk (0x1ful << SYS_GPB_MFP3_PB13MFP_Pos) /*!< SYS_T::GPB_MFP3: PB13MFP Mask */ 4241 4242 #define SYS_GPB_MFP3_PB14MFP_Pos (16) /*!< SYS_T::GPB_MFP3: PB14MFP Position */ 4243 #define SYS_GPB_MFP3_PB14MFP_Msk (0x1ful << SYS_GPB_MFP3_PB14MFP_Pos) /*!< SYS_T::GPB_MFP3: PB14MFP Mask */ 4244 4245 #define SYS_GPB_MFP3_PB15MFP_Pos (24) /*!< SYS_T::GPB_MFP3: PB15MFP Position */ 4246 #define SYS_GPB_MFP3_PB15MFP_Msk (0x1ful << SYS_GPB_MFP3_PB15MFP_Pos) /*!< SYS_T::GPB_MFP3: PB15MFP Mask */ 4247 4248 #define SYS_GPC_MFP0_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFP0: PC0MFP Position */ 4249 #define SYS_GPC_MFP0_PC0MFP_Msk (0x1ful << SYS_GPC_MFP0_PC0MFP_Pos) /*!< SYS_T::GPC_MFP0: PC0MFP Mask */ 4250 4251 #define SYS_GPC_MFP0_PC1MFP_Pos (8) /*!< SYS_T::GPC_MFP0: PC1MFP Position */ 4252 #define SYS_GPC_MFP0_PC1MFP_Msk (0x1ful << SYS_GPC_MFP0_PC1MFP_Pos) /*!< SYS_T::GPC_MFP0: PC1MFP Mask */ 4253 4254 #define SYS_GPC_MFP0_PC2MFP_Pos (16) /*!< SYS_T::GPC_MFP0: PC2MFP Position */ 4255 #define SYS_GPC_MFP0_PC2MFP_Msk (0x1ful << SYS_GPC_MFP0_PC2MFP_Pos) /*!< SYS_T::GPC_MFP0: PC2MFP Mask */ 4256 4257 #define SYS_GPC_MFP0_PC3MFP_Pos (24) /*!< SYS_T::GPC_MFP0: PC3MFP Position */ 4258 #define SYS_GPC_MFP0_PC3MFP_Msk (0x1ful << SYS_GPC_MFP0_PC3MFP_Pos) /*!< SYS_T::GPC_MFP0: PC3MFP Mask */ 4259 4260 #define SYS_GPC_MFP1_PC4MFP_Pos (0) /*!< SYS_T::GPC_MFP1: PC4MFP Position */ 4261 #define SYS_GPC_MFP1_PC4MFP_Msk (0x1ful << SYS_GPC_MFP1_PC4MFP_Pos) /*!< SYS_T::GPC_MFP1: PC4MFP Mask */ 4262 4263 #define SYS_GPC_MFP1_PC5MFP_Pos (8) /*!< SYS_T::GPC_MFP1: PC5MFP Position */ 4264 #define SYS_GPC_MFP1_PC5MFP_Msk (0x1ful << SYS_GPC_MFP1_PC5MFP_Pos) /*!< SYS_T::GPC_MFP1: PC5MFP Mask */ 4265 4266 #define SYS_GPC_MFP1_PC6MFP_Pos (16) /*!< SYS_T::GPC_MFP1: PC6MFP Position */ 4267 #define SYS_GPC_MFP1_PC6MFP_Msk (0x1ful << SYS_GPC_MFP1_PC6MFP_Pos) /*!< SYS_T::GPC_MFP1: PC6MFP Mask */ 4268 4269 #define SYS_GPC_MFP1_PC7MFP_Pos (24) /*!< SYS_T::GPC_MFP1: PC7MFP Position */ 4270 #define SYS_GPC_MFP1_PC7MFP_Msk (0x1ful << SYS_GPC_MFP1_PC7MFP_Pos) /*!< SYS_T::GPC_MFP1: PC7MFP Mask */ 4271 4272 #define SYS_GPC_MFP2_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFP2: PC8MFP Position */ 4273 #define SYS_GPC_MFP2_PC8MFP_Msk (0x1ful << SYS_GPC_MFP2_PC8MFP_Pos) /*!< SYS_T::GPC_MFP2: PC8MFP Mask */ 4274 4275 #define SYS_GPC_MFP2_PC9MFP_Pos (8) /*!< SYS_T::GPC_MFP2: PC9MFP Position */ 4276 #define SYS_GPC_MFP2_PC9MFP_Msk (0x1ful << SYS_GPC_MFP2_PC9MFP_Pos) /*!< SYS_T::GPC_MFP2: PC9MFP Mask */ 4277 4278 #define SYS_GPC_MFP2_PC10MFP_Pos (16) /*!< SYS_T::GPC_MFP2: PC10MFP Position */ 4279 #define SYS_GPC_MFP2_PC10MFP_Msk (0x1ful << SYS_GPC_MFP2_PC10MFP_Pos) /*!< SYS_T::GPC_MFP2: PC10MFP Mask */ 4280 4281 #define SYS_GPC_MFP2_PC11MFP_Pos (24) /*!< SYS_T::GPC_MFP2: PC11MFP Position */ 4282 #define SYS_GPC_MFP2_PC11MFP_Msk (0x1ful << SYS_GPC_MFP2_PC11MFP_Pos) /*!< SYS_T::GPC_MFP2: PC11MFP Mask */ 4283 4284 #define SYS_GPC_MFP3_PC12MFP_Pos (0) /*!< SYS_T::GPC_MFP3: PC12MFP Position */ 4285 #define SYS_GPC_MFP3_PC12MFP_Msk (0x1ful << SYS_GPC_MFP3_PC12MFP_Pos) /*!< SYS_T::GPC_MFP3: PC12MFP Mask */ 4286 4287 #define SYS_GPC_MFP3_PC13MFP_Pos (8) /*!< SYS_T::GPC_MFP3: PC13MFP Position */ 4288 #define SYS_GPC_MFP3_PC13MFP_Msk (0x1ful << SYS_GPC_MFP3_PC13MFP_Pos) /*!< SYS_T::GPC_MFP3: PC13MFP Mask */ 4289 4290 #define SYS_GPC_MFP3_PC14MFP_Pos (16) /*!< SYS_T::GPC_MFP3: PC14MFP Position */ 4291 #define SYS_GPC_MFP3_PC14MFP_Msk (0x1ful << SYS_GPC_MFP3_PC14MFP_Pos) /*!< SYS_T::GPC_MFP3: PC14MFP Mask */ 4292 4293 #define SYS_GPD_MFP0_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFP0: PD0MFP Position */ 4294 #define SYS_GPD_MFP0_PD0MFP_Msk (0x1ful << SYS_GPD_MFP0_PD0MFP_Pos) /*!< SYS_T::GPD_MFP0: PD0MFP Mask */ 4295 4296 #define SYS_GPD_MFP0_PD1MFP_Pos (8) /*!< SYS_T::GPD_MFP0: PD1MFP Position */ 4297 #define SYS_GPD_MFP0_PD1MFP_Msk (0x1ful << SYS_GPD_MFP0_PD1MFP_Pos) /*!< SYS_T::GPD_MFP0: PD1MFP Mask */ 4298 4299 #define SYS_GPD_MFP0_PD2MFP_Pos (16) /*!< SYS_T::GPD_MFP0: PD2MFP Position */ 4300 #define SYS_GPD_MFP0_PD2MFP_Msk (0x1ful << SYS_GPD_MFP0_PD2MFP_Pos) /*!< SYS_T::GPD_MFP0: PD2MFP Mask */ 4301 4302 #define SYS_GPD_MFP0_PD3MFP_Pos (24) /*!< SYS_T::GPD_MFP0: PD3MFP Position */ 4303 #define SYS_GPD_MFP0_PD3MFP_Msk (0x1ful << SYS_GPD_MFP0_PD3MFP_Pos) /*!< SYS_T::GPD_MFP0: PD3MFP Mask */ 4304 4305 #define SYS_GPD_MFP1_PD4MFP_Pos (0) /*!< SYS_T::GPD_MFP1: PD4MFP Position */ 4306 #define SYS_GPD_MFP1_PD4MFP_Msk (0x1ful << SYS_GPD_MFP1_PD4MFP_Pos) /*!< SYS_T::GPD_MFP1: PD4MFP Mask */ 4307 4308 #define SYS_GPD_MFP1_PD5MFP_Pos (8) /*!< SYS_T::GPD_MFP1: PD5MFP Position */ 4309 #define SYS_GPD_MFP1_PD5MFP_Msk (0x1ful << SYS_GPD_MFP1_PD5MFP_Pos) /*!< SYS_T::GPD_MFP1: PD5MFP Mask */ 4310 4311 #define SYS_GPD_MFP1_PD6MFP_Pos (16) /*!< SYS_T::GPD_MFP1: PD6MFP Position */ 4312 #define SYS_GPD_MFP1_PD6MFP_Msk (0x1ful << SYS_GPD_MFP1_PD6MFP_Pos) /*!< SYS_T::GPD_MFP1: PD6MFP Mask */ 4313 4314 #define SYS_GPD_MFP1_PD7MFP_Pos (24) /*!< SYS_T::GPD_MFP1: PD7MFP Position */ 4315 #define SYS_GPD_MFP1_PD7MFP_Msk (0x1ful << SYS_GPD_MFP1_PD7MFP_Pos) /*!< SYS_T::GPD_MFP1: PD7MFP Mask */ 4316 4317 #define SYS_GPD_MFP2_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFP2: PD8MFP Position */ 4318 #define SYS_GPD_MFP2_PD8MFP_Msk (0x1ful << SYS_GPD_MFP2_PD8MFP_Pos) /*!< SYS_T::GPD_MFP2: PD8MFP Mask */ 4319 4320 #define SYS_GPD_MFP2_PD9MFP_Pos (8) /*!< SYS_T::GPD_MFP2: PD9MFP Position */ 4321 #define SYS_GPD_MFP2_PD9MFP_Msk (0x1ful << SYS_GPD_MFP2_PD9MFP_Pos) /*!< SYS_T::GPD_MFP2: PD9MFP Mask */ 4322 4323 #define SYS_GPD_MFP2_PD10MFP_Pos (16) /*!< SYS_T::GPD_MFP2: PD10MFP Position */ 4324 #define SYS_GPD_MFP2_PD10MFP_Msk (0x1ful << SYS_GPD_MFP2_PD10MFP_Pos) /*!< SYS_T::GPD_MFP2: PD10MFP Mask */ 4325 4326 #define SYS_GPD_MFP2_PD11MFP_Pos (24) /*!< SYS_T::GPD_MFP2: PD11MFP Position */ 4327 #define SYS_GPD_MFP2_PD11MFP_Msk (0x1ful << SYS_GPD_MFP2_PD11MFP_Pos) /*!< SYS_T::GPD_MFP2: PD11MFP Mask */ 4328 4329 #define SYS_GPD_MFP3_PD12MFP_Pos (0) /*!< SYS_T::GPD_MFP3: PD12MFP Position */ 4330 #define SYS_GPD_MFP3_PD12MFP_Msk (0x1ful << SYS_GPD_MFP3_PD12MFP_Pos) /*!< SYS_T::GPD_MFP3: PD12MFP Mask */ 4331 4332 #define SYS_GPD_MFP3_PD13MFP_Pos (8) /*!< SYS_T::GPD_MFP3: PD13MFP Position */ 4333 #define SYS_GPD_MFP3_PD13MFP_Msk (0x1ful << SYS_GPD_MFP3_PD13MFP_Pos) /*!< SYS_T::GPD_MFP3: PD13MFP Mask */ 4334 4335 #define SYS_GPD_MFP3_PD14MFP_Pos (16) /*!< SYS_T::GPD_MFP3: PD14MFP Position */ 4336 #define SYS_GPD_MFP3_PD14MFP_Msk (0x1ful << SYS_GPD_MFP3_PD14MFP_Pos) /*!< SYS_T::GPD_MFP3: PD14MFP Mask */ 4337 4338 #define SYS_GPE_MFP0_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFP0: PE0MFP Position */ 4339 #define SYS_GPE_MFP0_PE0MFP_Msk (0x1ful << SYS_GPE_MFP0_PE0MFP_Pos) /*!< SYS_T::GPE_MFP0: PE0MFP Mask */ 4340 4341 #define SYS_GPE_MFP0_PE1MFP_Pos (8) /*!< SYS_T::GPE_MFP0: PE1MFP Position */ 4342 #define SYS_GPE_MFP0_PE1MFP_Msk (0x1ful << SYS_GPE_MFP0_PE1MFP_Pos) /*!< SYS_T::GPE_MFP0: PE1MFP Mask */ 4343 4344 #define SYS_GPE_MFP0_PE2MFP_Pos (16) /*!< SYS_T::GPE_MFP0: PE2MFP Position */ 4345 #define SYS_GPE_MFP0_PE2MFP_Msk (0x1ful << SYS_GPE_MFP0_PE2MFP_Pos) /*!< SYS_T::GPE_MFP0: PE2MFP Mask */ 4346 4347 #define SYS_GPE_MFP0_PE3MFP_Pos (24) /*!< SYS_T::GPE_MFP0: PE3MFP Position */ 4348 #define SYS_GPE_MFP0_PE3MFP_Msk (0x1ful << SYS_GPE_MFP0_PE3MFP_Pos) /*!< SYS_T::GPE_MFP0: PE3MFP Mask */ 4349 4350 #define SYS_GPE_MFP1_PE4MFP_Pos (0) /*!< SYS_T::GPE_MFP1: PE4MFP Position */ 4351 #define SYS_GPE_MFP1_PE4MFP_Msk (0x1ful << SYS_GPE_MFP1_PE4MFP_Pos) /*!< SYS_T::GPE_MFP1: PE4MFP Mask */ 4352 4353 #define SYS_GPE_MFP1_PE5MFP_Pos (8) /*!< SYS_T::GPE_MFP1: PE5MFP Position */ 4354 #define SYS_GPE_MFP1_PE5MFP_Msk (0x1ful << SYS_GPE_MFP1_PE5MFP_Pos) /*!< SYS_T::GPE_MFP1: PE5MFP Mask */ 4355 4356 #define SYS_GPE_MFP1_PE6MFP_Pos (16) /*!< SYS_T::GPE_MFP1: PE6MFP Position */ 4357 #define SYS_GPE_MFP1_PE6MFP_Msk (0x1ful << SYS_GPE_MFP1_PE6MFP_Pos) /*!< SYS_T::GPE_MFP1: PE6MFP Mask */ 4358 4359 #define SYS_GPE_MFP1_PE7MFP_Pos (24) /*!< SYS_T::GPE_MFP1: PE7MFP Position */ 4360 #define SYS_GPE_MFP1_PE7MFP_Msk (0x1ful << SYS_GPE_MFP1_PE7MFP_Pos) /*!< SYS_T::GPE_MFP1: PE7MFP Mask */ 4361 4362 #define SYS_GPE_MFP2_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFP2: PE8MFP Position */ 4363 #define SYS_GPE_MFP2_PE8MFP_Msk (0x1ful << SYS_GPE_MFP2_PE8MFP_Pos) /*!< SYS_T::GPE_MFP2: PE8MFP Mask */ 4364 4365 #define SYS_GPE_MFP2_PE9MFP_Pos (8) /*!< SYS_T::GPE_MFP2: PE9MFP Position */ 4366 #define SYS_GPE_MFP2_PE9MFP_Msk (0x1ful << SYS_GPE_MFP2_PE9MFP_Pos) /*!< SYS_T::GPE_MFP2: PE9MFP Mask */ 4367 4368 #define SYS_GPE_MFP2_PE10MFP_Pos (16) /*!< SYS_T::GPE_MFP2: PE10MFP Position */ 4369 #define SYS_GPE_MFP2_PE10MFP_Msk (0x1ful << SYS_GPE_MFP2_PE10MFP_Pos) /*!< SYS_T::GPE_MFP2: PE10MFP Mask */ 4370 4371 #define SYS_GPE_MFP2_PE11MFP_Pos (24) /*!< SYS_T::GPE_MFP2: PE11MFP Position */ 4372 #define SYS_GPE_MFP2_PE11MFP_Msk (0x1ful << SYS_GPE_MFP2_PE11MFP_Pos) /*!< SYS_T::GPE_MFP2: PE11MFP Mask */ 4373 4374 #define SYS_GPE_MFP3_PE12MFP_Pos (0) /*!< SYS_T::GPE_MFP3: PE12MFP Position */ 4375 #define SYS_GPE_MFP3_PE12MFP_Msk (0x1ful << SYS_GPE_MFP3_PE12MFP_Pos) /*!< SYS_T::GPE_MFP3: PE12MFP Mask */ 4376 4377 #define SYS_GPE_MFP3_PE13MFP_Pos (8) /*!< SYS_T::GPE_MFP3: PE13MFP Position */ 4378 #define SYS_GPE_MFP3_PE13MFP_Msk (0x1ful << SYS_GPE_MFP3_PE13MFP_Pos) /*!< SYS_T::GPE_MFP3: PE13MFP Mask */ 4379 4380 #define SYS_GPE_MFP3_PE14MFP_Pos (16) /*!< SYS_T::GPE_MFP3: PE14MFP Position */ 4381 #define SYS_GPE_MFP3_PE14MFP_Msk (0x1ful << SYS_GPE_MFP3_PE14MFP_Pos) /*!< SYS_T::GPE_MFP3: PE14MFP Mask */ 4382 4383 #define SYS_GPE_MFP3_PE15MFP_Pos (24) /*!< SYS_T::GPE_MFP3: PE15MFP Position */ 4384 #define SYS_GPE_MFP3_PE15MFP_Msk (0x1ful << SYS_GPE_MFP3_PE15MFP_Pos) /*!< SYS_T::GPE_MFP3: PE15MFP Mask */ 4385 4386 #define SYS_GPF_MFP0_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFP0: PF0MFP Position */ 4387 #define SYS_GPF_MFP0_PF0MFP_Msk (0x1ful << SYS_GPF_MFP0_PF0MFP_Pos) /*!< SYS_T::GPF_MFP0: PF0MFP Mask */ 4388 4389 #define SYS_GPF_MFP0_PF1MFP_Pos (8) /*!< SYS_T::GPF_MFP0: PF1MFP Position */ 4390 #define SYS_GPF_MFP0_PF1MFP_Msk (0x1ful << SYS_GPF_MFP0_PF1MFP_Pos) /*!< SYS_T::GPF_MFP0: PF1MFP Mask */ 4391 4392 #define SYS_GPF_MFP0_PF2MFP_Pos (16) /*!< SYS_T::GPF_MFP0: PF2MFP Position */ 4393 #define SYS_GPF_MFP0_PF2MFP_Msk (0x1ful << SYS_GPF_MFP0_PF2MFP_Pos) /*!< SYS_T::GPF_MFP0: PF2MFP Mask */ 4394 4395 #define SYS_GPF_MFP0_PF3MFP_Pos (24) /*!< SYS_T::GPF_MFP0: PF3MFP Position */ 4396 #define SYS_GPF_MFP0_PF3MFP_Msk (0x1ful << SYS_GPF_MFP0_PF3MFP_Pos) /*!< SYS_T::GPF_MFP0: PF3MFP Mask */ 4397 4398 #define SYS_GPF_MFP1_PF4MFP_Pos (0) /*!< SYS_T::GPF_MFP1: PF4MFP Position */ 4399 #define SYS_GPF_MFP1_PF4MFP_Msk (0x1ful << SYS_GPF_MFP1_PF4MFP_Pos) /*!< SYS_T::GPF_MFP1: PF4MFP Mask */ 4400 4401 #define SYS_GPF_MFP1_PF5MFP_Pos (8) /*!< SYS_T::GPF_MFP1: PF5MFP Position */ 4402 #define SYS_GPF_MFP1_PF5MFP_Msk (0x1ful << SYS_GPF_MFP1_PF5MFP_Pos) /*!< SYS_T::GPF_MFP1: PF5MFP Mask */ 4403 4404 #define SYS_GPF_MFP1_PF6MFP_Pos (16) /*!< SYS_T::GPF_MFP1: PF6MFP Position */ 4405 #define SYS_GPF_MFP1_PF6MFP_Msk (0x1ful << SYS_GPF_MFP1_PF6MFP_Pos) /*!< SYS_T::GPF_MFP1: PF6MFP Mask */ 4406 4407 #define SYS_GPF_MFP1_PF7MFP_Pos (24) /*!< SYS_T::GPF_MFP1: PF7MFP Position */ 4408 #define SYS_GPF_MFP1_PF7MFP_Msk (0x1ful << SYS_GPF_MFP1_PF7MFP_Pos) /*!< SYS_T::GPF_MFP1: PF7MFP Mask */ 4409 4410 #define SYS_GPF_MFP2_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFP2: PF8MFP Position */ 4411 #define SYS_GPF_MFP2_PF8MFP_Msk (0x1ful << SYS_GPF_MFP2_PF8MFP_Pos) /*!< SYS_T::GPF_MFP2: PF8MFP Mask */ 4412 4413 #define SYS_GPF_MFP2_PF9MFP_Pos (8) /*!< SYS_T::GPF_MFP2: PF9MFP Position */ 4414 #define SYS_GPF_MFP2_PF9MFP_Msk (0x1ful << SYS_GPF_MFP2_PF9MFP_Pos) /*!< SYS_T::GPF_MFP2: PF9MFP Mask */ 4415 4416 #define SYS_GPF_MFP2_PF10MFP_Pos (16) /*!< SYS_T::GPF_MFP2: PF10MFP Position */ 4417 #define SYS_GPF_MFP2_PF10MFP_Msk (0x1ful << SYS_GPF_MFP2_PF10MFP_Pos) /*!< SYS_T::GPF_MFP2: PF10MFP Mask */ 4418 4419 #define SYS_GPF_MFP2_PF11MFP_Pos (24) /*!< SYS_T::GPF_MFP2: PF11MFP Position */ 4420 #define SYS_GPF_MFP2_PF11MFP_Msk (0x1ful << SYS_GPF_MFP2_PF11MFP_Pos) /*!< SYS_T::GPF_MFP2: PF11MFP Mask */ 4421 4422 #define SYS_GPG_MFP0_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFP0: PG0MFP Position */ 4423 #define SYS_GPG_MFP0_PG0MFP_Msk (0x1ful << SYS_GPG_MFP0_PG0MFP_Pos) /*!< SYS_T::GPG_MFP0: PG0MFP Mask */ 4424 4425 #define SYS_GPG_MFP0_PG1MFP_Pos (8) /*!< SYS_T::GPG_MFP0: PG1MFP Position */ 4426 #define SYS_GPG_MFP0_PG1MFP_Msk (0x1ful << SYS_GPG_MFP0_PG1MFP_Pos) /*!< SYS_T::GPG_MFP0: PG1MFP Mask */ 4427 4428 #define SYS_GPG_MFP0_PG2MFP_Pos (16) /*!< SYS_T::GPG_MFP0: PG2MFP Position */ 4429 #define SYS_GPG_MFP0_PG2MFP_Msk (0x1ful << SYS_GPG_MFP0_PG2MFP_Pos) /*!< SYS_T::GPG_MFP0: PG2MFP Mask */ 4430 4431 #define SYS_GPG_MFP0_PG3MFP_Pos (24) /*!< SYS_T::GPG_MFP0: PG3MFP Position */ 4432 #define SYS_GPG_MFP0_PG3MFP_Msk (0x1ful << SYS_GPG_MFP0_PG3MFP_Pos) /*!< SYS_T::GPG_MFP0: PG3MFP Mask */ 4433 4434 #define SYS_GPG_MFP1_PG4MFP_Pos (0) /*!< SYS_T::GPG_MFP1: PG4MFP Position */ 4435 #define SYS_GPG_MFP1_PG4MFP_Msk (0x1ful << SYS_GPG_MFP1_PG4MFP_Pos) /*!< SYS_T::GPG_MFP1: PG4MFP Mask */ 4436 4437 #define SYS_GPG_MFP1_PG5MFP_Pos (8) /*!< SYS_T::GPG_MFP1: PG5MFP Position */ 4438 #define SYS_GPG_MFP1_PG5MFP_Msk (0x1ful << SYS_GPG_MFP1_PG5MFP_Pos) /*!< SYS_T::GPG_MFP1: PG5MFP Mask */ 4439 4440 #define SYS_GPG_MFP1_PG6MFP_Pos (16) /*!< SYS_T::GPG_MFP1: PG6MFP Position */ 4441 #define SYS_GPG_MFP1_PG6MFP_Msk (0x1ful << SYS_GPG_MFP1_PG6MFP_Pos) /*!< SYS_T::GPG_MFP1: PG6MFP Mask */ 4442 4443 #define SYS_GPG_MFP1_PG7MFP_Pos (24) /*!< SYS_T::GPG_MFP1: PG7MFP Position */ 4444 #define SYS_GPG_MFP1_PG7MFP_Msk (0x1ful << SYS_GPG_MFP1_PG7MFP_Pos) /*!< SYS_T::GPG_MFP1: PG7MFP Mask */ 4445 4446 #define SYS_GPG_MFP2_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFP2: PG8MFP Position */ 4447 #define SYS_GPG_MFP2_PG8MFP_Msk (0x1ful << SYS_GPG_MFP2_PG8MFP_Pos) /*!< SYS_T::GPG_MFP2: PG8MFP Mask */ 4448 4449 #define SYS_GPG_MFP2_PG9MFP_Pos (8) /*!< SYS_T::GPG_MFP2: PG9MFP Position */ 4450 #define SYS_GPG_MFP2_PG9MFP_Msk (0x1ful << SYS_GPG_MFP2_PG9MFP_Pos) /*!< SYS_T::GPG_MFP2: PG9MFP Mask */ 4451 4452 #define SYS_GPG_MFP2_PG10MFP_Pos (16) /*!< SYS_T::GPG_MFP2: PG10MFP Position */ 4453 #define SYS_GPG_MFP2_PG10MFP_Msk (0x1ful << SYS_GPG_MFP2_PG10MFP_Pos) /*!< SYS_T::GPG_MFP2: PG10MFP Mask */ 4454 4455 #define SYS_GPG_MFP2_PG11MFP_Pos (24) /*!< SYS_T::GPG_MFP2: PG11MFP Position */ 4456 #define SYS_GPG_MFP2_PG11MFP_Msk (0x1ful << SYS_GPG_MFP2_PG11MFP_Pos) /*!< SYS_T::GPG_MFP2: PG11MFP Mask */ 4457 4458 #define SYS_GPG_MFP3_PG12MFP_Pos (0) /*!< SYS_T::GPG_MFP3: PG12MFP Position */ 4459 #define SYS_GPG_MFP3_PG12MFP_Msk (0x1ful << SYS_GPG_MFP3_PG12MFP_Pos) /*!< SYS_T::GPG_MFP3: PG12MFP Mask */ 4460 4461 #define SYS_GPG_MFP3_PG13MFP_Pos (8) /*!< SYS_T::GPG_MFP3: PG13MFP Position */ 4462 #define SYS_GPG_MFP3_PG13MFP_Msk (0x1ful << SYS_GPG_MFP3_PG13MFP_Pos) /*!< SYS_T::GPG_MFP3: PG13MFP Mask */ 4463 4464 #define SYS_GPG_MFP3_PG14MFP_Pos (16) /*!< SYS_T::GPG_MFP3: PG14MFP Position */ 4465 #define SYS_GPG_MFP3_PG14MFP_Msk (0x1ful << SYS_GPG_MFP3_PG14MFP_Pos) /*!< SYS_T::GPG_MFP3: PG14MFP Mask */ 4466 4467 #define SYS_GPG_MFP3_PG15MFP_Pos (24) /*!< SYS_T::GPG_MFP3: PG15MFP Position */ 4468 #define SYS_GPG_MFP3_PG15MFP_Msk (0x1ful << SYS_GPG_MFP3_PG15MFP_Pos) /*!< SYS_T::GPG_MFP3: PG15MFP Mask */ 4469 4470 #define SYS_GPH_MFP0_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFP0: PH0MFP Position */ 4471 #define SYS_GPH_MFP0_PH0MFP_Msk (0x1ful << SYS_GPH_MFP0_PH0MFP_Pos) /*!< SYS_T::GPH_MFP0: PH0MFP Mask */ 4472 4473 #define SYS_GPH_MFP0_PH1MFP_Pos (8) /*!< SYS_T::GPH_MFP0: PH1MFP Position */ 4474 #define SYS_GPH_MFP0_PH1MFP_Msk (0x1ful << SYS_GPH_MFP0_PH1MFP_Pos) /*!< SYS_T::GPH_MFP0: PH1MFP Mask */ 4475 4476 #define SYS_GPH_MFP0_PH2MFP_Pos (16) /*!< SYS_T::GPH_MFP0: PH2MFP Position */ 4477 #define SYS_GPH_MFP0_PH2MFP_Msk (0x1ful << SYS_GPH_MFP0_PH2MFP_Pos) /*!< SYS_T::GPH_MFP0: PH2MFP Mask */ 4478 4479 #define SYS_GPH_MFP0_PH3MFP_Pos (24) /*!< SYS_T::GPH_MFP0: PH3MFP Position */ 4480 #define SYS_GPH_MFP0_PH3MFP_Msk (0x1ful << SYS_GPH_MFP0_PH3MFP_Pos) /*!< SYS_T::GPH_MFP0: PH3MFP Mask */ 4481 4482 #define SYS_GPH_MFP1_PH4MFP_Pos (0) /*!< SYS_T::GPH_MFP1: PH4MFP Position */ 4483 #define SYS_GPH_MFP1_PH4MFP_Msk (0x1ful << SYS_GPH_MFP1_PH4MFP_Pos) /*!< SYS_T::GPH_MFP1: PH4MFP Mask */ 4484 4485 #define SYS_GPH_MFP1_PH5MFP_Pos (8) /*!< SYS_T::GPH_MFP1: PH5MFP Position */ 4486 #define SYS_GPH_MFP1_PH5MFP_Msk (0x1ful << SYS_GPH_MFP1_PH5MFP_Pos) /*!< SYS_T::GPH_MFP1: PH5MFP Mask */ 4487 4488 #define SYS_GPH_MFP1_PH6MFP_Pos (16) /*!< SYS_T::GPH_MFP1: PH6MFP Position */ 4489 #define SYS_GPH_MFP1_PH6MFP_Msk (0x1ful << SYS_GPH_MFP1_PH6MFP_Pos) /*!< SYS_T::GPH_MFP1: PH6MFP Mask */ 4490 4491 #define SYS_GPH_MFP1_PH7MFP_Pos (24) /*!< SYS_T::GPH_MFP1: PH7MFP Position */ 4492 #define SYS_GPH_MFP1_PH7MFP_Msk (0x1ful << SYS_GPH_MFP1_PH7MFP_Pos) /*!< SYS_T::GPH_MFP1: PH7MFP Mask */ 4493 4494 #define SYS_GPH_MFP2_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFP2: PH8MFP Position */ 4495 #define SYS_GPH_MFP2_PH8MFP_Msk (0x1ful << SYS_GPH_MFP2_PH8MFP_Pos) /*!< SYS_T::GPH_MFP2: PH8MFP Mask */ 4496 4497 #define SYS_GPH_MFP2_PH9MFP_Pos (8) /*!< SYS_T::GPH_MFP2: PH9MFP Position */ 4498 #define SYS_GPH_MFP2_PH9MFP_Msk (0x1ful << SYS_GPH_MFP2_PH9MFP_Pos) /*!< SYS_T::GPH_MFP2: PH9MFP Mask */ 4499 4500 #define SYS_GPH_MFP2_PH10MFP_Pos (16) /*!< SYS_T::GPH_MFP2: PH10MFP Position */ 4501 #define SYS_GPH_MFP2_PH10MFP_Msk (0x1ful << SYS_GPH_MFP2_PH10MFP_Pos) /*!< SYS_T::GPH_MFP2: PH10MFP Mask */ 4502 4503 #define SYS_GPH_MFP2_PH11MFP_Pos (24) /*!< SYS_T::GPH_MFP2: PH11MFP Position */ 4504 #define SYS_GPH_MFP2_PH11MFP_Msk (0x1ful << SYS_GPH_MFP2_PH11MFP_Pos) /*!< SYS_T::GPH_MFP2: PH11MFP Mask */ 4505 4506 #define SYS_GPH_MFP3_PH12MFP_Pos (0) /*!< SYS_T::GPH_MFP3: PH12MFP Position */ 4507 #define SYS_GPH_MFP3_PH12MFP_Msk (0x1ful << SYS_GPH_MFP3_PH12MFP_Pos) /*!< SYS_T::GPH_MFP3: PH12MFP Mask */ 4508 4509 #define SYS_GPH_MFP3_PH13MFP_Pos (8) /*!< SYS_T::GPH_MFP3: PH13MFP Position */ 4510 #define SYS_GPH_MFP3_PH13MFP_Msk (0x1ful << SYS_GPH_MFP3_PH13MFP_Pos) /*!< SYS_T::GPH_MFP3: PH13MFP Mask */ 4511 4512 #define SYS_GPH_MFP3_PH14MFP_Pos (16) /*!< SYS_T::GPH_MFP3: PH14MFP Position */ 4513 #define SYS_GPH_MFP3_PH14MFP_Msk (0x1ful << SYS_GPH_MFP3_PH14MFP_Pos) /*!< SYS_T::GPH_MFP3: PH14MFP Mask */ 4514 4515 #define SYS_GPH_MFP3_PH15MFP_Pos (24) /*!< SYS_T::GPH_MFP3: PH15MFP Position */ 4516 #define SYS_GPH_MFP3_PH15MFP_Msk (0x1ful << SYS_GPH_MFP3_PH15MFP_Pos) /*!< SYS_T::GPH_MFP3: PH15MFP Mask */ 4517 4518 #define SYS_GPI_MFP1_PI6MFP_Pos (16) /*!< SYS_T::GPI_MFP1: PI6MFP Position */ 4519 #define SYS_GPI_MFP1_PI6MFP_Msk (0x1ful << SYS_GPI_MFP1_PI6MFP_Pos) /*!< SYS_T::GPI_MFP1: PI6MFP Mask */ 4520 4521 #define SYS_GPI_MFP1_PI7MFP_Pos (24) /*!< SYS_T::GPI_MFP1: PI7MFP Position */ 4522 #define SYS_GPI_MFP1_PI7MFP_Msk (0x1ful << SYS_GPI_MFP1_PI7MFP_Pos) /*!< SYS_T::GPI_MFP1: PI7MFP Mask */ 4523 4524 #define SYS_GPI_MFP2_PI8MFP_Pos (0) /*!< SYS_T::GPI_MFP2: PI8MFP Position */ 4525 #define SYS_GPI_MFP2_PI8MFP_Msk (0x1ful << SYS_GPI_MFP2_PI8MFP_Pos) /*!< SYS_T::GPI_MFP2: PI8MFP Mask */ 4526 4527 #define SYS_GPI_MFP2_PI9MFP_Pos (8) /*!< SYS_T::GPI_MFP2: PI9MFP Position */ 4528 #define SYS_GPI_MFP2_PI9MFP_Msk (0x1ful << SYS_GPI_MFP2_PI9MFP_Pos) /*!< SYS_T::GPI_MFP2: PI9MFP Mask */ 4529 4530 #define SYS_GPI_MFP2_PI10MFP_Pos (16) /*!< SYS_T::GPI_MFP2: PI10MFP Position */ 4531 #define SYS_GPI_MFP2_PI10MFP_Msk (0x1ful << SYS_GPI_MFP2_PI10MFP_Pos) /*!< SYS_T::GPI_MFP2: PI10MFP Mask */ 4532 4533 #define SYS_GPI_MFP2_PI11MFP_Pos (24) /*!< SYS_T::GPI_MFP2: PI11MFP Position */ 4534 #define SYS_GPI_MFP2_PI11MFP_Msk (0x1ful << SYS_GPI_MFP2_PI11MFP_Pos) /*!< SYS_T::GPI_MFP2: PI11MFP Mask */ 4535 4536 #define SYS_GPI_MFP3_PI12MFP_Pos (0) /*!< SYS_T::GPI_MFP3: PI12MFP Position */ 4537 #define SYS_GPI_MFP3_PI12MFP_Msk (0x1ful << SYS_GPI_MFP3_PI12MFP_Pos) /*!< SYS_T::GPI_MFP3: PI12MFP Mask */ 4538 4539 #define SYS_GPI_MFP3_PI13MFP_Pos (8) /*!< SYS_T::GPI_MFP3: PI13MFP Position */ 4540 #define SYS_GPI_MFP3_PI13MFP_Msk (0x1ful << SYS_GPI_MFP3_PI13MFP_Pos) /*!< SYS_T::GPI_MFP3: PI13MFP Mask */ 4541 4542 #define SYS_GPI_MFP3_PI14MFP_Pos (16) /*!< SYS_T::GPI_MFP3: PI14MFP Position */ 4543 #define SYS_GPI_MFP3_PI14MFP_Msk (0x1ful << SYS_GPI_MFP3_PI14MFP_Pos) /*!< SYS_T::GPI_MFP3: PI14MFP Mask */ 4544 4545 #define SYS_GPI_MFP3_PI15MFP_Pos (24) /*!< SYS_T::GPI_MFP3: PI15MFP Position */ 4546 #define SYS_GPI_MFP3_PI15MFP_Msk (0x1ful << SYS_GPI_MFP3_PI15MFP_Pos) /*!< SYS_T::GPI_MFP3: PI15MFP Mask */ 4547 4548 #define SYS_GPJ_MFP0_PJ0MFP_Pos (0) /*!< SYS_T::GPJ_MFP0: PJ0MFP Position */ 4549 #define SYS_GPJ_MFP0_PJ0MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ0MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ0MFP Mask */ 4550 4551 #define SYS_GPJ_MFP0_PJ1MFP_Pos (8) /*!< SYS_T::GPJ_MFP0: PJ1MFP Position */ 4552 #define SYS_GPJ_MFP0_PJ1MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ1MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ1MFP Mask */ 4553 4554 #define SYS_GPJ_MFP0_PJ2MFP_Pos (16) /*!< SYS_T::GPJ_MFP0: PJ2MFP Position */ 4555 #define SYS_GPJ_MFP0_PJ2MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ2MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ2MFP Mask */ 4556 4557 #define SYS_GPJ_MFP0_PJ3MFP_Pos (24) /*!< SYS_T::GPJ_MFP0: PJ3MFP Position */ 4558 #define SYS_GPJ_MFP0_PJ3MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ3MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ3MFP Mask */ 4559 4560 #define SYS_GPJ_MFP1_PJ4MFP_Pos (0) /*!< SYS_T::GPJ_MFP1: PJ4MFP Position */ 4561 #define SYS_GPJ_MFP1_PJ4MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ4MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ4MFP Mask */ 4562 4563 #define SYS_GPJ_MFP1_PJ5MFP_Pos (8) /*!< SYS_T::GPJ_MFP1: PJ5MFP Position */ 4564 #define SYS_GPJ_MFP1_PJ5MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ5MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ5MFP Mask */ 4565 4566 #define SYS_GPJ_MFP1_PJ6MFP_Pos (16) /*!< SYS_T::GPJ_MFP1: PJ6MFP Position */ 4567 #define SYS_GPJ_MFP1_PJ6MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ6MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ6MFP Mask */ 4568 4569 #define SYS_GPJ_MFP1_PJ7MFP_Pos (24) /*!< SYS_T::GPJ_MFP1: PJ7MFP Position */ 4570 #define SYS_GPJ_MFP1_PJ7MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ7MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ7MFP Mask */ 4571 4572 #define SYS_GPJ_MFP2_PJ8MFP_Pos (0) /*!< SYS_T::GPJ_MFP2: PJ8MFP Position */ 4573 #define SYS_GPJ_MFP2_PJ8MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ8MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ8MFP Mask */ 4574 4575 #define SYS_GPJ_MFP2_PJ9MFP_Pos (8) /*!< SYS_T::GPJ_MFP2: PJ9MFP Position */ 4576 #define SYS_GPJ_MFP2_PJ9MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ9MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ9MFP Mask */ 4577 4578 #define SYS_GPJ_MFP2_PJ10MFP_Pos (16) /*!< SYS_T::GPJ_MFP2: PJ10MFP Position */ 4579 #define SYS_GPJ_MFP2_PJ10MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ10MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ10MFP Mask */ 4580 4581 #define SYS_GPJ_MFP2_PJ11MFP_Pos (24) /*!< SYS_T::GPJ_MFP2: PJ11MFP Position */ 4582 #define SYS_GPJ_MFP2_PJ11MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ11MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ11MFP Mask */ 4583 4584 #define SYS_GPJ_MFP3_PJ12MFP_Pos (0) /*!< SYS_T::GPJ_MFP3: PJ12MFP Position */ 4585 #define SYS_GPJ_MFP3_PJ12MFP_Msk (0x1ful << SYS_GPJ_MFP3_PJ12MFP_Pos) /*!< SYS_T::GPJ_MFP3: PJ12MFP Mask */ 4586 4587 #define SYS_GPJ_MFP3_PJ13MFP_Pos (8) /*!< SYS_T::GPJ_MFP3: PJ13MFP Position */ 4588 #define SYS_GPJ_MFP3_PJ13MFP_Msk (0x1ful << SYS_GPJ_MFP3_PJ13MFP_Pos) /*!< SYS_T::GPJ_MFP3: PJ13MFP Mask */ 4589 4590 /**@}*/ /* SYS_CONST */ 4591 /**@}*/ /* end of SYS register group */ 4592 4593 /** 4594 @addtogroup NMI NMI Controller (NMI) 4595 Memory Mapped Structure for NMI Controller 4596 @{ */ 4597 4598 typedef struct 4599 { 4600 4601 4602 /** 4603 * @var NMI_T::NMIEN 4604 * Offset: 0x00 NMI Source Interrupt Enable Register 4605 * --------------------------------------------------------------------------------------------------- 4606 * |Bits |Field |Descriptions 4607 * | :----: | :----: | :---- | 4608 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) 4609 * | | |0 = BOD NMI source Disabled. 4610 * | | |1 = BOD NMI source Enabled. 4611 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4612 * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect) 4613 * | | |0 = IRC TRIM NMI source Disabled. 4614 * | | |1 = IRC TRIM NMI source Enabled. 4615 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4616 * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect) 4617 * | | |0 = Power-down mode wake-up NMI source Disabled. 4618 * | | |1 = Power-down mode wake-up NMI source Enabled. 4619 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4620 * |[3] |SRAMPERR |SRAM Parity Check NMI Source Enable (Write Protect) 4621 * | | |0 = SRAM parity check error NMI source Disabled. 4622 * | | |1 = SRAM parity check error NMI source Enabled. 4623 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4624 * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) 4625 * | | |0 = Clock fail detected interrupt NMI source Disabled. 4626 * | | |1 = Clock fail detected interrupt NMI source Enabled. 4627 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4628 * |[6] |RTCINT |RTC NMI Source Enable (Write Protect) 4629 * | | |0 = RTC NMI source Disabled. 4630 * | | |1 = RTC NMI source Enabled. 4631 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4632 * |[7] |TAMPERINT |TAMPER NMI Source Enable (Write Protect) 4633 * | | |0 = Backup register tamper detected NMI source Disabled. 4634 * | | |1 = Backup register tamper detected NMI source Enabled. 4635 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4636 * |[8] |EINT0 |External Interrupt from INT0 Pins NMI Source Enable (Write Protect) 4637 * | | |0 = External interrupt from INT0 pins NMI source Disabled. 4638 * | | |1 = External interrupt from INT0 pins NMI source Enabled. 4639 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4640 * |[9] |EINT1 |External Interrupt from INT1 Pins NMI Source Enable (Write Protect) 4641 * | | |0 = External interrupt from INT1 pins NMI source Disabled. 4642 * | | |1 = External interrupt from INT1 pins NMI source Enabled. 4643 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4644 * |[10] |EINT2 |External Interrupt rrom INT2 Pins NMI Source Enable (Write Protect) 4645 * | | |0 = External interrupt from INT2 pins NMI source Disabled. 4646 * | | |1 = External interrupt from INT2 pins NMI source Enabled. 4647 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4648 * |[11] |EINT3 |External Interrupt from INT3 Pins NMI Source Enable (Write Protect) 4649 * | | |0 = External interrupt from INT3 pins NMI source Disabled. 4650 * | | |1 = External interrupt from INT3 pins pin NMI source Enabled. 4651 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4652 * |[12] |EINT4 |External Interrupt from INT4 Pins NMI Source Enable (Write Protect) 4653 * | | |0 = External interrupt from INT4 pins NMI source Disabled. 4654 * | | |1 = External interrupt from INT4 pins NMI source Enabled. 4655 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4656 * |[13] |EINT5 |External Interrupt from INT5 Pins NMI Source Enable (Write Protect) 4657 * | | |0 = External interrupt from INT5 pins NMI source Disabled. 4658 * | | |1 = External interrupt from INT5 pins NMI source Enabled. 4659 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4660 * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect) 4661 * | | |0 = UART0 NMI source Disabled. 4662 * | | |1 = UART0 NMI source Enabled. 4663 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4664 * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect) 4665 * | | |0 = UART1 NMI source Disabled. 4666 * | | |1 = UART1 NMI source Enabled. 4667 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 4668 * @var NMI_T::NMISTS 4669 * Offset: 0x04 NMI Source Interrupt Status Register 4670 * --------------------------------------------------------------------------------------------------- 4671 * |Bits |Field |Descriptions 4672 * | :----: | :----: | :---- | 4673 * |[0] |BODOUT |BOD Interrupt Flag (Read Only) 4674 * | | |0 = BOD interrupt is deasserted. 4675 * | | |1 = BOD interrupt is asserted. 4676 * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only) 4677 * | | |0 = IRC TRIM interrupt is deasserted. 4678 * | | |1 = IRC TRIM interrupt is asserted. 4679 * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only) 4680 * | | |0 = Power-down mode wake-up interrupt is deasserted. 4681 * | | |1 = Power-down mode wake-up interrupt is asserted. 4682 * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only) 4683 * | | |0 = SRAM parity check error interrupt is deasserted. 4684 * | | |1 = SRAM parity check error interrupt is asserted. 4685 * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) 4686 * | | |0 = Clock fail detected interrupt is deasserted. 4687 * | | |1 = Clock fail detected interrupt is asserted. 4688 * |[6] |RTCINT |RTC Interrupt Flag (Read Only) 4689 * | | |0 = RTC interrupt is deasserted. 4690 * | | |1 = RTC interrupt is asserted. 4691 * |[7] |TAMPERINT |TAMPER Interrupt Flag (Read Only) 4692 * | | |0 = Backup register tamper detected interrupt is deasserted. 4693 * | | |1 = Backup register tamper detected interrupt is asserted. 4694 * |[8] |EINT0 |External Interrupt from INT0 Pins Interrupt Flag (Read Only) 4695 * | | |0 = External Interrupt from INT0 interrupt is deasserted. 4696 * | | |1 = External Interrupt from INT0 interrupt is asserted. 4697 * |[9] |EINT1 |External Interrupt from INT1 Pins Interrupt Flag (Read Only) 4698 * | | |0 = External Interrupt from INT1 interrupt is deasserted. 4699 * | | |1 = External Interrupt from INT1 interrupt is asserted. 4700 * |[10] |EINT2 |External Interrupt from INT2 Pins Interrupt Flag (Read Only) 4701 * | | |0 = External Interrupt from INT2 interrupt is deasserted. 4702 * | | |1 = External Interrupt from INT2 interrupt is asserted. 4703 * |[11] |EINT3 |External Interrupt from INT3 Pins Interrupt Flag (Read Only) 4704 * | | |0 = External Interrupt from INT3 interrupt is deasserted. 4705 * | | |1 = External Interrupt from INT3 interrupt is asserted. 4706 * |[12] |EINT4 |External Interrupt from INT4 Pins Interrupt Flag (Read Only) 4707 * | | |0 = External Interrupt from INT4 interrupt is deasserted. 4708 * | | |1 = External Interrupt from INT4 interrupt is asserted. 4709 * |[13] |EINT5 |External Interrupt from INT5 Pins Interrupt Flag (Read Only) 4710 * | | |0 = External Interrupt from INT5 interrupt is deasserted. 4711 * | | |1 = External Interrupt from INT5 interrupt is asserted. 4712 * |[14] |UART0INT |UART0 Interrupt Flag (Read Only) 4713 * | | |0 = UART1 interrupt is deasserted. 4714 * | | |1 = UART1 interrupt is asserted. 4715 * |[15] |UART1INT |UART1 Interrupt Flag (Read Only) 4716 * | | |0 = UART1 interrupt is deasserted. 4717 * | | |1 = UART1 interrupt is asserted. 4718 */ 4719 __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ 4720 __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ 4721 4722 } NMI_T; 4723 4724 /** 4725 @addtogroup NMI_CONST NMI Bit Field Definition 4726 Constant Definitions for NMI Controller 4727 @{ */ 4728 4729 #define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ 4730 #define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ 4731 4732 #define NMI_NMIEN_IRCINT_Pos (1) /*!< NMI_T::NMIEN: IRCINT Position */ 4733 #define NMI_NMIEN_IRCINT_Msk (0x1ul << NMI_NMIEN_IRCINT_Pos) /*!< NMI_T::NMIEN: IRCINT Mask */ 4734 4735 #define NMI_NMIEN_PWRWUINT_Pos (2) /*!< NMI_T::NMIEN: PWRWUINT Position */ 4736 #define NMI_NMIEN_PWRWUINT_Msk (0x1ul << NMI_NMIEN_PWRWUINT_Pos) /*!< NMI_T::NMIEN: PWRWUINT Mask */ 4737 4738 #define NMI_NMIEN_SRAMPERR_Pos (3) /*!< NMI_T::NMIEN: SRAMPERR Position */ 4739 #define NMI_NMIEN_SRAMPERR_Msk (0x1ul << NMI_NMIEN_SRAMPERR_Pos) /*!< NMI_T::NMIEN: SRAMPERR Mask */ 4740 4741 #define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ 4742 #define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ 4743 4744 #define NMI_NMIEN_RTCINT_Pos (6) /*!< NMI_T::NMIEN: RTCINT Position */ 4745 #define NMI_NMIEN_RTCINT_Msk (0x1ul << NMI_NMIEN_RTCINT_Pos) /*!< NMI_T::NMIEN: RTCINT Mask */ 4746 4747 #define NMI_NMIEN_TAMPERINT_Pos (7) /*!< NMI_T::NMIEN: TAMPERINT Position */ 4748 #define NMI_NMIEN_TAMPERINT_Msk (0x1ul << NMI_NMIEN_TAMPERINT_Pos) /*!< NMI_T::NMIEN: TAMPERINT Mask */ 4749 4750 #define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ 4751 #define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ 4752 4753 #define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ 4754 #define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ 4755 4756 #define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ 4757 #define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ 4758 4759 #define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ 4760 #define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ 4761 4762 #define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ 4763 #define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ 4764 4765 #define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ 4766 #define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ 4767 4768 #define NMI_NMIEN_UART0INT_Pos (14) /*!< NMI_T::NMIEN: UART0INT Position */ 4769 #define NMI_NMIEN_UART0INT_Msk (0x1ul << NMI_NMIEN_UART0INT_Pos) /*!< NMI_T::NMIEN: UART0INT Mask */ 4770 4771 #define NMI_NMIEN_UART1INT_Pos (15) /*!< NMI_T::NMIEN: UART1INT Position */ 4772 #define NMI_NMIEN_UART1INT_Msk (0x1ul << NMI_NMIEN_UART1INT_Pos) /*!< NMI_T::NMIEN: UART1INT Mask */ 4773 4774 #define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ 4775 #define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ 4776 4777 #define NMI_NMISTS_IRCINT_Pos (1) /*!< NMI_T::NMISTS: IRCINT Position */ 4778 #define NMI_NMISTS_IRCINT_Msk (0x1ul << NMI_NMISTS_IRC_NT_Pos) /*!< NMI_T::NMISTS: IRCINT Mask */ 4779 4780 #define NMI_NMISTS_PWRWUINT_Pos (2) /*!< NMI_T::NMISTS: PWRWUINT Position */ 4781 #define NMI_NMISTS_PWRWUINT_Msk (0x1ul << NMI_NMISTS_PWRWUINT_Pos) /*!< NMI_T::NMISTS: PWRWUINT Mask */ 4782 4783 #define NMI_NMISTS_SRAMPERR_Pos (3) /*!< NMI_T::NMISTS: SRAMPERR Position */ 4784 #define NMI_NMISTS_SRAMPERR_Msk (0x1ul << NMI_NMISTS_SRAMPERR_Pos) /*!< NMI_T::NMISTS: SRAMPERR Mask */ 4785 4786 #define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ 4787 #define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ 4788 4789 #define NMI_NMISTS_RTCINT_Pos (6) /*!< NMI_T::NMISTS: RTCINT Position */ 4790 #define NMI_NMISTS_RTCINT_Msk (0x1ul << NMI_NMISTS_RTCINT_Pos) /*!< NMI_T::NMISTS: RTCINT Mask */ 4791 4792 #define NMI_NMISTS_TAMPERINT_Pos (7) /*!< NMI_T::NMISTS: TAMPERINT Position */ 4793 #define NMI_NMISTS_TAMPERINT_Msk (0x1ul << NMI_NMISTS_TAMPERINT_Pos) /*!< NMI_T::NMISTS: TAMPERINT Mask */ 4794 4795 #define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ 4796 #define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ 4797 4798 #define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ 4799 #define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ 4800 4801 #define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ 4802 #define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ 4803 4804 #define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ 4805 #define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ 4806 4807 #define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ 4808 #define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ 4809 4810 #define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ 4811 #define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ 4812 4813 #define NMI_NMISTS_UART0INT_Pos (14) /*!< NMI_T::NMISTS: UART0INT Position */ 4814 #define NMI_NMISTS_UART0INT_Msk (0x1ul << NMI_NMISTS_UART0INT_Pos) /*!< NMI_T::NMISTS: UART0INT Mask */ 4815 4816 #define NMI_NMISTS_UART1INT_Pos (15) /*!< NMI_T::NMISTS: UART1INT Position */ 4817 #define NMI_NMISTS_UART1INT_Msk (0x1ul << NMI_NMISTS_UART1INT_Pos) /*!< NMI_T::NMISTS: UART1INT Mask */ 4818 4819 /**@}*/ /* NMI_CONST */ 4820 /**@}*/ /* end of NMI register group */ 4821 /**@}*/ /* end of REGISTER group */ 4822 4823 #if defined ( __CC_ARM ) 4824 #pragma no_anon_unions 4825 #endif 4826 4827 #endif /* __SYS_REG_H__ */ 4828
