1 /* 2 * Copyright (c) 2021-2023, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /*! ============================================================================ 33 * @file GPIOLPF3.h 34 * 35 * @brief GPIO driver implementation for Low Power F3 devices 36 * 37 * The GPIO header file should be included in an application as follows: 38 * @code 39 * #include <ti/drivers/GPIO.h> 40 * #include <ti/drivers/gpio/GPIOLPF3.h> 41 * @endcode 42 * 43 * Refer to @ref GPIO.h for a complete description of the GPIO 44 * driver APIs provided and examples of their use. 45 * 46 * The definitions in this file should not be used directly. All GPIO_CFG 47 * macros should be used as-is from GPIO.h. 48 * 49 * There are no additional configuration values or platform-specific 50 * functions for GPIOLPF3. 51 */ 52 53 #ifndef ti_drivers_GPIOLPF3__include 54 #define ti_drivers_GPIOLPF3__include 55 56 #include <ti/drivers/GPIO.h> 57 58 #include <ti/devices/DeviceFamily.h> 59 #include DeviceFamily_constructPath(inc/hw_ioc.h) 60 61 #ifdef __cplusplus 62 extern "C" { 63 #endif 64 65 /* Do not configure this pin. */ 66 #define GPIO_CFG_DO_NOT_CONFIG_INTERNAL 0x80000000 67 68 /* Re-map IOC PORTCFG defines from hw_ioc.h to GPIO defines*/ 69 #define GPIO_MUX_PORTCFG_PFUNC7 IOC_IOC3_PORTCFG_DTB 70 #define GPIO_MUX_PORTCFG_PFUNC6 IOC_IOC3_PORTCFG_ANA 71 #define GPIO_MUX_PORTCFG_PFUNC5 IOC_IOC3_PORTCFG_PFUNC5 72 #define GPIO_MUX_PORTCFG_PFUNC4 IOC_IOC3_PORTCFG_PFUNC4 73 #define GPIO_MUX_PORTCFG_PFUNC3 IOC_IOC3_PORTCFG_PFUNC3 74 #define GPIO_MUX_PORTCFG_PFUNC2 IOC_IOC3_PORTCFG_PFUNC2 75 #define GPIO_MUX_PORTCFG_PFUNC1 IOC_IOC3_PORTCFG_PFUNC1 76 #define GPIO_MUX_GPIO_INTERNAL IOC_IOC3_PORTCFG_BASE 77 78 /* We don't define this value on purpose - any unsupported values will cause a 79 * compile-time error. If your compiler tells you that this macro is missing, 80 * you are trying to use an unsupported option. 81 * 82 * See below for which options are unsupported. 83 */ 84 #undef GPIOLPF3_CFG_OPTION_NOT_SUPPORTED 85 86 /* Most configuration values are directly mapped to fields in the IOCn 87 * registers, but the mux bits are reserved for configuration options that 88 * cannot be directly mapped to the IOCn registers. The define below is the 89 * mask used by the GPIO driver to mask off the non-IOC configuration values. 90 */ 91 #define GPIOLPF3_CFG_IOC_M 0xFFFFFFF8 92 93 /* Low and high value interrupts are not available on Low Power F3 devices */ 94 #define GPIO_CFG_INT_LOW_INTERNAL GPIOLPF3_CFG_OPTION_NOT_SUPPORTED 95 #define GPIO_CFG_INT_HIGH_INTERNAL GPIOLPF3_CFG_OPTION_NOT_SUPPORTED 96 97 /* General options */ 98 #define GPIO_CFG_NO_DIR_INTERNAL (IOC_IOC3_IOMODE_NORMAL | GPIOLPF3_CFG_PIN_IS_INPUT_INTERNAL) 99 /* Hysteresis is enabled by default for all input pins due to hardware changes on these devices. 100 * This may impact pin response by 1-2ns, but creates significantly more stable environments for 101 * high-speed use cases like SPI. 102 */ 103 #define GPIO_CFG_INPUT_INTERNAL \ 104 (IOC_IOC3_IOMODE_NORMAL | IOC_IOC3_INPEN | IOC_IOC3_WUENSB | IOC_IOC3_HYSTEN | GPIOLPF3_CFG_PIN_IS_INPUT_INTERNAL) 105 #define GPIO_CFG_OUTPUT_INTERNAL (IOC_IOC3_IOMODE_NORMAL | IOC_IOC3_INPEN | GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL) 106 #define GPIO_CFG_OUTPUT_OPEN_DRAIN_INTERNAL \ 107 (IOC_IOC3_IOMODE_OPEND | IOC_IOC3_INPEN | GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL) 108 #define GPIO_CFG_OUT_OPEN_SOURCE_INTERNAL (IOC_IOC3_IOMODE_OPENS | IOC_IOC3_INPEN | GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL) 109 110 #define GPIO_CFG_PULL_NONE_INTERNAL IOC_IOC3_PULLCTL_PULL_DIS 111 #define GPIO_CFG_PULL_UP_INTERNAL IOC_IOC3_PULLCTL_PULL_UP 112 #define GPIO_CFG_PULL_DOWN_INTERNAL IOC_IOC3_PULLCTL_PULL_DOWN 113 114 #define GPIO_CFG_INT_NONE_INTERNAL IOC_IOC3_EDGEDET_EDGE_DIS 115 #define GPIO_CFG_INT_FALLING_INTERNAL IOC_IOC3_EDGEDET_EDGE_NEG 116 #define GPIO_CFG_INT_RISING_INTERNAL IOC_IOC3_EDGEDET_EDGE_POS 117 #define GPIO_CFG_INT_BOTH_EDGES_INTERNAL IOC_IOC3_EDGEDET_EDGE_BOTH 118 119 /* We can feed this into the low bit of IOMODE, and it can then be ORed with output/input/OD/OS */ 120 #define GPIO_CFG_INVERT_OFF_INTERNAL 0 121 #define GPIO_CFG_INVERT_ON_INTERNAL IOC_IOC3_IOMODE_INVERTED 122 123 #define GPIO_CFG_HYSTERESIS_OFF_INTERNAL 0 124 #define GPIO_CFG_HYSTERESIS_ON_INTERNAL IOC_IOC3_HYSTEN 125 126 #define GPIO_CFG_SHUTDOWN_WAKE_OFF_INTERNAL 0 127 #define GPIO_CFG_SHUTDOWN_WAKE_HIGH_INTERNAL IOC_IOC3_WUCFGSD_WAKE_HIGH 128 #define GPIO_CFG_SHUTDOWN_WAKE_LOW_INTERNAL IOC_IOC3_WUCFGSD_WAKE_LOW 129 130 /* Slew limits and drive strength are only supported on specific pins: pin 12, pins 16-19, and pin 24 */ 131 #define GPIO_CFG_SLEW_NORMAL_INTERNAL IOC_IOC17_SLEWRED_NORMAL 132 #define GPIO_CFG_SLEW_REDUCED_INTERNAL IOC_IOC17_SLEWRED_REDUCED 133 134 #define GPIO_CFG_DRVSTR_LOW_INTERNAL IOC_IOC17_IOCURR_CUR_2MA 135 #define GPIO_CFG_DRVSTR_MED_INTERNAL IOC_IOC17_IOCURR_CUR_4MA 136 #define GPIO_CFG_DRVSTR_HIGH_INTERNAL IOC_IOC17_IOCURR_CUR_8MA 137 138 /* Configuration values stored in mux bits. Any configuration options not 139 * directly handled by IOC need to be stored inside the mux bits (lowest 3 bits 140 * on Low Power F3 devices). These are masked out by GPIO_init(), 141 * GPIO_setConfig(), GPIO_setConfigAndMux() and GPIO_getConfig() using 142 * GPIOLPF3_CFG_IOC_M. 143 */ 144 145 /* Default output value */ 146 #define GPIO_CFG_OUTPUT_DEFAULT_HIGH_INTERNAL 0x1 147 #define GPIO_CFG_OUTPUT_DEFAULT_LOW_INTERNAL 0 148 149 /* Whether GPIO hardware should have the output enable bit set for this pin */ 150 #define GPIOLPF3_CFG_PIN_IS_INPUT_INTERNAL 0x2 151 #define GPIOLPF3_CFG_PIN_IS_OUTPUT_INTERNAL 0 152 153 /* Interrupt enable is in the GPIO module */ 154 #define GPIO_CFG_INT_ENABLE_INTERNAL 0x4 155 #define GPIO_CFG_INT_DISABLE_INTERNAL 0 156 157 #ifdef __cplusplus 158 } 159 #endif 160 161 #endif /* ti_drivers_GPIOCC26XX__include */
