1 /* 2 * Copyright (c) 2019-2024 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file device_definition.c 19 * \brief This file defines exports the structures based on the peripheral 20 * definitions from device_cfg.h. 21 * This file is meant to be used as a helper for baremetal 22 * applications and/or as an example of how to configure the generic 23 * driver structures. 24 */ 25 26 #include "device_definition.h" 27 #include "platform_base_address.h" 28 29 /* Arm ATU driver structures */ 30 #ifdef ATU_S 31 static const struct atu_dev_cfg_t ATU_DEV_CFG_S = { 32 .base = ATU_BASE_S}; 33 struct atu_dev_t ATU_DEV_S = {&ATU_DEV_CFG_S}; 34 #endif 35 36 /* Arm SIC driver structures */ 37 #ifdef SIC_S 38 static const struct sic_dev_cfg_t SIC_DEV_CFG_S = { 39 .base = SIC_BASE_S}; 40 struct sic_dev_t SIC_DEV_S = {&SIC_DEV_CFG_S}; 41 #endif 42 43 /* Arm TRAM driver structures */ 44 #ifdef TRAM_S 45 static const struct tram_dev_cfg_t TRAM_DEV_CFG_S = { 46 .base = TRAM_BASE_S}; 47 struct tram_dev_t TRAM_DEV_S = {&TRAM_DEV_CFG_S}; 48 #endif 49 50 /* UART CMSDK driver structures */ 51 #ifdef UART0_CMSDK_S 52 static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = { 53 .base = RSE_DEBUG_UART0_BASE_S, 54 .default_baudrate = DEFAULT_UART_BAUDRATE 55 }; 56 static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = { 57 .state = 0, 58 .system_clk = 0, 59 .baudrate = 0 60 }; 61 struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S = { 62 &(UART0_CMSDK_DEV_CFG_S), 63 &(UART0_CMSDK_DEV_DATA_S) 64 }; 65 #endif 66 #ifdef UART0_CMSDK_NS 67 static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_NS = { 68 .base = RSE_DEBUG_UART0_BASE_NS, 69 .default_baudrate = DEFAULT_UART_BAUDRATE 70 }; 71 static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = { 72 .state = 0, 73 .system_clk = 0, 74 .baudrate = 0 75 }; 76 struct uart_cmsdk_dev_t UART0_CMSDK_DEV_NS = { 77 &(UART0_CMSDK_DEV_CFG_NS), 78 &(UART0_CMSDK_DEV_DATA_NS) 79 }; 80 #endif 81 82 /* RSE PPC driver structures */ 83 #ifdef PPC_RSE_MAIN0_S 84 static struct ppc_rse_dev_cfg_t PPC_RSE_MAIN0_CFG_S = { 85 .sacfg_base = RSE_SACFG_BASE_S, 86 .nsacfg_base = RSE_NSACFG_BASE_NS, 87 .ppc_name = PPC_RSE_MAIN0}; 88 static struct ppc_rse_dev_data_t PPC_RSE_MAIN0_DATA_S = { 89 .sacfg_ns_ppc = 0, 90 .sacfg_sp_ppc = 0, 91 .nsacfg_nsp_ppc = 0, 92 .int_bit_mask = 0, 93 .is_initialized = false }; 94 struct ppc_rse_dev_t PPC_RSE_MAIN0_DEV_S = { 95 &PPC_RSE_MAIN0_CFG_S, 96 &PPC_RSE_MAIN0_DATA_S }; 97 #endif 98 99 #ifdef PPC_RSE_MAIN_EXP0_S 100 static struct ppc_rse_dev_cfg_t PPC_RSE_MAIN_EXP0_CFG_S = { 101 .sacfg_base = RSE_SACFG_BASE_S, 102 .nsacfg_base = RSE_NSACFG_BASE_NS, 103 .ppc_name = PPC_RSE_MAIN_EXP0}; 104 static struct ppc_rse_dev_data_t PPC_RSE_MAIN_EXP0_DATA_S = { 105 .sacfg_ns_ppc = 0, 106 .sacfg_sp_ppc = 0, 107 .nsacfg_nsp_ppc = 0, 108 .int_bit_mask = 0, 109 .is_initialized = false }; 110 struct ppc_rse_dev_t PPC_RSE_MAIN_EXP0_DEV_S = { 111 &PPC_RSE_MAIN_EXP0_CFG_S, 112 &PPC_RSE_MAIN_EXP0_DATA_S }; 113 #endif 114 115 #ifdef PPC_RSE_MAIN_EXP1_S 116 static struct ppc_rse_dev_cfg_t PPC_RSE_MAIN_EXP1_CFG_S = { 117 .sacfg_base = RSE_SACFG_BASE_S, 118 .nsacfg_base = RSE_NSACFG_BASE_NS, 119 .ppc_name = PPC_RSE_MAIN_EXP1}; 120 static struct ppc_rse_dev_data_t PPC_RSE_MAIN_EXP1_DATA_S = { 121 .sacfg_ns_ppc = 0, 122 .sacfg_sp_ppc = 0, 123 .nsacfg_nsp_ppc = 0, 124 .int_bit_mask = 0, 125 .is_initialized = false }; 126 struct ppc_rse_dev_t PPC_RSE_MAIN_EXP1_DEV_S = { 127 &PPC_RSE_MAIN_EXP1_CFG_S, 128 &PPC_RSE_MAIN_EXP1_DATA_S }; 129 #endif 130 131 #ifdef PPC_RSE_MAIN_EXP2_S 132 static struct ppc_rse_dev_cfg_t PPC_RSE_MAIN_EXP2_CFG_S = { 133 .sacfg_base = RSE_SACFG_BASE_S, 134 .nsacfg_base = RSE_NSACFG_BASE_NS, 135 .ppc_name = PPC_RSE_MAIN_EXP2}; 136 static struct ppc_rse_dev_data_t PPC_RSE_MAIN_EXP2_DATA_S = { 137 .sacfg_ns_ppc = 0, 138 .sacfg_sp_ppc = 0, 139 .nsacfg_nsp_ppc = 0, 140 .int_bit_mask = 0, 141 .is_initialized = false }; 142 struct ppc_rse_dev_t PPC_RSE_MAIN_EXP2_DEV_S = { 143 &PPC_RSE_MAIN_EXP2_CFG_S, 144 &PPC_RSE_MAIN_EXP2_DATA_S }; 145 #endif 146 147 #ifdef PPC_RSE_MAIN_EXP3_S 148 static struct ppc_rse_dev_cfg_t PPC_RSE_MAIN_EXP3_CFG_S = { 149 .sacfg_base = RSE_SACFG_BASE_S, 150 .nsacfg_base = RSE_NSACFG_BASE_NS, 151 .ppc_name = PPC_RSE_MAIN_EXP3}; 152 static struct ppc_rse_dev_data_t PPC_RSE_MAIN_EXP3_DATA_S = { 153 .sacfg_ns_ppc = 0, 154 .sacfg_sp_ppc = 0, 155 .nsacfg_nsp_ppc = 0, 156 .int_bit_mask = 0, 157 .is_initialized = false }; 158 struct ppc_rse_dev_t PPC_RSE_MAIN_EXP3_DEV_S = { 159 &PPC_RSE_MAIN_EXP3_CFG_S, 160 &PPC_RSE_MAIN_EXP3_DATA_S }; 161 #endif 162 163 #ifdef PPC_RSE_PERIPH0_S 164 static struct ppc_rse_dev_cfg_t PPC_RSE_PERIPH0_CFG_S = { 165 .sacfg_base = RSE_SACFG_BASE_S, 166 .nsacfg_base = RSE_NSACFG_BASE_NS, 167 .ppc_name = PPC_RSE_PERIPH0}; 168 static struct ppc_rse_dev_data_t PPC_RSE_PERIPH0_DATA_S = { 169 .sacfg_ns_ppc = 0, 170 .sacfg_sp_ppc = 0, 171 .nsacfg_nsp_ppc = 0, 172 .int_bit_mask = 0, 173 .is_initialized = false }; 174 struct ppc_rse_dev_t PPC_RSE_PERIPH0_DEV_S = { 175 &PPC_RSE_PERIPH0_CFG_S, 176 &PPC_RSE_PERIPH0_DATA_S }; 177 #endif 178 179 #ifdef PPC_RSE_PERIPH1_S 180 static struct ppc_rse_dev_cfg_t PPC_RSE_PERIPH1_CFG_S = { 181 .sacfg_base = RSE_SACFG_BASE_S, 182 .nsacfg_base = RSE_NSACFG_BASE_NS, 183 .ppc_name = PPC_RSE_PERIPH1}; 184 static struct ppc_rse_dev_data_t PPC_RSE_PERIPH1_DATA_S = { 185 .sacfg_ns_ppc = 0, 186 .sacfg_sp_ppc = 0, 187 .nsacfg_nsp_ppc = 0, 188 .int_bit_mask = 0, 189 .is_initialized = false }; 190 struct ppc_rse_dev_t PPC_RSE_PERIPH1_DEV_S = { 191 &PPC_RSE_PERIPH1_CFG_S, 192 &PPC_RSE_PERIPH1_DATA_S }; 193 #endif 194 195 #ifdef PPC_RSE_PERIPH_EXP0_S 196 static struct ppc_rse_dev_cfg_t PPC_RSE_PERIPH_EXP0_CFG_S = { 197 .sacfg_base = RSE_SACFG_BASE_S, 198 .nsacfg_base = RSE_NSACFG_BASE_NS, 199 .ppc_name = PPC_RSE_PERIPH_EXP0}; 200 static struct ppc_rse_dev_data_t PPC_RSE_PERIPH_EXP0_DATA_S = { 201 .sacfg_ns_ppc = 0, 202 .sacfg_sp_ppc = 0, 203 .nsacfg_nsp_ppc = 0, 204 .int_bit_mask = 0, 205 .is_initialized = false }; 206 struct ppc_rse_dev_t PPC_RSE_PERIPH_EXP0_DEV_S = { 207 &PPC_RSE_PERIPH_EXP0_CFG_S, 208 &PPC_RSE_PERIPH_EXP0_DATA_S }; 209 #endif 210 211 #ifdef PPC_RSE_PERIPH_EXP1_S 212 static struct ppc_rse_dev_cfg_t PPC_RSE_PERIPH_EXP1_CFG_S = { 213 .sacfg_base = RSE_SACFG_BASE_S, 214 .nsacfg_base = RSE_NSACFG_BASE_NS, 215 .ppc_name = PPC_RSE_PERIPH_EXP1}; 216 static struct ppc_rse_dev_data_t PPC_RSE_PERIPH_EXP1_DATA_S = { 217 .sacfg_ns_ppc = 0, 218 .sacfg_sp_ppc = 0, 219 .nsacfg_nsp_ppc = 0, 220 .int_bit_mask = 0, 221 .is_initialized = false }; 222 struct ppc_rse_dev_t PPC_RSE_PERIPH_EXP1_DEV_S = { 223 &PPC_RSE_PERIPH_EXP1_CFG_S, 224 &PPC_RSE_PERIPH_EXP1_DATA_S }; 225 #endif 226 227 #ifdef PPC_RSE_PERIPH_EXP2_S 228 static struct ppc_rse_dev_cfg_t PPC_RSE_PERIPH_EXP2_CFG_S = { 229 .sacfg_base = RSE_SACFG_BASE_S, 230 .nsacfg_base = RSE_NSACFG_BASE_NS, 231 .ppc_name = PPC_RSE_PERIPH_EXP2}; 232 static struct ppc_rse_dev_data_t PPC_RSE_PERIPH_EXP2_DATA_S = { 233 .sacfg_ns_ppc = 0, 234 .sacfg_sp_ppc = 0, 235 .nsacfg_nsp_ppc = 0, 236 .int_bit_mask = 0, 237 .is_initialized = false }; 238 struct ppc_rse_dev_t PPC_RSE_PERIPH_EXP2_DEV_S = { 239 &PPC_RSE_PERIPH_EXP2_CFG_S, 240 &PPC_RSE_PERIPH_EXP2_DATA_S }; 241 #endif 242 243 #ifdef PPC_RSE_PERIPH_EXP3_S 244 static struct ppc_rse_dev_cfg_t PPC_RSE_PERIPH_EXP3_CFG_S = { 245 .sacfg_base = RSE_SACFG_BASE_S, 246 .nsacfg_base = RSE_NSACFG_BASE_NS, 247 .ppc_name = PPC_RSE_PERIPH_EXP3}; 248 static struct ppc_rse_dev_data_t PPC_RSE_PERIPH_EXP3_DATA_S = { 249 .sacfg_ns_ppc = 0, 250 .sacfg_sp_ppc = 0, 251 .nsacfg_nsp_ppc = 0, 252 .int_bit_mask = 0, 253 .is_initialized = false }; 254 struct ppc_rse_dev_t PPC_RSE_PERIPH_EXP3_DEV_S = { 255 &PPC_RSE_PERIPH_EXP3_CFG_S, 256 &PPC_RSE_PERIPH_EXP3_DATA_S }; 257 #endif 258 259 /* System counters */ 260 #ifdef SYSCOUNTER_CNTRL_ARMV8_M_S 261 262 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT > \ 263 SYSCOUNTER_ARMV8_M_SCALE_VAL_INT_MAX 264 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT is invalid. 265 #endif 266 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT > \ 267 SYSCOUNTER_ARMV8_M_SCALE_VAL_FRACT_MAX 268 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT is invalid. 269 #endif 270 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT > \ 271 SYSCOUNTER_ARMV8_M_SCALE_VAL_INT_MAX 272 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT is invalid. 273 #endif 274 #if SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT > \ 275 SYSCOUNTER_ARMV8_M_SCALE_VAL_FRACT_MAX 276 #error SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT is invalid. 277 #endif 278 279 static const struct syscounter_armv8_m_cntrl_dev_cfg_t 280 SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_S = { 281 .base = SYSCNTR_CNTRL_BASE_S, 282 .scale0.integer = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT, 283 .scale0.fixed_point_fraction = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT, 284 .scale1.integer = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT, 285 .scale1.fixed_point_fraction = SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 286 }; 287 static struct syscounter_armv8_m_cntrl_dev_data_t 288 SYSCOUNTER_CNTRL_ARMV8_M_DEV_DATA_S = { 289 .is_initialized = false 290 }; 291 struct syscounter_armv8_m_cntrl_dev_t SYSCOUNTER_CNTRL_ARMV8_M_DEV_S = { 292 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_CFG_S), 293 &(SYSCOUNTER_CNTRL_ARMV8_M_DEV_DATA_S) 294 }; 295 #endif 296 297 #ifdef SYSCOUNTER_READ_ARMV8_M_S 298 static const struct syscounter_armv8_m_read_dev_cfg_t 299 SYSCOUNTER_READ_ARMV8_M_DEV_CFG_S = { 300 .base = SYSCNTR_READ_BASE_S, 301 }; 302 struct syscounter_armv8_m_read_dev_t SYSCOUNTER_READ_ARMV8_M_DEV_S = { 303 &(SYSCOUNTER_READ_ARMV8_M_DEV_CFG_S), 304 }; 305 #endif 306 307 /* System timers */ 308 #ifdef SYSTIMER0_ARMV8_M_S 309 static const struct systimer_armv8_m_dev_cfg_t 310 SYSTIMER0_ARMV8_M_DEV_CFG_S = { 311 .base = SYSTIMER0_ARMV8_M_BASE_S, 312 .default_freq_hz = SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ 313 }; 314 static struct systimer_armv8_m_dev_data_t 315 SYSTIMER0_ARMV8_M_DEV_DATA_S = { 316 .is_initialized = false 317 }; 318 struct systimer_armv8_m_dev_t SYSTIMER0_ARMV8_M_DEV_S = { 319 &(SYSTIMER0_ARMV8_M_DEV_CFG_S), 320 &(SYSTIMER0_ARMV8_M_DEV_DATA_S) 321 }; 322 #endif 323 324 #ifdef SYSTIMER0_ARMV8_M_NS 325 static const struct systimer_armv8_m_dev_cfg_t 326 SYSTIMER0_ARMV8_M_DEV_CFG_NS = { 327 .base = SYSTIMER0_ARMV8_M_BASE_NS, 328 .default_freq_hz = SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ 329 }; 330 static struct systimer_armv8_m_dev_data_t 331 SYSTIMER0_ARMV8_M_DEV_DATA_NS = { 332 .is_initialized = false 333 }; 334 struct systimer_armv8_m_dev_t SYSTIMER0_ARMV8_M_DEV_NS = { 335 &(SYSTIMER0_ARMV8_M_DEV_CFG_NS), 336 &(SYSTIMER0_ARMV8_M_DEV_DATA_NS) 337 }; 338 #endif 339 340 #ifdef SYSTIMER1_ARMV8_M_S 341 static const struct systimer_armv8_m_dev_cfg_t 342 SYSTIMER1_ARMV8_M_DEV_CFG_S = { 343 .base = SYSTIMER1_ARMV8_M_BASE_S, 344 .default_freq_hz = SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ 345 }; 346 static struct systimer_armv8_m_dev_data_t 347 SYSTIMER1_ARMV8_M_DEV_DATA_S = { 348 .is_initialized = false 349 }; 350 struct systimer_armv8_m_dev_t SYSTIMER1_ARMV8_M_DEV_S = { 351 &(SYSTIMER1_ARMV8_M_DEV_CFG_S), 352 &(SYSTIMER1_ARMV8_M_DEV_DATA_S) 353 }; 354 #endif 355 356 #ifdef SYSTIMER1_ARMV8_M_NS 357 static const struct systimer_armv8_m_dev_cfg_t 358 SYSTIMER1_ARMV8_M_DEV_CFG_NS = { 359 .base = SYSTIMER1_ARMV8_M_BASE_NS, 360 .default_freq_hz = SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ 361 }; 362 static struct systimer_armv8_m_dev_data_t 363 SYSTIMER1_ARMV8_M_DEV_DATA_NS = { 364 .is_initialized = false 365 }; 366 struct systimer_armv8_m_dev_t SYSTIMER1_ARMV8_M_DEV_NS = { 367 &(SYSTIMER1_ARMV8_M_DEV_CFG_NS), 368 &(SYSTIMER1_ARMV8_M_DEV_DATA_NS) 369 }; 370 #endif 371 372 #ifdef SYSTIMER2_ARMV8_M_S 373 static const struct systimer_armv8_m_dev_cfg_t 374 SYSTIMER2_ARMV8_M_DEV_CFG_S = { 375 .base = SYSTIMER2_ARMV8_M_BASE_S, 376 .default_freq_hz = SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ 377 }; 378 static struct systimer_armv8_m_dev_data_t 379 SYSTIMER2_ARMV8_M_DEV_DATA_S = { 380 .is_initialized = false 381 }; 382 struct systimer_armv8_m_dev_t SYSTIMER2_ARMV8_M_DEV_S = { 383 &(SYSTIMER2_ARMV8_M_DEV_CFG_S), 384 &(SYSTIMER2_ARMV8_M_DEV_DATA_S) 385 }; 386 #endif 387 388 #ifdef SYSTIMER2_ARMV8_M_NS 389 static const struct systimer_armv8_m_dev_cfg_t 390 SYSTIMER2_ARMV8_M_DEV_CFG_NS = { 391 .base = SYSTIMER2_ARMV8_M_BASE_NS, 392 .default_freq_hz = SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ 393 }; 394 static struct systimer_armv8_m_dev_data_t 395 SYSTIMER2_ARMV8_M_DEV_DATA_NS = { 396 .is_initialized = false 397 }; 398 struct systimer_armv8_m_dev_t SYSTIMER2_ARMV8_M_DEV_NS = { 399 &(SYSTIMER2_ARMV8_M_DEV_CFG_NS), 400 &(SYSTIMER2_ARMV8_M_DEV_DATA_NS) 401 }; 402 #endif 403 404 #ifdef SYSTIMER3_ARMV8_M_S 405 static const struct systimer_armv8_m_dev_cfg_t 406 SYSTIMER3_ARMV8_M_DEV_CFG_S = { 407 .base = SYSTIMER3_ARMV8_M_BASE_S, 408 .default_freq_hz = SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ 409 }; 410 static struct systimer_armv8_m_dev_data_t 411 SYSTIMER3_ARMV8_M_DEV_DATA_S = { 412 .is_initialized = false 413 }; 414 struct systimer_armv8_m_dev_t SYSTIMER3_ARMV8_M_DEV_S = { 415 &(SYSTIMER3_ARMV8_M_DEV_CFG_S), 416 &(SYSTIMER3_ARMV8_M_DEV_DATA_S) 417 }; 418 #endif 419 420 #ifdef SYSTIMER3_ARMV8_M_NS 421 static const struct systimer_armv8_m_dev_cfg_t 422 SYSTIMER3_ARMV8_M_DEV_CFG_NS = { 423 .base = SYSTIMER3_ARMV8_M_BASE_NS, 424 .default_freq_hz = SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ 425 }; 426 static struct systimer_armv8_m_dev_data_t 427 SYSTIMER3_ARMV8_M_DEV_DATA_NS = { 428 .is_initialized = false 429 }; 430 struct systimer_armv8_m_dev_t SYSTIMER3_ARMV8_M_DEV_NS = { 431 &(SYSTIMER3_ARMV8_M_DEV_CFG_NS), 432 &(SYSTIMER3_ARMV8_M_DEV_DATA_NS) 433 }; 434 #endif 435 436 /* System Watchdogs */ 437 #ifdef SYSWDOG_ARMV8_M_S 438 static const struct syswdog_armv8_m_dev_cfg_t 439 SYSWDOG_ARMV8_M_DEV_CFG_S = { 440 .base = SYSWDOG_ARMV8_M_CNTRL_BASE_S 441 }; 442 struct syswdog_armv8_m_dev_t SYSWDOG_ARMV8_M_DEV_S = { 443 &(SYSWDOG_ARMV8_M_DEV_CFG_S) 444 }; 445 #endif 446 447 #ifdef SYSWDOG_ARMV8_M_NS 448 static const struct syswdog_armv8_m_dev_cfg_t 449 SYSWDOG_ARMV8_M_DEV_CFG_NS = { 450 .base = SYSWDOG_ARMV8_M_CNTRL_BASE_NS 451 }; 452 struct syswdog_armv8_m_dev_t SYSWDOG_ARMV8_M_DEV_NS = { 453 &(SYSWDOG_ARMV8_M_DEV_CFG_NS) 454 }; 455 #endif 456 457 /* ARM MPC RSE driver structures */ 458 #ifdef MPC_VM0_S 459 /* Ranges controlled by this VM0_MPC */ 460 static const struct mpc_sie_memory_range_t MPC_VM0_RANGE_S = { 461 .base = MPC_VM0_RANGE_BASE_S, 462 .limit = MPC_VM0_RANGE_LIMIT_S, 463 .range_offset = 0, 464 .attr = MPC_SIE_SEC_ATTR_SECURE 465 }; 466 467 static const struct mpc_sie_memory_range_t MPC_VM0_RANGE_NS = { 468 .base = MPC_VM0_RANGE_BASE_NS, 469 .limit = MPC_VM0_RANGE_LIMIT_NS, 470 .range_offset = 0, 471 .attr = MPC_SIE_SEC_ATTR_NONSECURE 472 }; 473 474 #define MPC_VM0_RANGE_LIST_LEN 2u 475 static const struct mpc_sie_memory_range_t* 476 MPC_VM0_RANGE_LIST[MPC_VM0_RANGE_LIST_LEN] = { 477 &MPC_VM0_RANGE_S, 478 &MPC_VM0_RANGE_NS 479 }; 480 481 static const struct mpc_sie_dev_cfg_t MPC_VM0_DEV_CFG_S = { 482 .base = MPC_VM0_BASE_S, 483 .range_list = MPC_VM0_RANGE_LIST, 484 .nbr_of_ranges = MPC_VM0_RANGE_LIST_LEN}; 485 static struct mpc_sie_dev_data_t MPC_VM0_DEV_DATA_S = { 486 .is_initialized = false }; 487 struct mpc_sie_dev_t MPC_VM0_DEV_S = { 488 &(MPC_VM0_DEV_CFG_S), 489 &(MPC_VM0_DEV_DATA_S)}; 490 #endif 491 492 #ifdef MPC_VM1_S 493 /* Ranges controlled by this VM1_MPC */ 494 static const struct mpc_sie_memory_range_t MPC_VM1_RANGE_S = { 495 .base = MPC_VM1_RANGE_BASE_S, 496 .limit = MPC_VM1_RANGE_LIMIT_S, 497 .range_offset = 0, 498 .attr = MPC_SIE_SEC_ATTR_SECURE 499 }; 500 501 static const struct mpc_sie_memory_range_t MPC_VM1_RANGE_NS = { 502 .base = MPC_VM1_RANGE_BASE_NS, 503 .limit = MPC_VM1_RANGE_LIMIT_NS, 504 .range_offset = 0, 505 .attr = MPC_SIE_SEC_ATTR_NONSECURE 506 }; 507 508 #define MPC_VM1_RANGE_LIST_LEN 2u 509 static const struct mpc_sie_memory_range_t* 510 MPC_VM1_RANGE_LIST[MPC_VM1_RANGE_LIST_LEN] = { 511 &MPC_VM1_RANGE_S, 512 &MPC_VM1_RANGE_NS 513 }; 514 515 static const struct mpc_sie_dev_cfg_t MPC_VM1_DEV_CFG_S = { 516 .base = MPC_VM1_BASE_S, 517 .range_list = MPC_VM1_RANGE_LIST, 518 .nbr_of_ranges = MPC_VM1_RANGE_LIST_LEN}; 519 static struct mpc_sie_dev_data_t MPC_VM1_DEV_DATA_S = { 520 .is_initialized = false }; 521 struct mpc_sie_dev_t MPC_VM1_DEV_S = { 522 &(MPC_VM1_DEV_CFG_S), 523 &(MPC_VM1_DEV_DATA_S)}; 524 #endif 525 526 #ifdef MPC_SIC_S 527 /* Ranges controlled by this SIC_MPC */ 528 static const struct mpc_sie_memory_range_t MPC_SIC_RANGE_S = { 529 .base = MPC_SIC_RANGE_BASE_S, 530 .limit = MPC_SIC_RANGE_LIMIT_S, 531 .range_offset = 0, 532 .attr = MPC_SIE_SEC_ATTR_SECURE 533 }; 534 535 static const struct mpc_sie_memory_range_t MPC_SIC_RANGE_NS = { 536 .base = MPC_SIC_RANGE_BASE_NS, 537 .limit = MPC_SIC_RANGE_LIMIT_NS, 538 .range_offset = 0, 539 .attr = MPC_SIE_SEC_ATTR_NONSECURE 540 }; 541 542 #define MPC_SIC_RANGE_LIST_LEN 2u 543 static const struct mpc_sie_memory_range_t* 544 MPC_SIC_RANGE_LIST[MPC_SIC_RANGE_LIST_LEN] = { 545 &MPC_SIC_RANGE_S, 546 &MPC_SIC_RANGE_NS 547 }; 548 549 static const struct mpc_sie_dev_cfg_t MPC_SIC_DEV_CFG_S = { 550 .base = MPC_SIC_BASE_S, 551 .range_list = MPC_SIC_RANGE_LIST, 552 .nbr_of_ranges = MPC_SIC_RANGE_LIST_LEN}; 553 static struct mpc_sie_dev_data_t MPC_SIC_DEV_DATA_S = { 554 .is_initialized = false }; 555 struct mpc_sie_dev_t MPC_SIC_DEV_S = { 556 &(MPC_SIC_DEV_CFG_S), 557 &(MPC_SIC_DEV_DATA_S)}; 558 #endif 559 560 #ifdef KMU_S 561 static struct kmu_dev_cfg_t KMU_DEV_CFG_S = { 562 .base = KMU_BASE_S 563 }; 564 struct kmu_dev_t KMU_DEV_S = { 565 .cfg = &(KMU_DEV_CFG_S) 566 }; 567 #endif 568 569 #ifdef SAM_S 570 static const struct sam_dev_cfg_t SAM_DEV_CFG_S = { 571 .base = SAM_BASE_S, 572 573 /* Default SAM config that enables all events and sets all response actions 574 * to reset (except watchdog). 575 */ 576 .default_config = { 577 0xFFFFFFFF, 0x0000001F, 578 0xF99FFFFF, 0x0000001F, 579 0x88888828, 0x88888888, 580 0x80000088, 0x88888008, 581 0x00088888, 0x00000000, 582 0x00000000, 0x00000000, 583 0x00000000, 0x00000000, 584 0x00000000, 0x00000000, 585 0x00000000, 0x00000000, 586 0x00000000, 0x00000000, 587 0x00000000, 0x00000000, 588 0x00000000, 589 590 /* This is the integrity check value, it must equal the zero count of 591 * the rest of the SAM config. 592 */ 593 0x0000027C, 594 }, 595 }; 596 struct sam_dev_t SAM_DEV_S = { 597 .cfg = &SAM_DEV_CFG_S, 598 .event_handlers = {0}, 599 }; 600 #endif 601 602 #ifdef LCM_S 603 static struct lcm_dev_cfg_t LCM_DEV_CFG_S = { 604 .base = LCM_BASE_S 605 }; 606 struct lcm_dev_t LCM_DEV_S = { 607 .cfg = &(LCM_DEV_CFG_S) 608 }; 609 #endif 610 611 #ifdef INTEGRITY_CHECKER_S 612 static struct integrity_checker_dev_cfg_t INTEGRITY_CHECKER_DEV_CFG_S = { 613 .base = INTEGRITY_CHECKER_BASE_S, 614 .remap_cpusel = 0, 615 .remap_regions = { 616 {ITCM_BASE_S, ITCM_SIZE, ITCM_CPU0_BASE_S, 0x01000000}, 617 {ITCM_BASE_NS, ITCM_SIZE, ITCM_CPU0_BASE_NS, 0x01000000}, 618 {DTCM_BASE_S, DTCM_SIZE, DTCM_CPU0_BASE_S, 0x01000000}, 619 {DTCM_BASE_NS, DTCM_SIZE, DTCM_CPU0_BASE_NS, 0x01000000}, 620 } 621 }; 622 struct integrity_checker_dev_t INTEGRITY_CHECKER_DEV_S = { 623 .cfg = &(INTEGRITY_CHECKER_DEV_CFG_S) 624 }; 625 #endif 626 627 #ifdef DMA350_DMA0_S 628 static const struct dma350_dev_cfg_t DMA350_DMA0_DEV_CFG_S = { 629 .dma_sec_cfg = (DMASECCFG_TypeDef*) (DMA_350_BASE_S + 0x0UL), 630 .dma_sec_ctrl = (DMASECCTRL_TypeDef*) (DMA_350_BASE_S + 0x100UL), 631 .dma_nsec_ctrl = (DMANSECCTRL_TypeDef*) (DMA_350_BASE_S + 0x200UL), 632 .dma_info = (DMAINFO_TypeDef*) (DMA_350_BASE_S + 0xF00UL) 633 }; 634 static struct dma350_dev_data_t DMA350_DMA0_DEV_DATA_S = { 635 .state = 0 636 }; 637 struct dma350_dev_t DMA350_DMA0_DEV_S = { 638 &(DMA350_DMA0_DEV_CFG_S), 639 &(DMA350_DMA0_DEV_DATA_S) 640 }; 641 #endif 642 643 #ifdef DMA350_DMA0_CH0_S 644 struct dma350_ch_dev_t DMA350_DMA0_CH0_DEV_S = { 645 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1000UL), 646 .channel = 0}, 647 .data = {0} 648 }; 649 #endif 650 651 #ifdef DMA350_DMA0_CH1_S 652 struct dma350_ch_dev_t DMA350_DMA0_CH1_DEV_S = { 653 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1100UL), 654 .channel = 1}, 655 .data = {0} 656 }; 657 #endif 658 659 #ifdef DMA350_DMA0_CH2_S 660 struct dma350_ch_dev_t DMA350_DMA0_CH2_DEV_S = { 661 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1200UL), 662 .channel = 2}, 663 .data = {0} 664 }; 665 #endif 666 667 #ifdef DMA350_DMA0_CH3_S 668 struct dma350_ch_dev_t DMA350_DMA0_CH3_DEV_S = { 669 .cfg = {.ch_base = (DMACH_TypeDef*) (DMA_350_BASE_S + 0x1300UL), 670 .channel = 3}, 671 .data = {0} 672 }; 673 #endif 674 675 #ifdef GPIO0_S 676 pl061_regblk_t *const GPIO0_DEV_S = (pl061_regblk_t *) GPIO0_BASE_S; 677 #endif 678 679 #ifdef GPIO1_S 680 pl061_regblk_t *const GPIO1_DEV_S = (pl061_regblk_t *) GPIO1_BASE_S; 681 #endif 682 683 #ifdef GPIO0_NS 684 pl061_regblk_t *const GPIO0_DEV_NS = (pl061_regblk_t *) GPIO0_BASE_NS; 685 #endif 686 687 #ifdef GPIO1_NS 688 pl061_regblk_t *const GPIO1_DEV_NS = (pl061_regblk_t *) GPIO1_BASE_NS; 689 #endif 690
