1 /******************************************************************************* 2 * Copyright 2020 Microchip Corporation. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * This file contains system specific definitions for the PolarFire SoC MSS 7 * Ethernet MAC device driver. 8 * 9 * Note: This file is maintained in the driver source repository in the same 10 * folder as the driver source to keep them consistent but in the example 11 * repositories the working copy resides in the current boards 12 * platform_config/drivers/mss_mac folder and a reference copy is found in 13 * the platform/platform_config_reference/drivers/mss_mac folder. 14 * 15 */ 16 17 #ifndef MICROSEMI__FIRMWARE__POLARFIRE_SOC_MSS_ETHERNET_MAC_DRIVER__1_7_107_CONFIGURATION_HEADER 18 #define MICROSEMI__FIRMWARE__POLARFIRE_SOC_MSS_ETHERNET_MAC_DRIVER__1_7_107_CONFIGURATION_HEADER 19 20 21 /***************************************************************************//** 22 * When running the documentation scripts, this macro should be defined to make 23 * sure the maximal macro selections are enabled so that the scripts pick up 24 * the complete documentation. 25 * 26 * Some macro definitions that are not normally used will be enabled if this 27 * macro is defined... 28 */ 29 #if 0 30 #define MSS_MAC_DOCUMENTATION 31 #endif 32 33 34 /***************************************************************************//** 35 * Define this macro to add support for lower latency receive interrupt handling 36 * which may improve performance for full bandwidth network performance testing. 37 * 38 * If using debug mode build, you might set the NDEBUG macro in the project 39 * settings to further reduce interrupt overhead when using this option. 40 */ 41 #if defined(MSS_MAC_DOCUMENTATION) 42 #define MSS_MAC_UNH_TEST 43 #endif 44 45 /***************************************************************************//** 46 * This macro is normally defined at project level to select MPFS as the 47 * platform. The alternative is to define _TARGET_ALOE_ for the SiFive Aloe or 48 * Aloe + Vera boards. 49 */ 50 #if defined(MSS_MAC_DOCUMENTATION) 51 #define TARGET_G5_SOC 52 #endif 53 54 55 /***************************************************************************//** 56 * Driver versioning macros. 57 */ 58 #define CORE_VENDOR "Microsemi" 59 #define CORE_LIBRARY "Firmware" 60 #define CORE_NAME "PolarFire_SoC_MSS_Ethernet_MAC_Driver" 61 #define CORE_VERSION "1.7.107" 62 63 64 /***************************************************************************//** 65 * Define this macro to add support for high speed transmission for network 66 * saturation testing. Not recommended for normal builds of the code as it may 67 * cause some unexpected behaviour for normal operations. 68 * 69 * If using debug mode build, you might set the NDEBUG macro in the project 70 * settings to reduce interrupt overhead when using this option. 71 */ 72 #if defined(MSS_MAC_DOCUMENTATION) 73 #define MSS_MAC_SPEED_TEST 74 #endif 75 76 /***************************************************************************//** 77 * Defines for OS and network stack specific support. 78 * 79 * Un-comment as necessary or define in project properties etc. 80 */ 81 #if defined(MSS_MAC_DOCUMENTATION) 82 #define USING_FREERTOS 83 #define USING_LWIP 84 #endif 85 86 /***************************************************************************//** 87 * Supported PHY interface types: 88 */ 89 90 #define NULL_PHY (0x0001U) /*!< @brief No PHY in connection, for example GEM0 and GEM1 connected via fabric */ 91 #define GMII (0x0002U) /*!< @brief Currently only on Aloe board */ 92 #define TBI (0x0004U) /*!< @brief G5 SoC Emulation Platform designs with TBI */ 93 #define GMII_SGMII (0x0008U) /*!< @brief G5 SoC Emulation Platform designs with SGMII to GMII conversion */ 94 #if 0 95 #define BASEX1000 (0x0010U) /* Not currently available */ 96 #define RGMII (0x0020U) /* Not currently available */ 97 #define RMII (0x0040U) /* Not currently available */ 98 #define SGMII (0x0080U) /* Not currently available */ 99 #endif 100 101 /***************************************************************************//** 102 * Supported PHY models, used to control compile time inclusion of the 103 * associated PHY sub-drivers. 104 */ 105 106 #define MSS_MAC_DEV_PHY_NULL (0x0001U) /*!< @brief No PHY device connected, for loopback and direct connection configurations */ 107 #define MSS_MAC_DEV_PHY_VSC8575 (0x0002U) /*!< @brief VSC8575 using full VTSS API */ 108 #define MSS_MAC_DEV_PHY_VSC8541 (0x0004U) /*!< @brief VSC8541 without VTSS API */ 109 #define MSS_MAC_DEV_PHY_DP83867 (0x0008U) /*!< @brief TI DP83867 */ 110 #define MSS_MAC_DEV_PHY_VSC8575_LITE (0x0010U) /*!< @brief VSC8575 using Lite VTSS API */ 111 #define MSS_MAC_DEV_PHY_VSC8662 (0x0020U) /*!< @brief VSC8662 without VTSS API */ 112 113 114 /***************************************************************************//** 115 * Defines for the different hardware configurations for the applications using 116 * the driver. Used to allow software configure GPIO etc, to support the 117 * appropriate hardware configuration. 118 * 119 * Not strictly part of the driver but we manage them here to keep things tidy. 120 */ 121 122 #define MSS_MAC_DESIGN_ALOE (0) /*!< @brief ALOE board from Sifive (GMII)*/ 123 #define MSS_MAC_DESIGN_EMUL_GMII (1) /*!< @brief G5 SoC Emulation Platform VSC8575 designs with GMII to SGMII bridge on GEM0 */ 124 #define MSS_MAC_DESIGN_EMUL_TBI (2) /*!< @brief G5 SoC Emulation Platform VSC8575 designs with TBI to SGMII bridge on GEM0 */ 125 #define MSS_MAC_DESIGN_EMUL_DUAL_INTERNAL (3) /*!< @brief G5 SoC Emulation Platform Dual GEM design with loopback in fabric */ 126 #define MSS_MAC_DESIGN_EMUL_TI_GMII (4) /*!< @brief G5 SoC Emulation Platform DP83867 design with GMII to SGMII bridge */ 127 #define MSS_MAC_DESIGN_EMUL_DUAL_EX_TI (5) /*!< @brief G5 SoC Emulation Platform Dual GEM design with external TI PHY on GEM1 (GMII) */ 128 #define MSS_MAC_DESIGN_EMUL_DUAL_EX_VTS (6) /*!< @brief G5 SoC Emulation Platform Dual GEM design with external Vitess PHY on GEM0 (GMII) */ 129 #define MSS_MAC_DESIGN_EMUL_GMII_GEM1 (7) /*!< @brief G5 SoC Emulation Platform VSC8575 designs with GMII to SGMII bridge on GEM 1 */ 130 #define MSS_MAC_DESIGN_EMUL_DUAL_EXTERNAL (8) /*!< @brief G5 SoC Emulation Platform Dual GEM design with GEM0 -> VSC, GEM1 -> TI (both GMII) */ 131 #define MSS_MAC_DESIGN_EMUL_TBI_GEM1 (9) /*!< @brief G5 SoC Emulation Platform VSC8575 designs with TBI to SGMII bridge GEM1 */ 132 #define MSS_MAC_DESIGN_EMUL_TBI_TI (10) /*!< @brief G5 SoC Emulation Platform DP83867 designs with TBI to SGMII bridge GEM0 */ 133 #define MSS_MAC_DESIGN_EMUL_TBI_GEM1_TI (11) /*!< @brief G5 SoC Emulation Platform DP83867 designs with TBI to SGMII bridge GEM1 */ 134 #define MSS_MAC_DESIGN_EMUL_GMII_LOCAL (12) /*!< @brief G5 SoC Emulation Platform VSC8575 design with GMII to SGMII bridge with local ints */ 135 #define MSS_MAC_DESIGN_RENODE (13) /*!< @brief Renode */ 136 #define MSS_MAC_DESIGN_SVG_SGMII_GEM0 (14) /*!< @brief Silicon validation board GEM0 */ 137 #define MSS_MAC_DESIGN_SVG_SGMII_GEM1 (15) /*!< @brief Silicon validation board GEM1 */ 138 #define MSS_MAC_DESIGN_SVG_DUAL_GEM (16) /*!< @brief Silicon validation board both GEMS */ 139 #define MSS_MAC_DESIGN_SVG_GMII_GEM0 (17) /*!< @brief Silicon validation board GEM0 */ 140 #define MSS_MAC_DESIGN_SVG_GMII_GEM1 (18) /*!< @brief Silicon validation board GEM1 */ 141 #define MSS_MAC_DESIGN_ICICLE_SGMII_GEM0 (19) /*!< @brief Icicle board GEM0 */ 142 #define MSS_MAC_DESIGN_ICICLE_SGMII_GEM1 (20) /*!< @brief Icicle board GEM1 */ 143 #define MSS_MAC_DESIGN_ICICLE_SGMII_GEMS (21) /*!< @brief Icicle board GEM0 and GEM1 */ 144 #define MSS_MAC_DESIGN_ICICLE_STD_GEM0 (22) /*!< @brief Icicle board GEM0 Standard Reference Design */ 145 #define MSS_MAC_DESIGN_ICICLE_STD_GEM1 (23) /*!< @brief Icicle board GEM1 Standard Reference Design */ 146 #define MSS_MAC_DESIGN_ICICLE_STD_GEMS (24) /*!< @brief Icicle board GEM0 and GEM1 Standard Reference Design */ 147 #define MSS_MAC_DESIGN_SVG_GMII_GEM0_SGMII_GEM1 (25) /*!< @brief Silicon validation board GEM0 (GMII) and GEM1 (SGMII) */ 148 149 #if defined(TARGET_ALOE) 150 #define MSS_MAC_PHY_INTERFACE GMII /* Only one option allowed here... */ 151 #define MSS_MAC_RX_RING_SIZE (4U) 152 #define MSS_MAC_TX_RING_SIZE (2U) 153 #define MSS_MAC_PHYS (MSS_MAC_DEV_PHY_NULL | MSS_MAC_DEV_PHY_VSC8541) 154 #define MSS_MAC_HW_PLATFORM MSS_MAC_DESIGN_ALOE 155 #endif 156 157 /***************************************************************************//** 158 * Define one of these macros if using the VSC8662 PHY recovered clock through 159 * the NWC at 25MHZ or 125MHZ. You will need to configure the SGMII PLL Mux as 160 * well. 161 */ 162 #if defined(MSS_MAC_DOCUMENTATION) 163 #define MSS_MAC_VSC8662_NWC_25 164 #define MSS_MAC_VSC8662_NWC_125 165 #endif 166 167 #if defined(TARGET_G5_SOC) 168 /***************************************************************************//** 169 * This macro is a bit map that indicates which PHY sub drivers are included in 170 * this build. 171 */ 172 #define MSS_MAC_PHYS (MSS_MAC_DEV_PHY_NULL | MSS_MAC_DEV_PHY_VSC8575_LITE | MSS_MAC_DEV_PHY_DP83867 | MSS_MAC_DEV_PHY_VSC8662 | MSS_MAC_DEV_PHY_VSC8541) 173 174 /***************************************************************************//** 175 * Set this macro to one of the _MSS_MAC_DESIGN_XX_ macros to configure the 176 * hardware platform for the application. 177 */ 178 #define MSS_MAC_HW_PLATFORM MSS_MAC_DESIGN_ICICLE_STD_GEM0 179 //#define MSS_MAC_HW_PLATFORM MSS_MAC_DESIGN_SVG_SGMII_GEM1 180 //#define MSS_MAC_HW_PLATFORM MSS_MAC_DESIGN_EMUL_DUAL_EX_VTS 181 /***************************************************************************//** 182 * Number of receive buffer descriptors per queue. 183 * 184 * Minimum size is 16 as the descriptor caching implemented by the GEM DMA 185 * requires that we make sure there are valid packet descriptors in all the 186 * cached buffer slots. 187 */ 188 #define MSS_MAC_RX_RING_SIZE (16U) 189 190 /***************************************************************************//** 191 * Number of transmit buffer descriptors per queue. 192 * 193 * Minimum size is 16 as the descriptor caching implemented by the GEM DMA 194 * requires that we make sure there are valid packet descriptors in all the 195 * cached buffer slots. 196 */ 197 #if defined(MSS_MAC_SPEED_TEST) 198 #define MSS_MAC_TX_RING_SIZE (4001U) 199 #else 200 #define MSS_MAC_TX_RING_SIZE (16U) 201 #endif 202 #endif 203 204 /***************************************************************************//** 205 * Macros for testing for different PHY models supported in the current build. 206 */ 207 #define MSS_MAC_USE_PHY_VSC8575 (0U != (MSS_MAC_PHYS & MSS_MAC_DEV_PHY_VSC8575)) 208 #define MSS_MAC_USE_PHY_VSC8575_LITE (0U != (MSS_MAC_PHYS & MSS_MAC_DEV_PHY_VSC8575_LITE)) 209 #define MSS_MAC_USE_PHY_VSC8541 (0U != (MSS_MAC_PHYS & MSS_MAC_DEV_PHY_VSC8541)) 210 #define MSS_MAC_USE_PHY_DP83867 (0U != (MSS_MAC_PHYS & MSS_MAC_DEV_PHY_DP83867)) 211 #define MSS_MAC_USE_PHY_NULL (0U != (MSS_MAC_PHYS & MSS_MAC_DEV_PHY_NULL)) 212 #define MSS_MAC_USE_PHY_VSC8662 (0U != (MSS_MAC_PHYS & MSS_MAC_DEV_PHY_VSC8662)) 213 214 /***************************************************************************//** 215 * Macros for selecting options which change the size of the DMA descriptors. 216 * Both these features change the layout of the descriptors as there are 217 * additional entries needed in the descriptors to support them. 218 */ 219 #if !defined(MSS_MAC_SPEED_TEST) || defined(MSS_MAC_DOCUMENTATION) 220 #define MSS_MAC_TIME_STAMPED_MODE (0) /*!< @brief Enable time stamp support */ 221 #define MSS_MAC_64_BIT_ADDRESS_MODE (0) /*!< @brief Enable 64 bit addressing */ 222 #endif 223 224 /***************************************************************************//** 225 * Defines for different memory areas. Set the macro _MSS_MAC_USE_DDR_ to one of 226 * these values to select the area of memory and buffer sizes to use when 227 * testing for non LIM based areas of memory. 228 */ 229 230 #define MSS_MAC_MEM_DDR (0) 231 #define MSS_MAC_MEM_FIC0 (1) 232 #define MSS_MAC_MEM_FIC1 (2) 233 #define MSS_MAC_MEM_CRYPTO (3) 234 235 /***************************************************************************//** 236 * Number of additional queues for PMAC (eMAC only has 1). 237 * 238 * __Note:__ We explicitly set the number of queues in the MAC structure as we 239 * have to indicate the Interrupt Number so this is slightly artificial... 240 */ 241 #if defined(TARGET_ALOE) 242 #define MSS_MAC_QUEUE_COUNT (1) 243 #else 244 #if defined(MSS_MAC_SPEED_TEST) 245 #define MSS_MAC_QUEUE_COUNT (1) 246 #else 247 #define MSS_MAC_QUEUE_COUNT (4) 248 #endif 249 #endif 250 251 252 /***************************************************************************//** 253 * Number of Type 1 and 2 screeners for pMAC. 254 */ 255 256 #define MSS_MAC_TYPE_1_SCREENERS (4U) 257 #define MSS_MAC_TYPE_2_SCREENERS (4U) 258 #define MSS_MAC_TYPE_2_ETHERTYPES (4U) 259 #define MSS_MAC_TYPE_2_COMPARERS (12U) 260 261 /***************************************************************************//** 262 * Number of Type 1 and 2 screeners for eMAC. 263 * 264 * These are hard coded and not user selectable 265 */ 266 #define MSS_MAC_EMAC_TYPE_2_SCREENERS (2U) 267 #define MSS_MAC_EMAC_TYPE_2_COMPARERS (6U) 268 269 /***************************************************************************//** 270 * Define one or both of these macros to enable support for hardware based 271 * Hard Reset or Soft Reset of the PHY. This will result in inclusion of the 272 * MSS GPIO driver in the project. 273 */ 274 #if defined(MSS_MAC_DOCUMENTATION) 275 #define MSS_MAC_PHY_HW_RESET /*!< @brief If this is defined, the hard reset of the PHY is controllable via GPIO. */ 276 #endif 277 #if defined(MSS_MAC_DOCUMENTATION) 278 #define MSS_MAC_PHY_HW_SRESET /*!< @brief If this is defined, the hard reset of the PHY is controllable via GPIO. */ 279 #endif 280 281 #endif /* MICROSEMI__FIRMWARE__POLARFIRE_SOC_MSS_ETHERNET_MAC_DRIVER__1_7_107_CONFIGURATION_HEADER */ 282
