1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup GMAC_DRIVER GMAC Driver
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Gmac_Ip_Hw_Access.h"
25 #include "Gmac_Ip_Irq.h"
26
27 /*==================================================================================================
28 * SOURCE FILE VERSION INFORMATION
29 ==================================================================================================*/
30 #define GMAC_IP_IRQ_VENDOR_ID_C 43
31 #define GMAC_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4
32 #define GMAC_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7
33 #define GMAC_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0
34 #define GMAC_IP_IRQ_SW_MAJOR_VERSION_C 3
35 #define GMAC_IP_IRQ_SW_MINOR_VERSION_C 0
36 #define GMAC_IP_IRQ_SW_PATCH_VERSION_C 0
37
38 /*==================================================================================================
39 * FILE VERSION CHECKS
40 ==================================================================================================*/
41 /* Checks against Gmac_Ip_Hw_Access.h */
42 #if (GMAC_IP_IRQ_VENDOR_ID_C != GMAC_IP_HW_ACCESS_VENDOR_ID)
43 #error "Gmac_Ip_Irq.c and Gmac_Ip_Hw_Access.h have different vendor ids"
44 #endif
45 #if ((GMAC_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION) || \
46 (GMAC_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION) || \
47 (GMAC_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION))
48 #error "AUTOSAR Version Numbers of Gmac_Ip_Irq.c and Gmac_Ip_Hw_Access.h are different"
49 #endif
50 #if ((GMAC_IP_IRQ_SW_MAJOR_VERSION_C != GMAC_IP_HW_ACCESS_SW_MAJOR_VERSION) || \
51 (GMAC_IP_IRQ_SW_MINOR_VERSION_C != GMAC_IP_HW_ACCESS_SW_MINOR_VERSION) || \
52 (GMAC_IP_IRQ_SW_PATCH_VERSION_C != GMAC_IP_HW_ACCESS_SW_PATCH_VERSION))
53 #error "Software Version Numbers of Gmac_Ip_Irq.c and Gmac_Ip_Hw_Access.h are different"
54 #endif
55
56 /* Checks against Gmac_Ip_Irq.h */
57 #if (GMAC_IP_IRQ_VENDOR_ID_C != GMAC_IP_IRQ_VENDOR_ID)
58 #error "Gmac_Ip_Irq.c and Gmac_Ip_Irq.h have different vendor ids"
59 #endif
60 #if ((GMAC_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != GMAC_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
61 (GMAC_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != GMAC_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
62 (GMAC_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != GMAC_IP_IRQ_AR_RELEASE_REVISION_VERSION))
63 #error "AUTOSAR Version Numbers of Gmac_Ip_Irq.c and Gmac_Ip_Irq.h are different"
64 #endif
65 #if ((GMAC_IP_IRQ_SW_MAJOR_VERSION_C != GMAC_IP_IRQ_SW_MAJOR_VERSION) || \
66 (GMAC_IP_IRQ_SW_MINOR_VERSION_C != GMAC_IP_IRQ_SW_MINOR_VERSION) || \
67 (GMAC_IP_IRQ_SW_PATCH_VERSION_C != GMAC_IP_IRQ_SW_PATCH_VERSION))
68 #error "Software Version Numbers of Gmac_Ip_Irq.c and Gmac_Ip_Irq.h are different"
69 #endif
70
71 /*******************************************************************************
72 * Code
73 ******************************************************************************/
74 #define ETH_43_GMAC_START_SEC_CODE
75 #include "Eth_43_GMAC_MemMap.h"
76
77
78 #if (FEATURE_GMAC_NUM_INSTANCES > 0U)
79 /* Handle common interrupt */
ISR(GMAC0_Common_IRQHandler)80 ISR(GMAC0_Common_IRQHandler)
81 {
82 GMAC_CommonIRQHandler(0U);
83 }
84
85 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
86 /* Handle safety interrupt */
ISR(GMAC0_Safety_IRQHandler)87 ISR(GMAC0_Safety_IRQHandler)
88 {
89 GMAC_SafetyIRQHandler(0U);
90 }
91 #endif
92
93 #if FEATURE_GMAC_INDIVIDUAL_CH_IRQS
94
95 #if (FEATURE_GMAC_NUM_CHANNELS > 0U)
96 /* Handle Tx interrupt for channel 0 */
ISR(GMAC0_CH0_TX_IRQHandler)97 ISR(GMAC0_CH0_TX_IRQHandler)
98 {
99 GMAC_TxIRQHandler(0U, 0U);
100 }
101 /* Handle Rx interrupt for channel 0 */
ISR(GMAC0_CH0_RX_IRQHandler)102 ISR(GMAC0_CH0_RX_IRQHandler)
103 {
104 GMAC_RxIRQHandler(0U, 0U);
105 }
106 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 0U) */
107
108 #if (FEATURE_GMAC_NUM_CHANNELS > 1U)
109 /* Handle Tx interrupt for channel 1 */
ISR(GMAC0_CH1_TX_IRQHandler)110 ISR(GMAC0_CH1_TX_IRQHandler)
111 {
112 GMAC_TxIRQHandler(0U, 1U);
113 }
114 /* Handle Rx interrupt for channel 1 */
ISR(GMAC0_CH1_RX_IRQHandler)115 ISR(GMAC0_CH1_RX_IRQHandler)
116 {
117 GMAC_RxIRQHandler(0U, 1U);
118 }
119 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 1U) */
120
121 #if (FEATURE_GMAC_NUM_CHANNELS > 2U)
122 /* Handle Tx interrupt for channel 2 */
ISR(GMAC0_CH2_TX_IRQHandler)123 ISR(GMAC0_CH2_TX_IRQHandler)
124 {
125 GMAC_TxIRQHandler(0U, 2U);
126 }
127 /* Handle Rx interrupt for channel 2 */
ISR(GMAC0_CH2_RX_IRQHandler)128 ISR(GMAC0_CH2_RX_IRQHandler)
129 {
130 GMAC_RxIRQHandler(0U, 2U);
131 }
132 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 2U) */
133
134 #if (FEATURE_GMAC_NUM_CHANNELS > 3U)
135 /* Handle Tx interrupt for channel 3 */
ISR(GMAC0_CH3_TX_IRQHandler)136 ISR(GMAC0_CH3_TX_IRQHandler)
137 {
138 GMAC_TxIRQHandler(0U, 3U);
139 }
140 /* Handle Rx interrupt for channel 3 */
ISR(GMAC0_CH3_RX_IRQHandler)141 ISR(GMAC0_CH3_RX_IRQHandler)
142 {
143 GMAC_RxIRQHandler(0U, 3U);
144 }
145 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 3U) */
146
147 #if (FEATURE_GMAC_NUM_CHANNELS > 4U)
148 /* Handle Tx interrupt for channel 4 */
ISR(GMAC0_CH4_TX_IRQHandler)149 ISR(GMAC0_CH4_TX_IRQHandler)
150 {
151 GMAC_TxIRQHandler(0U, 4U);
152 }
153 /* Handle Rx interrupt for channel 4 */
ISR(GMAC0_CH4_RX_IRQHandler)154 ISR(GMAC0_CH4_RX_IRQHandler)
155 {
156 GMAC_RxIRQHandler(0U, 4U);
157 }
158 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 4U) */
159
160 #elif FEATURE_GMAC_UNIFIED_CH_IRQS
161 /* Find Tx channel flag raised */
ISR(GMAC0_CH_TX_IRQHandler)162 ISR(GMAC0_CH_TX_IRQHandler)
163 {
164 #if (FEATURE_GMAC_NUM_CHANNELS > 4U)
165 if ((IP_GMAC_0->DMA_CH4_STATUS & GMAC_DMA_CH4_STATUS_TI_MASK) != 0U)
166 {
167 GMAC_TxIRQHandler(0U, 4U);
168 }
169 #endif
170 #if (FEATURE_GMAC_NUM_CHANNELS > 3U)
171 if ((IP_GMAC_0->DMA_CH3_STATUS & GMAC_DMA_CH3_STATUS_TI_MASK) != 0U)
172 {
173 GMAC_TxIRQHandler(0U, 3U);
174 }
175 #endif
176 #if (FEATURE_GMAC_NUM_CHANNELS > 2U)
177 if ((IP_GMAC_0->DMA_CH2_STATUS & GMAC_DMA_CH2_STATUS_TI_MASK) != 0U)
178 {
179 GMAC_TxIRQHandler(0U, 2U);
180 }
181 #endif
182 #if (FEATURE_GMAC_NUM_CHANNELS > 1U)
183 if ((IP_GMAC_0->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_TI_MASK) != 0U)
184 {
185 GMAC_TxIRQHandler(0U, 1U);
186 }
187 #endif
188 #if (FEATURE_GMAC_NUM_CHANNELS > 0U)
189 if ((IP_GMAC_0->DMA_CH0_STATUS & GMAC_DMA_CH0_STATUS_TI_MASK) != 0U)
190 {
191 GMAC_TxIRQHandler(0U, 0U);
192 }
193 #endif
194 }
195
196 /* Find Rx channel flag raised */
ISR(GMAC0_CH_RX_IRQHandler)197 ISR(GMAC0_CH_RX_IRQHandler)
198 {
199 #if (FEATURE_GMAC_NUM_CHANNELS > 4U)
200 if ((IP_GMAC_0->DMA_CH4_STATUS & GMAC_DMA_CH4_STATUS_RI_MASK) != 0U)
201 {
202 GMAC_RxIRQHandler(0U, 4U);
203 }
204 #endif
205 #if (FEATURE_GMAC_NUM_CHANNELS > 3U)
206 if ((IP_GMAC_0->DMA_CH3_STATUS & GMAC_DMA_CH3_STATUS_RI_MASK) != 0U)
207 {
208 GMAC_RxIRQHandler(0U, 3U);
209 }
210 #endif
211 #if (FEATURE_GMAC_NUM_CHANNELS > 2U)
212 if ((IP_GMAC_0->DMA_CH2_STATUS & GMAC_DMA_CH2_STATUS_RI_MASK) != 0U)
213 {
214 GMAC_RxIRQHandler(0U, 2U);
215 }
216 #endif
217 #if (FEATURE_GMAC_NUM_CHANNELS > 1U)
218 if ((IP_GMAC_0->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_RI_MASK) != 0U)
219 {
220 GMAC_RxIRQHandler(0U, 1U);
221 }
222 #endif
223 #if (FEATURE_GMAC_NUM_CHANNELS > 0U)
224 if ((IP_GMAC_0->DMA_CH0_STATUS & GMAC_DMA_CH0_STATUS_RI_MASK) != 0U)
225 {
226 GMAC_RxIRQHandler(0U, 0U);
227 }
228 #endif
229 }
230 #endif /* FEATURE_GMAC_INDIVIDUAL_CH_IRQS */
231 #endif /* FEATURE_GMAC_NUM_INSTANCES > 0U*/
232 #if (FEATURE_GMAC_NUM_INSTANCES > 1U)
233
ISR(GMAC1_Common_IRQHandler)234 ISR(GMAC1_Common_IRQHandler)
235 {
236 GMAC_CommonIRQHandler(1U);
237 }
238
239 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
ISR(GMAC1_Safety_IRQHandler)240 ISR(GMAC1_Safety_IRQHandler)
241 {
242 GMAC_SafetyIRQHandler(1U);
243 }
244 #endif
245
246 #if FEATURE_GMAC_INDIVIDUAL_CH_IRQS
247
248 #if (FEATURE_GMAC_NUM_CHANNELS > 0U)
ISR(GMAC1_CH0_TX_IRQHandler)249 ISR(GMAC1_CH0_TX_IRQHandler)
250 {
251 GMAC_TxIRQHandler(1U, 0U);
252 }
ISR(GMAC1_CH0_RX_IRQHandler)253 ISR(GMAC1_CH0_RX_IRQHandler)
254 {
255 GMAC_RxIRQHandler(1U, 0U);
256 }
257 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 0U) */
258
259 #if (FEATURE_GMAC_NUM_CHANNELS > 1U)
ISR(GMAC1_CH1_TX_IRQHandler)260 ISR(GMAC1_CH1_TX_IRQHandler)
261 {
262 GMAC_TxIRQHandler(1U, 1U);
263 }
ISR(GMAC1_CH1_RX_IRQHandler)264 ISR(GMAC1_CH1_RX_IRQHandler)
265 {
266 GMAC_RxIRQHandler(1U, 1U);
267 }
268 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 1U) */
269
270 #if (FEATURE_GMAC_NUM_CHANNELS > 2U)
ISR(GMAC1_CH2_TX_IRQHandler)271 ISR(GMAC1_CH2_TX_IRQHandler)
272 {
273 GMAC_TxIRQHandler(1U, 2U);
274 }
ISR(GMAC1_CH2_RX_IRQHandler)275 ISR(GMAC1_CH2_RX_IRQHandler)
276 {
277 GMAC_RxIRQHandler(1U, 2U);
278 }
279 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 2U) */
280
281 #if (FEATURE_GMAC_NUM_CHANNELS > 3U)
ISR(GMAC1_CH3_TX_IRQHandler)282 ISR(GMAC1_CH3_TX_IRQHandler)
283 {
284 GMAC_TxIRQHandler(1U, 3U);
285 }
ISR(GMAC1_CH3_RX_IRQHandler)286 ISR(GMAC1_CH3_RX_IRQHandler)
287 {
288 GMAC_RxIRQHandler(1U, 3U);
289 }
290 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 3U) */
291
292 #if (FEATURE_GMAC_NUM_CHANNELS > 4U)
ISR(GMAC1_CH4_TX_IRQHandler)293 ISR(GMAC1_CH4_TX_IRQHandler)
294 {
295 GMAC_TxIRQHandler(1U, 4U);
296 }
ISR(GMAC1_CH4_RX_IRQHandler)297 ISR(GMAC1_CH4_RX_IRQHandler)
298 {
299 GMAC_RxIRQHandler(1U, 4U);
300 }
301 #endif /* (FEATURE_GMAC_NUM_CHANNELS > 4U) */
302
303 #elif FEATURE_GMAC_UNIFIED_CH_IRQS
ISR(GMAC1_CH_TX_IRQHandler)304 ISR(GMAC1_CH_TX_IRQHandler)
305 {
306 #if (FEATURE_GMAC_NUM_CHANNELS > 4U)
307 if ((IP_GMAC_1->DMA_CH4_STATUS & GMAC_DMA_CH4_STATUS_TI_MASK) != 0U)
308 {
309 GMAC_TxIRQHandler(1U, 4U);
310 }
311 #endif
312 #if (FEATURE_GMAC_NUM_CHANNELS > 3U)
313 if ((IP_GMAC_1->DMA_CH3_STATUS & GMAC_DMA_CH3_STATUS_TI_MASK) != 0U)
314 {
315 GMAC_TxIRQHandler(1U, 3U);
316 }
317 #endif
318 #if (FEATURE_GMAC_NUM_CHANNELS > 2U)
319 if ((IP_GMAC_1->DMA_CH2_STATUS & GMAC_DMA_CH2_STATUS_TI_MASK) != 0U)
320 {
321 GMAC_TxIRQHandler(1U, 2U);
322 }
323 #endif
324 #if (FEATURE_GMAC_NUM_CHANNELS > 1U)
325 if ((IP_GMAC_1->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_TI_MASK) != 0U)
326 {
327 GMAC_TxIRQHandler(1U, 1U);
328 }
329 #endif
330 #if (FEATURE_GMAC_NUM_CHANNELS > 0U)
331 if ((IP_GMAC_1->DMA_CH0_STATUS & GMAC_DMA_CH0_STATUS_TI_MASK) != 0U)
332 {
333 GMAC_TxIRQHandler(1U, 0U);
334 }
335 #endif
336 }
337
ISR(GMAC1_CH_RX_IRQHandler)338 ISR(GMAC1_CH_RX_IRQHandler)
339 {
340 #if (FEATURE_GMAC_NUM_CHANNELS > 4U)
341 if ((IP_GMAC_1->DMA_CH4_STATUS & GMAC_DMA_CH4_STATUS_RI_MASK) != 0U)
342 {
343 GMAC_RxIRQHandler(1U, 4U);
344 }
345 #endif
346 #if (FEATURE_GMAC_NUM_CHANNELS > 3U)
347 if ((IP_GMAC_1->DMA_CH3_STATUS & GMAC_DMA_CH3_STATUS_RI_MASK) != 0U)
348 {
349 GMAC_RxIRQHandler(1U, 3U);
350 }
351 #endif
352 #if (FEATURE_GMAC_NUM_CHANNELS > 2U)
353 if ((IP_GMAC_1->DMA_CH2_STATUS & GMAC_DMA_CH2_STATUS_RI_MASK) != 0U)
354 {
355 GMAC_RxIRQHandler(1U, 2U);
356 }
357 #endif
358 #if (FEATURE_GMAC_NUM_CHANNELS > 1U)
359 if ((IP_GMAC_1->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_RI_MASK) != 0U)
360 {
361 GMAC_RxIRQHandler(1U, 1U);
362 }
363 #endif
364 #if (FEATURE_GMAC_NUM_CHANNELS > 0U)
365 if ((IP_GMAC_1->DMA_CH0_STATUS & GMAC_DMA_CH0_STATUS_RI_MASK) != 0U)
366 {
367 GMAC_RxIRQHandler(1U, 0U);
368 }
369 #endif
370 }
371 #endif /* FEATURE_GMAC_INDIVIDUAL_CH_IRQS */
372 #endif /* (FEATURE_GMAC_NUM_INSTANCES > 1U) */
373
374 #define ETH_43_GMAC_STOP_SEC_CODE
375 #include "Eth_43_GMAC_MemMap.h"
376
377
378 #ifdef __cplusplus
379 }
380 #endif
381 /** @} */
382
383
