1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ 8 #define ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ 9 10 #include <zephyr/types.h> 11 #include <zephyr/device.h> 12 #include <zephyr/sys/atomic.h> 13 14 /* Cache and Share ability for ITS & Redistributor LPI state tables */ 15 #define GIC_BASER_CACHE_NGNRNE 0x0UL /* Device-nGnRnE */ 16 #define GIC_BASER_CACHE_INNERLIKE 0x0UL /* Same as Inner Cacheability. */ 17 #define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */ 18 #define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */ 19 #define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */ 20 #define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */ 21 #define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */ 22 #define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */ 23 #define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */ 24 #define GIC_BASER_SHARE_NO 0x0UL /* Non-shareable */ 25 #define GIC_BASER_SHARE_INNER 0x1UL /* Inner Shareable */ 26 #define GIC_BASER_SHARE_OUTER 0x2UL /* Outer Shareable */ 27 28 /* 29 * GIC Register Interface Base Addresses 30 */ 31 32 #define GIC_RDIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1) 33 #define GIC_RDIST_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1) 34 35 /* SGI base is at 64K offset from Redistributor */ 36 #define GICR_SGI_BASE_OFF 0x10000 37 38 /* GICR registers offset from RD_base(n) */ 39 #define GICR_CTLR 0x0000 40 #define GICR_IIDR 0x0004 41 #define GICR_TYPER 0x0008 42 #define GICR_STATUSR 0x0010 43 #define GICR_WAKER 0x0014 44 #define GICR_PWRR 0x0024 45 #define GICR_PROPBASER 0x0070 46 #define GICR_PENDBASER 0x0078 47 48 /* Register bit definitions */ 49 50 /* GICD_CTLR Interrupt group definitions */ 51 #define GICD_CTLR_ENABLE_G0 0 52 #define GICD_CTLR_ENABLE_G1NS 1 53 #define GICD_CTLR_ENABLE_G1S 2 54 #define GICD_CTRL_ARE_S 4 55 #define GICD_CTRL_ARE_NS 5 56 #define GICD_CTRL_NS 6 57 #define GICD_CGRL_E1NWF 7 58 59 /* GICD_CTLR Register write progress bit */ 60 #define GICD_CTLR_RWP 31 61 62 /* GICR_CTLR */ 63 #define GICR_CTLR_ENABLE_LPIS BIT(0) 64 #define GICR_CTLR_RWP 3 65 66 /* GICR_IIDR */ 67 #define GICR_IIDR_PRODUCT_ID_SHIFT 24 68 #define GICR_IIDR_PRODUCT_ID_MASK 0xFFUL 69 #define GICR_IIDR_PRODUCT_ID_GET(_val) MASK_GET(_val, GICR_IIDR_PRODUCT_ID) 70 71 /* GICR_TYPER */ 72 #define GICR_TYPER_AFFINITY_VALUE_SHIFT 32 73 #define GICR_TYPER_AFFINITY_VALUE_MASK 0xFFFFFFFFUL 74 #define GICR_TYPER_AFFINITY_VALUE_GET(_val) MASK_GET(_val, GICR_TYPER_AFFINITY_VALUE) 75 #define GICR_TYPER_LAST_SHIFT 4 76 #define GICR_TYPER_LAST_MASK 0x1UL 77 #define GICR_TYPER_LAST_GET(_val) MASK_GET(_val, GICR_TYPER_LAST) 78 #define GICR_TYPER_PROCESSOR_NUMBER_SHIFT 8 79 #define GICR_TYPER_PROCESSOR_NUMBER_MASK 0xFFFFUL 80 #define GICR_TYPER_PROCESSOR_NUMBER_GET(_val) MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER) 81 82 /* GICR_WAKER */ 83 #define GICR_WAKER_PS 1 84 #define GICR_WAKER_CA 2 85 86 /* GICR_PWRR */ 87 #define GICR_PWRR_RDPD 0 88 #define GICR_PWRR_RDAG 1 89 #define GICR_PWRR_RDGPO 3 90 91 /* GICR_PROPBASER */ 92 #define GITR_PROPBASER_ID_BITS_MASK 0x1fUL 93 #define GITR_PROPBASER_INNER_CACHE_SHIFT 7 94 #define GITR_PROPBASER_INNER_CACHE_MASK 0x7UL 95 #define GITR_PROPBASER_SHAREABILITY_SHIFT 10 96 #define GITR_PROPBASER_SHAREABILITY_MASK 0x3UL 97 #define GITR_PROPBASER_ADDR_SHIFT 12 98 #define GITR_PROPBASER_ADDR_MASK 0xFFFFFFFFFFUL 99 #define GITR_PROPBASER_OUTER_CACHE_SHIFT 56 100 #define GITR_PROPBASER_OUTER_CACHE_MASK 0x7UL 101 102 /* GICR_PENDBASER */ 103 #define GITR_PENDBASER_INNER_CACHE_SHIFT 7 104 #define GITR_PENDBASER_INNER_CACHE_MASK 0x7UL 105 #define GITR_PENDBASER_SHAREABILITY_SHIFT 10 106 #define GITR_PENDBASER_SHAREABILITY_MASK 0x3UL 107 #define GITR_PENDBASER_ADDR_SHIFT 16 108 #define GITR_PENDBASER_ADDR_MASK 0xFFFFFFFFFUL 109 #define GITR_PENDBASER_OUTER_CACHE_SHIFT 56 110 #define GITR_PENDBASER_OUTER_CACHE_MASK 0x7UL 111 #define GITR_PENDBASER_PTZ BIT64(62) 112 113 /* GITCD_IROUTER */ 114 #define GIC_DIST_IROUTER 0x6000 115 #define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8) 116 117 /* 118 * ITS registers, offsets from ITS_base 119 */ 120 #define GITS_CTLR 0x0000 121 #define GITS_IIDR 0x0004 122 #define GITS_TYPER 0x0008 123 #define GITS_STATUSR 0x0040 124 #define GITS_UMSIR 0x0048 125 #define GITS_CBASER 0x0080 126 #define GITS_CWRITER 0x0088 127 #define GITS_CREADR 0x0090 128 #define GITS_BASER(n) (0x0100 + ((n) * 8)) 129 130 #define GITS_TRANSLATER 0x10040 131 132 /* ITS CTLR register */ 133 #define GITS_CTLR_ENABLED_SHIFT 0 134 #define GITS_CTLR_ENABLED_MASK 0x1UL 135 #define GITS_CTLR_ITS_NUMBER_SHIFT 4 136 #define GITS_CTLR_ITS_NUMBER_MASK 0xfUL 137 #define GITS_CTLR_QUIESCENT_SHIFT 31 138 #define GITS_CTLR_QUIESCENT_MASK 0x1UL 139 140 #define GITS_CTLR_ENABLED_GET(_val) MASK_GET(_val, GITS_CTLR_ENABLED) 141 #define GITS_CTLR_QUIESCENT_GET(_val) MASK_GET(_val, GITS_CTLR_QUIESCENT) 142 143 /* ITS TYPER register */ 144 #define GITS_TYPER_PHY_SHIFT 0 145 #define GITS_TYPER_PHY_MASK 0x1UL 146 #define GITS_TYPER_VIRT_SHIFT 1 147 #define GITS_TYPER_VIRT_MASK 0x1UL 148 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 149 #define GITS_TYPER_ITT_ENTRY_SIZE_MASK 0xfUL 150 #define GITS_TYPER_IDBITS_SHIFT 8 151 #define GITS_TYPER_IDBITS_MASK 0x1fUL 152 #define GITS_TYPER_DEVBITS_SHIFT 13 153 #define GITS_TYPER_DEVBITS_MASK 0x1fUL 154 #define GITS_TYPER_SEIS_SHIFT 18 155 #define GITS_TYPER_SEIS_MASK 0x1UL 156 #define GITS_TYPER_PTA_SHIFT 19 157 #define GITS_TYPER_PTA_MASK 0x1UL 158 #define GITS_TYPER_HCC_SHIFT 24 159 #define GITS_TYPER_HCC_MASK 0xffUL 160 #define GITS_TYPER_CIDBITS_SHIFT 32 161 #define GITS_TYPER_CIDBITS_MASK 0xfUL 162 #define GITS_TYPER_CIL_SHIFT 36 163 #define GITS_TYPER_CIL_MASK 0x1UL 164 165 #define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE) 166 #define GITS_TYPER_PTA_GET(_val) MASK_GET(_val, GITS_TYPER_PTA) 167 #define GITS_TYPER_HCC_GET(_val) MASK_GET(_val, GITS_TYPER_HCC) 168 #define GITS_TYPER_DEVBITS_GET(_val) MASK_GET(_val, GITS_TYPER_DEVBITS) 169 170 /* ITS COMMON BASER / CBASER register */ 171 172 /* ITS CBASER register */ 173 #define GITS_CBASER_SIZE_SHIFT 0 174 #define GITS_CBASER_SIZE_MASK 0xffUL 175 #define GITS_CBASER_SHAREABILITY_SHIFT 10 176 #define GITS_CBASER_SHAREABILITY_MASK 0x3UL 177 #define GITS_CBASER_ADDR_SHIFT 12 178 #define GITS_CBASER_ADDR_MASK 0xfffffffffUL 179 #define GITS_CBASER_OUTER_CACHE_SHIFT 53 180 #define GITS_CBASER_OUTER_CACHE_MASK 0x7UL 181 #define GITS_CBASER_INNER_CACHE_SHIFT 59 182 #define GITS_CBASER_INNER_CACHE_MASK 0x7UL 183 #define GITS_CBASER_VALID_SHIFT 63 184 #define GITS_CBASER_VALID_MASK 0x1UL 185 186 /* ITS BASER<n> register */ 187 #define GITS_BASER_SIZE_SHIFT 0 188 #define GITS_BASER_SIZE_MASK 0xffUL 189 #define GITS_BASER_PAGE_SIZE_SHIFT 8 190 #define GITS_BASER_PAGE_SIZE_MASK 0x3UL 191 #define GITS_BASER_PAGE_SIZE_4K 0 192 #define GITS_BASER_PAGE_SIZE_16K 1 193 #define GITS_BASER_PAGE_SIZE_64K 2 194 #define GITS_BASER_SHAREABILITY_SHIFT 10 195 #define GITS_BASER_SHAREABILITY_MASK 0x3UL 196 #define GITS_BASER_ADDR_SHIFT 12 197 #define GITS_BASER_ADDR_MASK 0xfffffffff 198 #define GITS_BASER_ENTRY_SIZE_SHIFT 48 199 #define GITS_BASER_ENTRY_SIZE_MASK 0x1fUL 200 #define GITS_BASER_OUTER_CACHE_SHIFT 53 201 #define GITS_BASER_OUTER_CACHE_MASK 0x7UL 202 #define GITS_BASER_TYPE_SHIFT 56 203 #define GITS_BASER_TYPE_MASK 0x7UL 204 #define GITS_BASER_INNER_CACHE_SHIFT 59 205 #define GITS_BASER_INNER_CACHE_MASK 0x7UL 206 #define GITS_BASER_INDIRECT_SHIFT 62 207 #define GITS_BASER_INDIRECT_MASK 0x1UL 208 #define GITS_BASER_VALID_SHIFT 63 209 #define GITS_BASER_VALID_MASK 0x1UL 210 211 #define GITS_BASER_TYPE_NONE 0 212 #define GITS_BASER_TYPE_DEVICE 1 213 #define GITS_BASER_TYPE_COLLECTION 4 214 215 #define GITS_BASER_TYPE_GET(_val) MASK_GET(_val, GITS_BASER_TYPE) 216 #define GITS_BASER_PAGE_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_PAGE_SIZE) 217 #define GITS_BASER_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_ENTRY_SIZE) 218 #define GITS_BASER_INDIRECT_GET(_val) MASK_GET(_val, GITS_BASER_INDIRECT) 219 220 #define GITS_BASER_NR_REGS 8 221 222 /* ITS Commands */ 223 224 #define GITS_CMD_ID_MOVI 0x01 225 #define GITS_CMD_ID_INT 0x03 226 #define GITS_CMD_ID_CLEAR 0x04 227 #define GITS_CMD_ID_SYNC 0x05 228 #define GITS_CMD_ID_MAPD 0x08 229 #define GITS_CMD_ID_MAPC 0x09 230 #define GITS_CMD_ID_MAPTI 0x0a 231 #define GITS_CMD_ID_MAPI 0x0b 232 #define GITS_CMD_ID_INV 0x0c 233 #define GITS_CMD_ID_INVALL 0x0d 234 #define GITS_CMD_ID_MOVALL 0x0e 235 #define GITS_CMD_ID_DISCARD 0x0f 236 237 #define GITS_CMD_ID_OFFSET 0 238 #define GITS_CMD_ID_SHIFT 0 239 #define GITS_CMD_ID_MASK 0xffUL 240 241 #define GITS_CMD_DEVICEID_OFFSET 0 242 #define GITS_CMD_DEVICEID_SHIFT 32 243 #define GITS_CMD_DEVICEID_MASK 0xffffffffUL 244 245 #define GITS_CMD_SIZE_OFFSET 1 246 #define GITS_CMD_SIZE_SHIFT 0 247 #define GITS_CMD_SIZE_MASK 0x1fUL 248 249 #define GITS_CMD_EVENTID_OFFSET 1 250 #define GITS_CMD_EVENTID_SHIFT 0 251 #define GITS_CMD_EVENTID_MASK 0xffffffffUL 252 253 #define GITS_CMD_PINTID_OFFSET 1 254 #define GITS_CMD_PINTID_SHIFT 32 255 #define GITS_CMD_PINTID_MASK 0xffffffffUL 256 257 #define GITS_CMD_ICID_OFFSET 2 258 #define GITS_CMD_ICID_SHIFT 0 259 #define GITS_CMD_ICID_MASK 0xffffUL 260 261 #define GITS_CMD_ITTADDR_OFFSET 2 262 #define GITS_CMD_ITTADDR_SHIFT 8 263 #define GITS_CMD_ITTADDR_MASK 0xffffffffffUL 264 #define GITS_CMD_ITTADDR_ALIGN GITS_CMD_ITTADDR_SHIFT 265 #define GITS_CMD_ITTADDR_ALIGN_SZ (BIT(0) << GITS_CMD_ITTADDR_ALIGN) 266 267 #define GITS_CMD_RDBASE_OFFSET 2 268 #define GITS_CMD_RDBASE_SHIFT 16 269 #define GITS_CMD_RDBASE_MASK 0xffffffffUL 270 #define GITS_CMD_RDBASE_ALIGN GITS_CMD_RDBASE_SHIFT 271 272 #define GITS_CMD_VALID_OFFSET 2 273 #define GITS_CMD_VALID_SHIFT 63 274 #define GITS_CMD_VALID_MASK 0x1UL 275 276 #define MASK(__basename) (__basename##_MASK << __basename##_SHIFT) 277 #define MASK_SET(__val, __basename) (((__val) & __basename##_MASK) << __basename##_SHIFT) 278 #define MASK_GET(__reg, __basename) (((__reg) >> __basename##_SHIFT) & __basename##_MASK) 279 280 #ifdef CONFIG_GIC_V3_ITS 281 void its_rdist_map(void); 282 void its_rdist_invall(void); 283 284 extern atomic_t nlpi_intid; 285 #endif 286 287 #endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ */ 288
