1 /* 2 * Copyright 2020 Broadcom 3 * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ 9 #define ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ 10 11 #include <zephyr/types.h> 12 #include <zephyr/device.h> 13 #include <zephyr/sys/atomic.h> 14 15 /* Cache and Share ability for ITS & Redistributor LPI state tables */ 16 #define GIC_BASER_CACHE_NGNRNE 0x0UL /* Device-nGnRnE */ 17 #define GIC_BASER_CACHE_INNERLIKE 0x0UL /* Same as Inner Cacheability. */ 18 #define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */ 19 #define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */ 20 #define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */ 21 #define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */ 22 #define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */ 23 #define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */ 24 #define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */ 25 #define GIC_BASER_SHARE_NO 0x0UL /* Non-shareable */ 26 #define GIC_BASER_SHARE_INNER 0x1UL /* Inner Shareable */ 27 #define GIC_BASER_SHARE_OUTER 0x2UL /* Outer Shareable */ 28 29 /* SGI base is at 64K offset from Redistributor */ 30 #define GICR_SGI_BASE_OFF 0x10000 31 32 /* GICR registers offset from RD_base(n) */ 33 #define GICR_CTLR 0x0000 34 #define GICR_IIDR 0x0004 35 #define GICR_TYPER 0x0008 36 #define GICR_STATUSR 0x0010 37 #define GICR_WAKER 0x0014 38 #define GICR_PWRR 0x0024 39 #define GICR_PROPBASER 0x0070 40 #define GICR_PENDBASER 0x0078 41 42 /* Register bit definitions */ 43 44 /* GICD_CTLR Interrupt group definitions */ 45 #define GICD_CTLR_ENABLE_G0 0 46 #define GICD_CTLR_ENABLE_G1NS 1 47 #define GICD_CTLR_ENABLE_G1S 2 48 #define GICD_CTRL_ARE_S 4 49 #define GICD_CTRL_ARE_NS 5 50 #define GICD_CTRL_NS 6 51 #define GICD_CGRL_E1NWF 7 52 53 /* GICD_CTLR Register write progress bit */ 54 #define GICD_CTLR_RWP 31 55 56 /* GICR_CTLR */ 57 #define GICR_CTLR_ENABLE_LPIS BIT(0) 58 #define GICR_CTLR_RWP 3 59 60 /* GICR_IIDR */ 61 #define GICR_IIDR_PRODUCT_ID_SHIFT 24 62 #define GICR_IIDR_PRODUCT_ID_MASK 0xFFUL 63 #define GICR_IIDR_PRODUCT_ID_GET(_val) MASK_GET(_val, GICR_IIDR_PRODUCT_ID) 64 65 /* GICR_TYPER */ 66 #define GICR_TYPER_AFFINITY_VALUE_SHIFT 32 67 #define GICR_TYPER_AFFINITY_VALUE_MASK 0xFFFFFFFFUL 68 #define GICR_TYPER_AFFINITY_VALUE_GET(_val) MASK_GET(_val, GICR_TYPER_AFFINITY_VALUE) 69 #define GICR_TYPER_LAST_SHIFT 4 70 #define GICR_TYPER_LAST_MASK 0x1UL 71 #define GICR_TYPER_LAST_GET(_val) MASK_GET(_val, GICR_TYPER_LAST) 72 #define GICR_TYPER_PROCESSOR_NUMBER_SHIFT 8 73 #define GICR_TYPER_PROCESSOR_NUMBER_MASK 0xFFFFUL 74 #define GICR_TYPER_PROCESSOR_NUMBER_GET(_val) MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER) 75 76 /* GICR_WAKER */ 77 #define GICR_WAKER_PS 1 78 #define GICR_WAKER_CA 2 79 80 /* GICR_PWRR */ 81 #define GICR_PWRR_RDPD 0 82 #define GICR_PWRR_RDAG 1 83 #define GICR_PWRR_RDGPO 3 84 85 /* GICR_PROPBASER */ 86 #define GITR_PROPBASER_ID_BITS_MASK 0x1fUL 87 #define GITR_PROPBASER_INNER_CACHE_SHIFT 7 88 #define GITR_PROPBASER_INNER_CACHE_MASK 0x7UL 89 #define GITR_PROPBASER_SHAREABILITY_SHIFT 10 90 #define GITR_PROPBASER_SHAREABILITY_MASK 0x3UL 91 #define GITR_PROPBASER_ADDR_SHIFT 12 92 #define GITR_PROPBASER_ADDR_MASK 0xFFFFFFFFFFUL 93 #define GITR_PROPBASER_OUTER_CACHE_SHIFT 56 94 #define GITR_PROPBASER_OUTER_CACHE_MASK 0x7UL 95 96 /* GICR_PENDBASER */ 97 #define GITR_PENDBASER_INNER_CACHE_SHIFT 7 98 #define GITR_PENDBASER_INNER_CACHE_MASK 0x7UL 99 #define GITR_PENDBASER_SHAREABILITY_SHIFT 10 100 #define GITR_PENDBASER_SHAREABILITY_MASK 0x3UL 101 #define GITR_PENDBASER_ADDR_SHIFT 16 102 #define GITR_PENDBASER_ADDR_MASK 0xFFFFFFFFFUL 103 #define GITR_PENDBASER_OUTER_CACHE_SHIFT 56 104 #define GITR_PENDBASER_OUTER_CACHE_MASK 0x7UL 105 #define GITR_PENDBASER_PTZ BIT64(62) 106 107 /* GITCD_IROUTER */ 108 #define GIC_DIST_IROUTER 0x6000 109 #define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8) 110 111 /* 112 * ITS registers, offsets from ITS_base 113 */ 114 #define GITS_CTLR 0x0000 115 #define GITS_IIDR 0x0004 116 #define GITS_TYPER 0x0008 117 #define GITS_STATUSR 0x0040 118 #define GITS_UMSIR 0x0048 119 #define GITS_CBASER 0x0080 120 #define GITS_CWRITER 0x0088 121 #define GITS_CREADR 0x0090 122 #define GITS_BASER(n) (0x0100 + ((n) * 8)) 123 124 #define GITS_TRANSLATER 0x10040 125 126 /* ITS CTLR register */ 127 #define GITS_CTLR_ENABLED_SHIFT 0 128 #define GITS_CTLR_ENABLED_MASK 0x1UL 129 #define GITS_CTLR_ITS_NUMBER_SHIFT 4 130 #define GITS_CTLR_ITS_NUMBER_MASK 0xfUL 131 #define GITS_CTLR_QUIESCENT_SHIFT 31 132 #define GITS_CTLR_QUIESCENT_MASK 0x1UL 133 134 #define GITS_CTLR_ENABLED_GET(_val) MASK_GET(_val, GITS_CTLR_ENABLED) 135 #define GITS_CTLR_QUIESCENT_GET(_val) MASK_GET(_val, GITS_CTLR_QUIESCENT) 136 137 /* ITS TYPER register */ 138 #define GITS_TYPER_PHY_SHIFT 0 139 #define GITS_TYPER_PHY_MASK 0x1UL 140 #define GITS_TYPER_VIRT_SHIFT 1 141 #define GITS_TYPER_VIRT_MASK 0x1UL 142 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 143 #define GITS_TYPER_ITT_ENTRY_SIZE_MASK 0xfUL 144 #define GITS_TYPER_IDBITS_SHIFT 8 145 #define GITS_TYPER_IDBITS_MASK 0x1fUL 146 #define GITS_TYPER_DEVBITS_SHIFT 13 147 #define GITS_TYPER_DEVBITS_MASK 0x1fUL 148 #define GITS_TYPER_SEIS_SHIFT 18 149 #define GITS_TYPER_SEIS_MASK 0x1UL 150 #define GITS_TYPER_PTA_SHIFT 19 151 #define GITS_TYPER_PTA_MASK 0x1UL 152 #define GITS_TYPER_HCC_SHIFT 24 153 #define GITS_TYPER_HCC_MASK 0xffUL 154 #define GITS_TYPER_CIDBITS_SHIFT 32 155 #define GITS_TYPER_CIDBITS_MASK 0xfUL 156 #define GITS_TYPER_CIL_SHIFT 36 157 #define GITS_TYPER_CIL_MASK 0x1UL 158 159 #define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE) 160 #define GITS_TYPER_PTA_GET(_val) MASK_GET(_val, GITS_TYPER_PTA) 161 #define GITS_TYPER_HCC_GET(_val) MASK_GET(_val, GITS_TYPER_HCC) 162 #define GITS_TYPER_DEVBITS_GET(_val) MASK_GET(_val, GITS_TYPER_DEVBITS) 163 164 /* ITS COMMON BASER / CBASER register */ 165 166 /* ITS CBASER register */ 167 #define GITS_CBASER_SIZE_SHIFT 0 168 #define GITS_CBASER_SIZE_MASK 0xffUL 169 #define GITS_CBASER_SHAREABILITY_SHIFT 10 170 #define GITS_CBASER_SHAREABILITY_MASK 0x3UL 171 #define GITS_CBASER_ADDR_SHIFT 12 172 #define GITS_CBASER_ADDR_MASK 0xfffffffffUL 173 #define GITS_CBASER_OUTER_CACHE_SHIFT 53 174 #define GITS_CBASER_OUTER_CACHE_MASK 0x7UL 175 #define GITS_CBASER_INNER_CACHE_SHIFT 59 176 #define GITS_CBASER_INNER_CACHE_MASK 0x7UL 177 #define GITS_CBASER_VALID_SHIFT 63 178 #define GITS_CBASER_VALID_MASK 0x1UL 179 180 /* ITS BASER<n> register */ 181 #define GITS_BASER_SIZE_SHIFT 0 182 #define GITS_BASER_SIZE_MASK 0xffUL 183 #define GITS_BASER_PAGE_SIZE_SHIFT 8 184 #define GITS_BASER_PAGE_SIZE_MASK 0x3UL 185 #define GITS_BASER_PAGE_SIZE_4K 0 186 #define GITS_BASER_PAGE_SIZE_16K 1 187 #define GITS_BASER_PAGE_SIZE_64K 2 188 #define GITS_BASER_SHAREABILITY_SHIFT 10 189 #define GITS_BASER_SHAREABILITY_MASK 0x3UL 190 #define GITS_BASER_ADDR_SHIFT 12 191 #define GITS_BASER_ADDR_MASK 0xfffffffff 192 #define GITS_BASER_ENTRY_SIZE_SHIFT 48 193 #define GITS_BASER_ENTRY_SIZE_MASK 0x1fUL 194 #define GITS_BASER_OUTER_CACHE_SHIFT 53 195 #define GITS_BASER_OUTER_CACHE_MASK 0x7UL 196 #define GITS_BASER_TYPE_SHIFT 56 197 #define GITS_BASER_TYPE_MASK 0x7UL 198 #define GITS_BASER_INNER_CACHE_SHIFT 59 199 #define GITS_BASER_INNER_CACHE_MASK 0x7UL 200 #define GITS_BASER_INDIRECT_SHIFT 62 201 #define GITS_BASER_INDIRECT_MASK 0x1UL 202 #define GITS_BASER_VALID_SHIFT 63 203 #define GITS_BASER_VALID_MASK 0x1UL 204 205 #define GITS_BASER_TYPE_NONE 0 206 #define GITS_BASER_TYPE_DEVICE 1 207 #define GITS_BASER_TYPE_COLLECTION 4 208 209 #define GITS_BASER_TYPE_GET(_val) MASK_GET(_val, GITS_BASER_TYPE) 210 #define GITS_BASER_PAGE_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_PAGE_SIZE) 211 #define GITS_BASER_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_ENTRY_SIZE) 212 #define GITS_BASER_INDIRECT_GET(_val) MASK_GET(_val, GITS_BASER_INDIRECT) 213 214 #define GITS_BASER_NR_REGS 8 215 216 /* ITS Commands */ 217 218 #define GITS_CMD_ID_MOVI 0x01 219 #define GITS_CMD_ID_INT 0x03 220 #define GITS_CMD_ID_CLEAR 0x04 221 #define GITS_CMD_ID_SYNC 0x05 222 #define GITS_CMD_ID_MAPD 0x08 223 #define GITS_CMD_ID_MAPC 0x09 224 #define GITS_CMD_ID_MAPTI 0x0a 225 #define GITS_CMD_ID_MAPI 0x0b 226 #define GITS_CMD_ID_INV 0x0c 227 #define GITS_CMD_ID_INVALL 0x0d 228 #define GITS_CMD_ID_MOVALL 0x0e 229 #define GITS_CMD_ID_DISCARD 0x0f 230 231 #define GITS_CMD_ID_OFFSET 0 232 #define GITS_CMD_ID_SHIFT 0 233 #define GITS_CMD_ID_MASK 0xffUL 234 235 #define GITS_CMD_DEVICEID_OFFSET 0 236 #define GITS_CMD_DEVICEID_SHIFT 32 237 #define GITS_CMD_DEVICEID_MASK 0xffffffffUL 238 239 #define GITS_CMD_SIZE_OFFSET 1 240 #define GITS_CMD_SIZE_SHIFT 0 241 #define GITS_CMD_SIZE_MASK 0x1fUL 242 243 #define GITS_CMD_EVENTID_OFFSET 1 244 #define GITS_CMD_EVENTID_SHIFT 0 245 #define GITS_CMD_EVENTID_MASK 0xffffffffUL 246 247 #define GITS_CMD_PINTID_OFFSET 1 248 #define GITS_CMD_PINTID_SHIFT 32 249 #define GITS_CMD_PINTID_MASK 0xffffffffUL 250 251 #define GITS_CMD_ICID_OFFSET 2 252 #define GITS_CMD_ICID_SHIFT 0 253 #define GITS_CMD_ICID_MASK 0xffffUL 254 255 #define GITS_CMD_ITTADDR_OFFSET 2 256 #define GITS_CMD_ITTADDR_SHIFT 8 257 #define GITS_CMD_ITTADDR_MASK 0xffffffffffUL 258 #define GITS_CMD_ITTADDR_ALIGN GITS_CMD_ITTADDR_SHIFT 259 #define GITS_CMD_ITTADDR_ALIGN_SZ (BIT(0) << GITS_CMD_ITTADDR_ALIGN) 260 261 #define GITS_CMD_RDBASE_OFFSET 2 262 #define GITS_CMD_RDBASE_SHIFT 16 263 #define GITS_CMD_RDBASE_MASK 0xffffffffUL 264 #define GITS_CMD_RDBASE_ALIGN GITS_CMD_RDBASE_SHIFT 265 266 #define GITS_CMD_VALID_OFFSET 2 267 #define GITS_CMD_VALID_SHIFT 63 268 #define GITS_CMD_VALID_MASK 0x1UL 269 270 #define MASK(__basename) (__basename##_MASK << __basename##_SHIFT) 271 #define MASK_SET(__val, __basename) (((__val) & __basename##_MASK) << __basename##_SHIFT) 272 #define MASK_GET(__reg, __basename) (((__reg) >> __basename##_SHIFT) & __basename##_MASK) 273 274 #ifdef CONFIG_GIC_V3_ITS 275 void its_rdist_map(void); 276 void its_rdist_invall(void); 277 278 extern atomic_t nlpi_intid; 279 #endif 280 281 #endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ */ 282
