1 /*
2  * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef GICV3_H
8 #define GICV3_H
9 
10 /*******************************************************************************
11  * GICv3 and 3.1 miscellaneous definitions
12  ******************************************************************************/
13 /* Interrupt group definitions */
14 #define INTR_GROUP1S		U(0)
15 #define INTR_GROUP0		U(1)
16 #define INTR_GROUP1NS		U(2)
17 
18 /* Interrupt IDs reported by the HPPIR and IAR registers */
19 #define PENDING_G1S_INTID	U(1020)
20 #define PENDING_G1NS_INTID	U(1021)
21 
22 /* Constant to categorize LPI interrupt */
23 #define MIN_LPI_ID		U(8192)
24 
25 /* GICv3 can only target up to 16 PEs with SGI */
26 #define GICV3_MAX_SGI_TARGETS	U(16)
27 
28 /* PPIs INTIDs 16-31 */
29 #define MAX_PPI_ID		U(31)
30 
31 #if GIC_EXT_INTID
32 
33 /* GICv3.1 extended PPIs INTIDs 1056-1119 */
34 #define MIN_EPPI_ID		U(1056)
35 #define MAX_EPPI_ID		U(1119)
36 
37 /* Total number of GICv3.1 EPPIs */
38 #define TOTAL_EPPI_INTR_NUM	(MAX_EPPI_ID - MIN_EPPI_ID + U(1))
39 
40 /* Total number of GICv3.1 PPIs and EPPIs */
41 #define TOTAL_PRIVATE_INTR_NUM	(TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM)
42 
43 /* GICv3.1 extended SPIs INTIDs 4096 - 5119 */
44 #define MIN_ESPI_ID		U(4096)
45 #define MAX_ESPI_ID		U(5119)
46 
47 /* Total number of GICv3.1 ESPIs */
48 #define TOTAL_ESPI_INTR_NUM	(MAX_ESPI_ID - MIN_ESPI_ID + U(1))
49 
50 /* Total number of GICv3.1 SPIs and ESPIs */
51 #define	TOTAL_SHARED_INTR_NUM	(TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM)
52 
53 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
54 #define	IS_SGI_PPI(id)		(((id) <= MAX_PPI_ID)  || \
55 				(((id) >= MIN_EPPI_ID) && \
56 				 ((id) <= MAX_EPPI_ID)))
57 
58 /* SPIs: 32-1019, ESPIs: 4096-5119 */
59 #define	IS_SPI(id)		((((id) >= MIN_SPI_ID)  && \
60 				  ((id) <= MAX_SPI_ID)) || \
61 				 (((id) >= MIN_ESPI_ID) && \
62 				  ((id) <= MAX_ESPI_ID)))
63 #else	/* GICv3 */
64 
65 /* Total number of GICv3 PPIs */
66 #define TOTAL_PRIVATE_INTR_NUM	TOTAL_PCPU_INTR_NUM
67 
68 /* Total number of GICv3 SPIs */
69 #define	TOTAL_SHARED_INTR_NUM	TOTAL_SPI_INTR_NUM
70 
71 /* SGIs: 0-15, PPIs: 16-31 */
72 #define	IS_SGI_PPI(id)		((id) <= MAX_PPI_ID)
73 
74 /* SPIs: 32-1019 */
75 #define	IS_SPI(id)		(((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID))
76 
77 #endif	/* GIC_EXT_INTID */
78 
79 #define GIC_REV(r, p)           ((r << 4) | p)
80 
81 /*******************************************************************************
82  * GICv3 and 3.1 specific Distributor interface register offsets and constants
83  ******************************************************************************/
84 #define GICD_TYPER2		U(0x0c)
85 #define GICD_STATUSR		U(0x10)
86 #define GICD_SETSPI_NSR		U(0x40)
87 #define GICD_CLRSPI_NSR		U(0x48)
88 #define GICD_SETSPI_SR		U(0x50)
89 #define GICD_CLRSPI_SR		U(0x58)
90 #define GICD_IGRPMODR		U(0xd00)
91 #define GICD_IGROUPRE		U(0x1000)
92 #define GICD_ISENABLERE		U(0x1200)
93 #define GICD_ICENABLERE		U(0x1400)
94 #define GICD_ISPENDRE		U(0x1600)
95 #define GICD_ICPENDRE		U(0x1800)
96 #define GICD_ISACTIVERE		U(0x1a00)
97 #define GICD_ICACTIVERE		U(0x1c00)
98 #define GICD_IPRIORITYRE	U(0x2000)
99 #define GICD_ICFGRE		U(0x3000)
100 #define GICD_IGRPMODRE		U(0x3400)
101 #define GICD_NSACRE		U(0x3600)
102 /*
103  * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID
104  * and n >= 32, making the effective offset as 0x6100
105  */
106 #define GICD_IROUTER		U(0x6000)
107 #define GICD_IROUTERE		U(0x8000)
108 
109 #define GICD_PIDR0_GICV3	U(0xffe0)
110 #define GICD_PIDR1_GICV3	U(0xffe4)
111 #define GICD_PIDR2_GICV3	U(0xffe8)
112 
113 #define IGRPMODR_SHIFT		5
114 
115 /* GICD_CTLR bit definitions */
116 #define CTLR_ENABLE_G1NS_SHIFT		1
117 #define CTLR_ENABLE_G1S_SHIFT		2
118 #define CTLR_ARE_S_SHIFT		4
119 #define CTLR_ARE_NS_SHIFT		5
120 #define CTLR_DS_SHIFT			6
121 #define CTLR_E1NWF_SHIFT		7
122 #define GICD_CTLR_RWP_SHIFT		31
123 
124 #define CTLR_ENABLE_G1NS_MASK		U(0x1)
125 #define CTLR_ENABLE_G1S_MASK		U(0x1)
126 #define CTLR_ARE_S_MASK			U(0x1)
127 #define CTLR_ARE_NS_MASK		U(0x1)
128 #define CTLR_DS_MASK			U(0x1)
129 #define CTLR_E1NWF_MASK			U(0x1)
130 #define GICD_CTLR_RWP_MASK		U(0x1)
131 
132 #define CTLR_ENABLE_G1NS_BIT		BIT_32(CTLR_ENABLE_G1NS_SHIFT)
133 #define CTLR_ENABLE_G1S_BIT		BIT_32(CTLR_ENABLE_G1S_SHIFT)
134 #define CTLR_ARE_S_BIT			BIT_32(CTLR_ARE_S_SHIFT)
135 #define CTLR_ARE_NS_BIT			BIT_32(CTLR_ARE_NS_SHIFT)
136 #define CTLR_DS_BIT			BIT_32(CTLR_DS_SHIFT)
137 #define CTLR_E1NWF_BIT			BIT_32(CTLR_E1NWF_SHIFT)
138 #define GICD_CTLR_RWP_BIT		BIT_32(GICD_CTLR_RWP_SHIFT)
139 
140 /* GICD_IROUTER shifts and masks */
141 #define IROUTER_SHIFT		0
142 #define IROUTER_IRM_SHIFT	31
143 #define IROUTER_IRM_MASK	U(0x1)
144 
145 #define GICV3_IRM_PE		U(0)
146 #define GICV3_IRM_ANY		U(1)
147 
148 #define NUM_OF_DIST_REGS	30
149 
150 /* GICD_TYPER shifts and masks */
151 #define	TYPER_ESPI		U(1 << 8)
152 #define	TYPER_DVIS		U(1 << 18)
153 #define	TYPER_ESPI_RANGE_MASK	U(0x1f)
154 #define	TYPER_ESPI_RANGE_SHIFT	U(27)
155 #define	TYPER_ESPI_RANGE	U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
156 
157 /*******************************************************************************
158  * Common GIC Redistributor interface registers & constants
159  ******************************************************************************/
160 #define GICR_V4_PCPUBASE_SHIFT	0x12
161 #define GICR_V3_PCPUBASE_SHIFT	0x11
162 #define GICR_SGIBASE_OFFSET	U(65536)	/* 64 KB */
163 #define GICR_CTLR		U(0x0)
164 #define GICR_IIDR		U(0x04)
165 #define GICR_TYPER		U(0x08)
166 #define GICR_STATUSR		U(0x10)
167 #define GICR_WAKER		U(0x14)
168 #define GICR_PROPBASER		U(0x70)
169 #define GICR_PENDBASER		U(0x78)
170 #define GICR_IGROUPR0		(GICR_SGIBASE_OFFSET + U(0x80))
171 #define GICR_ISENABLER0		(GICR_SGIBASE_OFFSET + U(0x100))
172 #define GICR_ICENABLER0		(GICR_SGIBASE_OFFSET + U(0x180))
173 #define GICR_ISPENDR0		(GICR_SGIBASE_OFFSET + U(0x200))
174 #define GICR_ICPENDR0		(GICR_SGIBASE_OFFSET + U(0x280))
175 #define GICR_ISACTIVER0		(GICR_SGIBASE_OFFSET + U(0x300))
176 #define GICR_ICACTIVER0		(GICR_SGIBASE_OFFSET + U(0x380))
177 #define GICR_IPRIORITYR		(GICR_SGIBASE_OFFSET + U(0x400))
178 #define GICR_ICFGR0		(GICR_SGIBASE_OFFSET + U(0xc00))
179 #define GICR_ICFGR1		(GICR_SGIBASE_OFFSET + U(0xc04))
180 #define GICR_IGRPMODR0		(GICR_SGIBASE_OFFSET + U(0xd00))
181 #define GICR_NSACR		(GICR_SGIBASE_OFFSET + U(0xe00))
182 
183 #define GICR_IGROUPR		GICR_IGROUPR0
184 #define GICR_ISENABLER		GICR_ISENABLER0
185 #define GICR_ICENABLER		GICR_ICENABLER0
186 #define GICR_ISPENDR		GICR_ISPENDR0
187 #define GICR_ICPENDR		GICR_ICPENDR0
188 #define GICR_ISACTIVER		GICR_ISACTIVER0
189 #define GICR_ICACTIVER		GICR_ICACTIVER0
190 #define GICR_ICFGR		GICR_ICFGR0
191 #define GICR_IGRPMODR		GICR_IGRPMODR0
192 
193 /* GICR_CTLR bit definitions */
194 #define GICR_CTLR_UWP_SHIFT	31
195 #define GICR_CTLR_UWP_MASK	U(0x1)
196 #define GICR_CTLR_UWP_BIT	BIT_32(GICR_CTLR_UWP_SHIFT)
197 #define GICR_CTLR_DPG1S_SHIFT	26
198 #define GICR_CTLR_DPG1S_MASK	U(0x1)
199 #define GICR_CTLR_DPG1S_BIT	BIT_32(GICR_CTLR_DPG1S_SHIFT)
200 #define GICR_CTLR_DPG1NS_SHIFT	25
201 #define GICR_CTLR_DPG1NS_MASK	U(0x1)
202 #define GICR_CTLR_DPG1NS_BIT	BIT_32(GICR_CTLR_DPG1NS_SHIFT)
203 #define GICR_CTLR_DPG0_SHIFT	24
204 #define GICR_CTLR_DPG0_MASK	U(0x1)
205 #define GICR_CTLR_DPG0_BIT	BIT_32(GICR_CTLR_DPG0_SHIFT)
206 #define GICR_CTLR_RWP_SHIFT	3
207 #define GICR_CTLR_RWP_MASK	U(0x1)
208 #define GICR_CTLR_RWP_BIT	BIT_32(GICR_CTLR_RWP_SHIFT)
209 #define GICR_CTLR_EN_LPIS_BIT	BIT_32(0)
210 
211 /* GICR_WAKER bit definitions */
212 #define WAKER_CA_SHIFT		2
213 #define WAKER_PS_SHIFT		1
214 
215 #define WAKER_CA_MASK		U(0x1)
216 #define WAKER_PS_MASK		U(0x1)
217 
218 #define WAKER_CA_BIT		BIT_32(WAKER_CA_SHIFT)
219 #define WAKER_PS_BIT		BIT_32(WAKER_PS_SHIFT)
220 
221 /* GICR_TYPER bit definitions */
222 #define TYPER_AFF_VAL_SHIFT	32
223 #define TYPER_PROC_NUM_SHIFT	8
224 #define TYPER_LAST_SHIFT	4
225 #define TYPER_VLPI_SHIFT	1
226 
227 #define TYPER_AFF_VAL_MASK	U(0xffffffff)
228 #define TYPER_PROC_NUM_MASK	U(0xffff)
229 #define TYPER_LAST_MASK		U(0x1)
230 
231 #define TYPER_LAST_BIT		BIT_32(TYPER_LAST_SHIFT)
232 #define TYPER_VLPI_BIT		BIT_32(TYPER_VLPI_SHIFT)
233 
234 #define TYPER_PPI_NUM_SHIFT	U(27)
235 #define TYPER_PPI_NUM_MASK	U(0x1f)
236 
237 /* GICR_IIDR bit definitions */
238 #define IIDR_PRODUCT_ID_MASK	U(0xff)
239 #define IIDR_VARIANT_MASK	U(0xf)
240 #define IIDR_REV_MASK		U(0xf)
241 #define IIDR_IMPLEMENTER_MASK	U(0xfff)
242 #define IIDR_PRODUCT_ID_SHIFT	24
243 #define IIDR_VARIANT_SHIFT	16
244 #define IIDR_REV_SHIFT		12
245 #define IIDR_IMPLEMENTER_SHIFT	0
246 #define IIDR_PRODUCT_ID_BIT	BIT_32(IIDR_PRODUCT_ID_SHIFT)
247 #define IIDR_VARIANT_BIT	BIT_32(IIDR_VARIANT_SHIFT)
248 #define IIDR_REV_BIT		BIT_32(IIDR_REVISION_SHIFT)
249 #define IIDR_IMPLEMENTER_BIT	BIT_32(IIDR_IMPLEMENTER_SHIFT)
250 
251 #define IIDR_MODEL_MASK		(IIDR_PRODUCT_ID_MASK << IIDR_PRODUCT_ID_SHIFT | \
252 				 IIDR_IMPLEMENTER_MASK << IIDR_IMPLEMENTER_SHIFT)
253 
254 #define GIC_PRODUCT_ID_GIC600	U(0x2)
255 #define GIC_PRODUCT_ID_GIC600AE	U(0x3)
256 #define GIC_PRODUCT_ID_GIC700	U(0x4)
257 
258 /*
259  * Note that below revisions and variants definations are as per GIC600/GIC600AE
260  * specification.
261  */
262 #define GIC_REV_P0		U(0x1)
263 #define GIC_REV_P1		U(0x3)
264 #define GIC_REV_P2		U(0x4)
265 #define GIC_REV_P3		U(0x5)
266 #define GIC_REV_P4		U(0x6)
267 #define GIC_REV_P6		U(0x7)
268 
269 #define GIC_VARIANT_R0		U(0x0)
270 #define GIC_VARIANT_R1		U(0x1)
271 #define GIC_VARIANT_R2		U(0x2)
272 
273 /*******************************************************************************
274  * GICv3 and 3.1 CPU interface registers & constants
275  ******************************************************************************/
276 /* ICC_SRE bit definitions */
277 #define ICC_SRE_EN_BIT		BIT_32(3)
278 #define ICC_SRE_DIB_BIT		BIT_32(2)
279 #define ICC_SRE_DFB_BIT		BIT_32(1)
280 #define ICC_SRE_SRE_BIT		BIT_32(0)
281 
282 /* ICC_IGRPEN1_EL3 bit definitions */
283 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT	0
284 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT	1
285 
286 #define IGRPEN1_EL3_ENABLE_G1NS_BIT	BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
287 #define IGRPEN1_EL3_ENABLE_G1S_BIT	BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
288 
289 /* ICC_IGRPEN0_EL1 bit definitions */
290 #define IGRPEN1_EL1_ENABLE_G0_SHIFT	0
291 #define IGRPEN1_EL1_ENABLE_G0_BIT	BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
292 
293 /* ICC_HPPIR0_EL1 bit definitions */
294 #define HPPIR0_EL1_INTID_SHIFT		0
295 #define HPPIR0_EL1_INTID_MASK		U(0xffffff)
296 
297 /* ICC_HPPIR1_EL1 bit definitions */
298 #define HPPIR1_EL1_INTID_SHIFT		0
299 #define HPPIR1_EL1_INTID_MASK		U(0xffffff)
300 
301 /* ICC_IAR0_EL1 bit definitions */
302 #define IAR0_EL1_INTID_SHIFT		0
303 #define IAR0_EL1_INTID_MASK		U(0xffffff)
304 
305 /* ICC_IAR1_EL1 bit definitions */
306 #define IAR1_EL1_INTID_SHIFT		0
307 #define IAR1_EL1_INTID_MASK		U(0xffffff)
308 
309 /* ICC SGI macros */
310 #define SGIR_TGT_MASK			ULL(0xffff)
311 #define SGIR_AFF1_SHIFT			16
312 #define SGIR_INTID_SHIFT		24
313 #define SGIR_INTID_MASK			ULL(0xf)
314 #define SGIR_AFF2_SHIFT			32
315 #define SGIR_IRM_SHIFT			40
316 #define SGIR_IRM_MASK			ULL(0x1)
317 #define SGIR_AFF3_SHIFT			48
318 #define SGIR_AFF_MASK			ULL(0xff)
319 
320 #define SGIR_IRM_TO_AFF			U(0)
321 
322 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt)	\
323 	((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) |	\
324 	 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) |	\
325 	 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) |	\
326 	 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) |		\
327 	 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) |		\
328 	 ((_tgt) & SGIR_TGT_MASK))
329 
330 /*****************************************************************************
331  * GICv3 and 3.1 ITS registers and constants
332  *****************************************************************************/
333 #define GITS_CTLR			U(0x0)
334 #define GITS_IIDR			U(0x4)
335 #define GITS_TYPER			U(0x8)
336 #define GITS_CBASER			U(0x80)
337 #define GITS_CWRITER			U(0x88)
338 #define GITS_CREADR			U(0x90)
339 #define GITS_BASER			U(0x100)
340 
341 /* GITS_CTLR bit definitions */
342 #define GITS_CTLR_ENABLED_BIT		BIT_32(0)
343 #define GITS_CTLR_QUIESCENT_BIT		BIT_32(1)
344 
345 #define GITS_TYPER_VSGI			BIT_64(39)
346 
347 #ifndef __ASSEMBLER__
348 
349 #include <stdbool.h>
350 #include <stdint.h>
351 
352 #include <arch_helpers.h>
353 #include <common/interrupt_props.h>
354 #include <drivers/arm/gic_common.h>
355 #include <lib/utils_def.h>
356 
357 typedef enum {
358 	GICV3_G1S,
359 	GICV3_G1NS,
360 	GICV3_G0
361 } gicv3_irq_group_t;
362 
gicv3_redist_size(uint64_t typer_val)363 static inline uintptr_t gicv3_redist_size(uint64_t typer_val)
364 {
365 #if GIC_ENABLE_V4_EXTN
366 	if ((typer_val & TYPER_VLPI_BIT) != 0U) {
367 		return 1U << GICR_V4_PCPUBASE_SHIFT;
368 	} else {
369 		return 1U << GICR_V3_PCPUBASE_SHIFT;
370 	}
371 #else
372 	return 1U << GICR_V3_PCPUBASE_SHIFT;
373 #endif
374 }
375 
376 unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame);
377 
gicv3_is_intr_id_special_identifier(unsigned int id)378 static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
379 {
380 	return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);
381 }
382 
383 /*******************************************************************************
384  * Helper GICv3 and 3.1 macros for SEL1
385  ******************************************************************************/
gicv3_acknowledge_interrupt_sel1(void)386 static inline uint32_t gicv3_acknowledge_interrupt_sel1(void)
387 {
388 	return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK;
389 }
390 
gicv3_get_pending_interrupt_id_sel1(void)391 static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
392 {
393 	return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
394 }
395 
gicv3_end_of_interrupt_sel1(unsigned int id)396 static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
397 {
398 	/*
399 	 * Interrupt request deassertion from peripheral to GIC happens
400 	 * by clearing interrupt condition by a write to the peripheral
401 	 * register. It is desired that the write transfer is complete
402 	 * before the core tries to change GIC state from 'AP/Active' to
403 	 * a new state on seeing 'EOI write'.
404 	 * Since ICC interface writes are not ordered against Device
405 	 * memory writes, a barrier is required to ensure the ordering.
406 	 * The dsb will also ensure *completion* of previous writes with
407 	 * DEVICE nGnRnE attribute.
408 	 */
409 	dsbishst();
410 	write_icc_eoir1_el1(id);
411 }
412 
413 /*******************************************************************************
414  * Helper GICv3 macros for EL3
415  ******************************************************************************/
gicv3_acknowledge_interrupt(void)416 static inline uint32_t gicv3_acknowledge_interrupt(void)
417 {
418 	return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK;
419 }
420 
gicv3_end_of_interrupt(unsigned int id)421 static inline void gicv3_end_of_interrupt(unsigned int id)
422 {
423 	/*
424 	 * Interrupt request deassertion from peripheral to GIC happens
425 	 * by clearing interrupt condition by a write to the peripheral
426 	 * register. It is desired that the write transfer is complete
427 	 * before the core tries to change GIC state from 'AP/Active' to
428 	 * a new state on seeing 'EOI write'.
429 	 * Since ICC interface writes are not ordered against Device
430 	 * memory writes, a barrier is required to ensure the ordering.
431 	 * The dsb will also ensure *completion* of previous writes with
432 	 * DEVICE nGnRnE attribute.
433 	 */
434 	dsbishst();
435 	return write_icc_eoir0_el1(id);
436 }
437 
438 /*
439  * This macro returns the total number of GICD/GICR registers corresponding to
440  * the register name
441  */
442 #define GICD_NUM_REGS(reg_name)	\
443 	DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT))
444 
445 #define GICR_NUM_REGS(reg_name)	\
446 	DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT))
447 
448 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
449 #define INT_ID_MASK	U(0xffffff)
450 
451 /*******************************************************************************
452  * This structure describes some of the implementation defined attributes of the
453  * GICv3 IP. It is used by the platform port to specify these attributes in order
454  * to initialise the GICV3 driver. The attributes are described below.
455  *
456  * The 'gicd_base' field contains the base address of the Distributor interface
457  * programmer's view.
458  *
459  * The 'gicr_base' field contains the base address of the Re-distributor
460  * interface programmer's view.
461  *
462  * The 'interrupt_props' field is a pointer to an array that enumerates secure
463  * interrupts and their properties. If this field is not NULL, both
464  * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
465  *
466  * The 'interrupt_props_num' field contains the number of entries in the
467  * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num'
468  * and 'g1s_interrupt_num' are ignored.
469  *
470  * The 'rdistif_num' field contains the number of Redistributor interfaces the
471  * GIC implements. This is equal to the number of CPUs or CPU interfaces
472  * instantiated in the GIC.
473  *
474  * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for
475  * storing the base address of the Redistributor interface frame of each CPU in
476  * the system. The size of the array = 'rdistif_num'. The base addresses are
477  * detected during driver initialisation.
478  *
479  * The 'mpidr_to_core_pos' field is a pointer to a hash function which the
480  * driver will use to convert an MPIDR value to a linear core index. This index
481  * will be used for accessing the 'rdistif_base_addrs' array. This is an
482  * optional field. A GICv3 implementation maps each MPIDR to a linear core index
483  * as well. This mapping can be found by reading the "Affinity Value" and
484  * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
485  * "Processor Numbers" are suitable to index into an array to access core
486  * specific information. If this not the case, the platform port must provide a
487  * hash function. Otherwise, the "Processor Number" field will be used to access
488  * the array elements.
489  ******************************************************************************/
490 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
491 
492 typedef struct gicv3_driver_data {
493 	uintptr_t gicd_base;
494 	uintptr_t gicr_base;
495 	const interrupt_prop_t *interrupt_props;
496 	unsigned int interrupt_props_num;
497 	unsigned int rdistif_num;
498 	uintptr_t *rdistif_base_addrs;
499 	mpidr_hash_fn mpidr_to_core_pos;
500 } gicv3_driver_data_t;
501 
502 typedef struct gicv3_redist_ctx {
503 	/* 64 bits registers */
504 	uint64_t gicr_propbaser;
505 	uint64_t gicr_pendbaser;
506 
507 	/* 32 bits registers */
508 	uint32_t gicr_ctlr;
509 	uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)];
510 	uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)];
511 	uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)];
512 	uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)];
513 	uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
514 	uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)];
515 	uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)];
516 	uint32_t gicr_nsacr;
517 } gicv3_redist_ctx_t;
518 
519 typedef struct gicv3_dist_ctx {
520 	/* 64 bits registers */
521 	uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM];
522 
523 	/* 32 bits registers */
524 	uint32_t gicd_ctlr;
525 	uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
526 	uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
527 	uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
528 	uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
529 	uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
530 	uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
531 	uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
532 	uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
533 } gicv3_dist_ctx_t;
534 
535 typedef struct gicv3_its_ctx {
536 	/* 64 bits registers */
537 	uint64_t gits_cbaser;
538 	uint64_t gits_cwriter;
539 	uint64_t gits_baser[8];
540 
541 	/* 32 bits registers */
542 	uint32_t gits_ctlr;
543 } gicv3_its_ctx_t;
544 
545 /*******************************************************************************
546  * GICv3 EL3 driver API
547  ******************************************************************************/
548 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
549 int gicv3_rdistif_probe(const uintptr_t gicr_frame);
550 void gicv3_distif_init(void);
551 void gicv3_rdistif_init(unsigned int proc_num);
552 void gicv3_rdistif_on(unsigned int proc_num);
553 void gicv3_rdistif_off(unsigned int proc_num);
554 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame);
555 void gicv3_cpuif_enable(unsigned int proc_num);
556 void gicv3_cpuif_disable(unsigned int proc_num);
557 unsigned int gicv3_get_pending_interrupt_type(void);
558 unsigned int gicv3_get_pending_interrupt_id(void);
559 unsigned int gicv3_get_interrupt_group(unsigned int id,
560 					  unsigned int proc_num);
561 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
562 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
563 /*
564  * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
565  * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
566  * implementation-defined sequence is needed at these steps, an empty function
567  * can be provided.
568  */
569 void gicv3_distif_post_restore(unsigned int proc_num);
570 void gicv3_distif_pre_save(unsigned int proc_num);
571 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
572 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
573 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
574 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
575 
576 unsigned int gicv3_get_running_priority(void);
577 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num);
578 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num);
579 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
580 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
581 		unsigned int priority);
582 void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num,
583 		unsigned int group);
584 void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group,
585 					 u_register_t target);
586 void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
587 		u_register_t mpidr);
588 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
589 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
590 unsigned int gicv3_set_pmr(unsigned int mask);
591 unsigned int gicv3_deactivate_priority(unsigned int mask);
592 
593 void gicv3_get_component_prodid_rev(const uintptr_t gicd_base,
594 				    unsigned int *gic_prod_id,
595 				    uint8_t *gic_rev);
596 void gicv3_check_erratas_applies(const uintptr_t gicd_base);
597 #if GIC600_ERRATA_WA_2384374
598 void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base);
599 #else
gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base)600 static inline void gicv3_apply_errata_wa_2384374(const uintptr_t gicr_base)
601 {
602 }
603 #endif /* GIC600_ERRATA_WA_2384374 */
604 
605 #endif /* __ASSEMBLER__ */
606 #endif /* GICV3_H */
607