1 /*
2  * Copyright 2020 Broadcom
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
8 #define ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
9 
10 #include <zephyr/types.h>
11 #include <device.h>
12 
13 /*
14  * GIC Register Interface Base Addresses
15  */
16 
17 #define GIC_RDIST_BASE	DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
18 
19 /* SGI base is at 64K offset from Redistributor */
20 #define GICR_SGI_BASE_OFF		0x10000
21 
22 /* GICR registers offset from RD_base(n) */
23 #define GICR_CTLR			0x0000
24 #define GICR_IIDR			0x0004
25 #define GICR_TYPER			0x0008
26 #define GICR_STATUSR			0x0010
27 #define GICR_WAKER			0x0014
28 
29 /* Register bit definations */
30 
31 /* GICD_CTLR Interrupt group definitions */
32 #define GICD_CTLR_ENABLE_G0		0
33 #define GICD_CTLR_ENABLE_G1NS		1
34 #define GICD_CTLR_ENABLE_G1S		2
35 #define GICD_CTRL_ARE_S			4
36 #define GICD_CTRL_ARE_NS		5
37 #define GICD_CTRL_NS			6
38 #define GICD_CGRL_E1NWF			7
39 
40 /* GICD_CTLR Register write progress bit */
41 #define GICD_CTLR_RWP			31
42 
43 /* GICR_CTLR */
44 #define GICR_CTLR_RWP			3
45 
46 /* GICR_WAKER */
47 #define GICR_WAKER_PS			1
48 #define GICR_WAKER_CA			2
49 
50 /* GITCD_IROUTER */
51 #define GIC_DIST_IROUTER		0x6000
52 #define IROUTER(base, n)		(base + GIC_DIST_IROUTER + (n) * 8)
53 
54 #endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ */
55