1 /* 2 * Copyright (c) 2020 PHYTEC Messtechnik GmbH 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ 8 #define ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ 9 10 #define GD7965_CMD_PSR 0x00 11 #define GD7965_CMD_PWR 0x01 12 #define GD7965_CMD_POF 0x02 13 #define GD7965_CMD_PFS 0x03 14 #define GD7965_CMD_PON 0x04 15 #define GD7965_CMD_PMES 0x05 16 #define GD7965_CMD_BTST 0x06 17 #define GD7965_CMD_DSLP 0x07 18 #define GD7965_CMD_DTM1 0x10 19 #define GD7965_CMD_DSP 0x11 20 #define GD7965_CMD_DRF 0x12 21 #define GD7965_CMD_DTM2 0x13 22 #define GD7965_CMD_DUSPI 0x15 23 #define GD7965_CMD_AUTO 0x17 24 #define GD7965_CMD_LUTOPT 0x2A 25 #define GD7965_CMD_KWOPT 0x2B 26 #define GD7965_CMD_PLL 0x30 27 #define GD7965_CMD_TSC 0x40 28 #define GD7965_CMD_TSE 0x41 29 #define GD7965_CMD_TSW 0x42 30 #define GD7965_CMD_TSR 0x43 31 #define GD7965_CMD_PBC 0x44 32 #define GD7965_CMD_CDI 0x50 33 #define GD7965_CMD_LPD 0x51 34 #define GD7965_CMD_EVS 0x52 35 #define GD7965_CMD_TCON 0x60 36 #define GD7965_CMD_TRES 0x61 37 #define GD7965_CMD_GSST 0x65 38 #define GD7965_CMD_REV 0x70 39 #define GD7965_CMD_FLG 0x71 40 #define GD7965_CMD_AMV 0x80 41 #define GD7965_CMD_VV 0x81 42 #define GD7965_CMD_VDCS 0x82 43 #define GD7965_CMD_PTL 0x90 44 #define GD7965_CMD_PTIN 0x91 45 #define GD7965_CMD_PTOUT 0x92 46 #define GD7965_CMD_PGM 0xA0 47 #define GD7965_CMD_APG 0xA1 48 #define GD7965_CMD_ROTP 0xA2 49 #define GD7965_CMD_CCSET 0xE0 50 #define GD7965_CMD_PWS 0xE3 51 #define GD7965_CMD_LVSEL 0xE4 52 #define GD7965_CMD_TSSET 0xE5 53 #define GD7965_CMD_TSBDRY 0xE7 54 55 #define GD7965_PSR_REG BIT(5) 56 #define GD7965_PSR_KW_R BIT(4) 57 #define GD7965_PSR_UD BIT(3) 58 #define GD7965_PSR_SHL BIT(2) 59 #define GD7965_PSR_SHD BIT(1) 60 #define GD7965_PSR_RST BIT(0) 61 62 #define GD7965_AUTO_PON_DRF_POF 0xA5 63 #define GD7965_AUTO_PON_DRF_POF_DSLP 0xA7 64 65 #define GD7965_CDI_REG_LENGTH 2U 66 #define GD7965_CDI_BDZ_DDX_IDX 0 67 #define GD7965_CDI_CDI_IDX 1 68 #define GD7965_CDI_BDZ BIT(7) 69 #define GD7965_CDI_BDV1 BIT(5) 70 #define GD7965_CDI_BDV0 BIT(4) 71 #define GD7965_CDI_N2OCP BIT(3) 72 #define GD7965_CDI_DDX1 BIT(1) 73 #define GD7965_CDI_DDX0 BIT(0) 74 75 #define GD7965_TRES_REG_LENGTH 4U 76 #define GD7965_TRES_HRES_IDX 0 77 #define GD7965_TRES_VRES_IDX 2 78 79 #define GD7965_PTL_REG_LENGTH 9U 80 #define GD7965_PTL_HRST_IDX 0 81 #define GD7965_PTL_HRED_IDX 2 82 #define GD7965_PTL_VRST_IDX 4 83 #define GD7965_PTL_VRED_IDX 6 84 #define GD7965_PTL_PT_SCAN BIT(0) 85 86 /* Time constants in ms */ 87 #define GD7965_RESET_DELAY 10U 88 #define GD7965_PON_DELAY 100U 89 #define GD7965_BUSY_DELAY 1U 90 91 #endif /* ZEPHYR_DRIVERS_DISPLAY_GD7965_REGS_H_ */ 92
