1 /* 2 * Copyright (c) 2021 Teslabs Engineering S.L. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * Gigadevice SoC specific helpers for pinctrl driver 10 */ 11 12 #ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ 13 #define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ 14 15 #include <zephyr/devicetree.h> 16 #include <zephyr/types.h> 17 18 #ifdef CONFIG_PINCTRL_GD32_AF 19 #include <dt-bindings/pinctrl/gd32-af.h> 20 #else 21 #include <dt-bindings/pinctrl/gd32-afio.h> 22 #endif /* CONFIG_PINCTRL_GD32_AF */ 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /** @cond INTERNAL_HIDDEN */ 29 30 /** @brief Type for GD32 pin. 31 * 32 * Bits (AF model): 33 * - 0-12: GD32_PINMUX_AF bit field. 34 * - 13-25: Reserved. 35 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG). 36 * 37 * Bits (AFIO model): 38 * - 0-19: GD32_PINMUX_AFIO bit field. 39 * - 20-25: Reserved. 40 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG). 41 */ 42 typedef uint32_t pinctrl_soc_pin_t; 43 44 /** 45 * @brief Utility macro to initialize each pin. 46 * 47 * @param node_id Node identifier. 48 * @param prop Property name. 49 * @param idx Property entry index. 50 */ 51 #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ 52 (DT_PROP_BY_IDX(node_id, prop, idx) | \ 53 ((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up)) \ 54 << GD32_PUPD_POS) | \ 55 ((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down)) \ 56 << GD32_PUPD_POS) | \ 57 ((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain)) \ 58 << GD32_OTYPE_POS) | \ 59 (DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)), 60 61 /** 62 * @brief Utility macro to initialize state pins contained in a given property. 63 * 64 * @param node_id Node identifier. 65 * @param prop Property name describing state pins. 66 */ 67 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 68 {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 69 DT_FOREACH_PROP_ELEM, pinmux, \ 70 Z_PINCTRL_STATE_PIN_INIT)} 71 72 /** @endcond */ 73 74 /** 75 * @name GD32 PUPD (values match the ones in the HAL for AF model). 76 * @{ 77 */ 78 79 /** No pull-up/down */ 80 #define GD32_PUPD_NONE 0U 81 /** Pull-up */ 82 #define GD32_PUPD_PULLUP 1U 83 /** Pull-down */ 84 #define GD32_PUPD_PULLDOWN 2U 85 86 /** @} */ 87 88 /** 89 * @name GD32 OTYPE (values match the ones in the HAL for AF model). 90 * @{ 91 */ 92 93 /** Push-pull */ 94 #define GD32_OTYPE_PP 0U 95 /** Open-drain */ 96 #define GD32_OTYPE_OD 1U 97 98 /** @} */ 99 100 /** 101 * @name GD32 OSPEED (values match the ones in the HAL for AF model, mode minus 102 * one for AFIO model). 103 * @{ 104 */ 105 106 #ifdef CONFIG_PINCTRL_GD32_AF 107 /** Maximum 2MHz */ 108 #define GD32_OSPEED_2MHZ 0U 109 #if defined(CONFIG_SOC_SERIES_GD32F3X0) || \ 110 defined(CONFIG_SOC_SERIES_GD32A50X) || \ 111 defined(CONFIG_SOC_SERIES_GD32L23X) 112 /** Maximum 10MHz */ 113 #define GD32_OSPEED_10MHZ 1U 114 /** Maximum 50MHz */ 115 #define GD32_OSPEED_50MHZ 3U 116 #else 117 /** Maximum 25MHz */ 118 #define GD32_OSPEED_25MHZ 1U 119 /** Maximum 50MHz */ 120 #define GD32_OSPEED_50MHZ 2U 121 /** Maximum speed */ 122 #define GD32_OSPEED_MAX 3U 123 #endif 124 125 #else /* CONFIG_PINCTRL_GD32_AF */ 126 /** Maximum 10MHz */ 127 #define GD32_OSPEED_10MHZ 0U 128 /** Maximum 2MHz */ 129 #define GD32_OSPEED_2MHZ 1U 130 /** Maximum 50MHz */ 131 #define GD32_OSPEED_50MHZ 2U 132 /** Maximum speed */ 133 #define GD32_OSPEED_MAX 3U 134 #endif /* CONFIG_PINCTRL_GD32_AF */ 135 136 /** @} */ 137 138 /** 139 * @name GD32 pin configuration bit field mask and positions. 140 * @anchor GD32_PINCFG 141 * 142 * Fields: 143 * 144 * - 31..29: Pull-up/down 145 * - 28: Output type 146 * - 27..26: Output speed 147 * 148 * @{ 149 */ 150 151 /** PUPD field mask. */ 152 #define GD32_PUPD_MSK 0x3U 153 /** PUPD field position. */ 154 #define GD32_PUPD_POS 29U 155 /** OTYPE field mask. */ 156 #define GD32_OTYPE_MSK 0x1U 157 /** OTYPE field position. */ 158 #define GD32_OTYPE_POS 28U 159 /** OSPEED field mask. */ 160 #define GD32_OSPEED_MSK 0x3U 161 /** OSPEED field position. */ 162 #define GD32_OSPEED_POS 26U 163 164 /** @} */ 165 166 /** 167 * Obtain PUPD field from pinctrl_soc_pin_t configuration. 168 * 169 * @param pincfg pinctrl_soc_pin_t bit field value. 170 */ 171 #define GD32_PUPD_GET(pincfg) \ 172 (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK) 173 174 /** 175 * Obtain OTYPE field from pinctrl_soc_pin_t configuration. 176 * 177 * @param pincfg pinctrl_soc_pin_t bit field value. 178 */ 179 #define GD32_OTYPE_GET(pincfg) \ 180 (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK) 181 182 /** 183 * Obtain OSPEED field from pinctrl_soc_pin_t configuration. 184 * 185 * @param pincfg pinctrl_soc_pin_t bit field value. 186 */ 187 #define GD32_OSPEED_GET(pincfg) \ 188 (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK) 189 190 #ifdef __cplusplus 191 } 192 #endif 193 194 #endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ */ 195
