1 /** 2 * \file 3 * 4 * \brief Component description for GCLK 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_GCLK_COMPONENT_ 30 #define _SAML21_GCLK_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR GCLK */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_GCLK Generic Clock Generator */ 36 /*@{*/ 37 38 #define GCLK_U2122 39 #define REV_GCLK 0x111 40 41 /* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 47 } bit; /*!< Structure used for bit access */ 48 uint8_t reg; /*!< Type used for register access */ 49 } GCLK_CTRLA_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */ 53 #define GCLK_CTRLA_RESETVALUE _U(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */ 54 55 #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ 56 #define GCLK_CTRLA_SWRST (_U(0x1) << GCLK_CTRLA_SWRST_Pos) 57 #define GCLK_CTRLA_MASK _U(0x01) /**< \brief (GCLK_CTRLA) MASK Register */ 58 59 /* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */ 64 uint32_t :1; /*!< bit: 1 Reserved */ 65 uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */ 66 uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */ 67 uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */ 68 uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */ 69 uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */ 70 uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */ 71 uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */ 72 uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */ 73 uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */ 74 uint32_t :21; /*!< bit: 11..31 Reserved */ 75 } bit; /*!< Structure used for bit access */ 76 struct { 77 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 78 uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control x Synchronization Busy bits */ 79 uint32_t :21; /*!< bit: 11..31 Reserved */ 80 } vec; /*!< Structure used for vec access */ 81 uint32_t reg; /*!< Type used for register access */ 82 } GCLK_SYNCBUSY_Type; 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 #define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */ 86 #define GCLK_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */ 87 88 #define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */ 89 #define GCLK_SYNCBUSY_SWRST (_U(0x1) << GCLK_SYNCBUSY_SWRST_Pos) 90 #define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */ 91 #define GCLK_SYNCBUSY_GENCTRL0 (1 << GCLK_SYNCBUSY_GENCTRL0_Pos) 92 #define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */ 93 #define GCLK_SYNCBUSY_GENCTRL1 (1 << GCLK_SYNCBUSY_GENCTRL1_Pos) 94 #define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */ 95 #define GCLK_SYNCBUSY_GENCTRL2 (1 << GCLK_SYNCBUSY_GENCTRL2_Pos) 96 #define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */ 97 #define GCLK_SYNCBUSY_GENCTRL3 (1 << GCLK_SYNCBUSY_GENCTRL3_Pos) 98 #define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */ 99 #define GCLK_SYNCBUSY_GENCTRL4 (1 << GCLK_SYNCBUSY_GENCTRL4_Pos) 100 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */ 101 #define GCLK_SYNCBUSY_GENCTRL5 (1 << GCLK_SYNCBUSY_GENCTRL5_Pos) 102 #define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */ 103 #define GCLK_SYNCBUSY_GENCTRL6 (1 << GCLK_SYNCBUSY_GENCTRL6_Pos) 104 #define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */ 105 #define GCLK_SYNCBUSY_GENCTRL7 (1 << GCLK_SYNCBUSY_GENCTRL7_Pos) 106 #define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */ 107 #define GCLK_SYNCBUSY_GENCTRL8 (1 << GCLK_SYNCBUSY_GENCTRL8_Pos) 108 #define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */ 109 #define GCLK_SYNCBUSY_GENCTRL_Msk (_U(0x1FF) << GCLK_SYNCBUSY_GENCTRL_Pos) 110 #define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos)) 111 #define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */ 112 #define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */ 113 #define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */ 114 #define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */ 115 #define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */ 116 #define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */ 117 #define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */ 118 #define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */ 119 #define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */ 120 #define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 121 #define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 122 #define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 123 #define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 124 #define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 125 #define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 126 #define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 127 #define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 128 #define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 129 #define GCLK_SYNCBUSY_MASK _U(0x000007FD) /**< \brief (GCLK_SYNCBUSY) MASK Register */ 130 131 /* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */ 132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 133 typedef union { 134 struct { 135 uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */ 136 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 137 uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */ 138 uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */ 139 uint32_t OOV:1; /*!< bit: 10 Output Off Value */ 140 uint32_t OE:1; /*!< bit: 11 Output Enable */ 141 uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */ 142 uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */ 143 uint32_t :2; /*!< bit: 14..15 Reserved */ 144 uint32_t DIV:16; /*!< bit: 16..31 Division Factor */ 145 } bit; /*!< Structure used for bit access */ 146 uint32_t reg; /*!< Type used for register access */ 147 } GCLK_GENCTRL_Type; 148 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 149 150 #define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ 151 #define GCLK_GENCTRL_RESETVALUE _U(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ 152 153 #define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */ 154 #define GCLK_GENCTRL_SRC_Msk (_U(0xF) << GCLK_GENCTRL_SRC_Pos) 155 #define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)) 156 #define GCLK_GENCTRL_SRC_XOSC_Val _U(0x0) /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ 157 #define GCLK_GENCTRL_SRC_GCLKIN_Val _U(0x1) /**< \brief (GCLK_GENCTRL) Generator input pad */ 158 #define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U(0x2) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ 159 #define GCLK_GENCTRL_SRC_OSCULP32K_Val _U(0x3) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ 160 #define GCLK_GENCTRL_SRC_OSC32K_Val _U(0x4) /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ 161 #define GCLK_GENCTRL_SRC_XOSC32K_Val _U(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ 162 #define GCLK_GENCTRL_SRC_OSC16M_Val _U(0x6) /**< \brief (GCLK_GENCTRL) OSC16M oscillator output */ 163 #define GCLK_GENCTRL_SRC_DFLL48M_Val _U(0x7) /**< \brief (GCLK_GENCTRL) DFLL48M output */ 164 #define GCLK_GENCTRL_SRC_DPLL96M_Val _U(0x8) /**< \brief (GCLK_GENCTRL) DPLL96M output */ 165 #define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) 166 #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) 167 #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) 168 #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) 169 #define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) 170 #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) 171 #define GCLK_GENCTRL_SRC_OSC16M (GCLK_GENCTRL_SRC_OSC16M_Val << GCLK_GENCTRL_SRC_Pos) 172 #define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) 173 #define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos) 174 #define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ 175 #define GCLK_GENCTRL_GENEN (_U(0x1) << GCLK_GENCTRL_GENEN_Pos) 176 #define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ 177 #define GCLK_GENCTRL_IDC (_U(0x1) << GCLK_GENCTRL_IDC_Pos) 178 #define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */ 179 #define GCLK_GENCTRL_OOV (_U(0x1) << GCLK_GENCTRL_OOV_Pos) 180 #define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */ 181 #define GCLK_GENCTRL_OE (_U(0x1) << GCLK_GENCTRL_OE_Pos) 182 #define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */ 183 #define GCLK_GENCTRL_DIVSEL (_U(0x1) << GCLK_GENCTRL_DIVSEL_Pos) 184 #define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */ 185 #define GCLK_GENCTRL_RUNSTDBY (_U(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos) 186 #define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */ 187 #define GCLK_GENCTRL_DIV_Msk (_U(0xFFFF) << GCLK_GENCTRL_DIV_Pos) 188 #define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos)) 189 #define GCLK_GENCTRL_MASK _U(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */ 190 191 /* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */ 192 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 193 typedef union { 194 struct { 195 uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */ 196 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 197 uint32_t CHEN:1; /*!< bit: 6 Channel Enable */ 198 uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */ 199 uint32_t :24; /*!< bit: 8..31 Reserved */ 200 } bit; /*!< Structure used for bit access */ 201 uint32_t reg; /*!< Type used for register access */ 202 } GCLK_PCHCTRL_Type; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */ 206 #define GCLK_PCHCTRL_RESETVALUE _U(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */ 207 208 #define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */ 209 #define GCLK_PCHCTRL_GEN_Msk (_U(0xF) << GCLK_PCHCTRL_GEN_Pos) 210 #define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos)) 211 #define GCLK_PCHCTRL_GEN_GCLK0_Val _U(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */ 212 #define GCLK_PCHCTRL_GEN_GCLK1_Val _U(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */ 213 #define GCLK_PCHCTRL_GEN_GCLK2_Val _U(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */ 214 #define GCLK_PCHCTRL_GEN_GCLK3_Val _U(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */ 215 #define GCLK_PCHCTRL_GEN_GCLK4_Val _U(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */ 216 #define GCLK_PCHCTRL_GEN_GCLK5_Val _U(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */ 217 #define GCLK_PCHCTRL_GEN_GCLK6_Val _U(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */ 218 #define GCLK_PCHCTRL_GEN_GCLK7_Val _U(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */ 219 #define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) 220 #define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) 221 #define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) 222 #define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) 223 #define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) 224 #define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) 225 #define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) 226 #define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) 227 #define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */ 228 #define GCLK_PCHCTRL_CHEN (_U(0x1) << GCLK_PCHCTRL_CHEN_Pos) 229 #define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */ 230 #define GCLK_PCHCTRL_WRTLOCK (_U(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos) 231 #define GCLK_PCHCTRL_MASK _U(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */ 232 233 /** \brief GCLK hardware registers */ 234 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 235 typedef struct { 236 __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ 237 RoReg8 Reserved1[0x3]; 238 __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */ 239 RoReg8 Reserved2[0x18]; 240 __IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */ 241 RoReg8 Reserved3[0x3C]; 242 __IO GCLK_PCHCTRL_Type PCHCTRL[36]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */ 243 } Gclk; 244 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 245 246 /*@}*/ 247 248 #endif /* _SAML21_GCLK_COMPONENT_ */ 249
