1 /**
2  * Copyright (c) 2023 Mr Beam Lasers GmbH.
3  * Copyright (c) 2023 Amrith Venkat Kesavamoorthi <amrith@mr-beam.org>
4  * Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
5  *
6  * SPDX-License-Identifier: Apache-2.0
7  */
8 #ifndef ZEPHYR_DRIVERS_DISPLAY_GC9X01X_H_
9 #define ZEPHYR_DRIVERS_DISPLAY_GC9X01X_H_
10 
11 #include <zephyr/sys/util.h>
12 
13 /* Command registers */
14 #define GC9X01X_CMD_SLPIN     0x10U /* Enter Sleep Mode */
15 #define GC9X01X_CMD_SLPOUT    0x11U /* Exit Sleep Mode */
16 #define GC9X01X_CMD_PTLON     0x12U /* Partial Mode ON */
17 #define GC9X01X_CMD_NORON     0x13U /* Normal Display Mode ON */
18 #define GC9X01X_CMD_INVOFF    0x20U /* Display Inversion OFF */
19 #define GC9X01X_CMD_INVON     0x21U /* Display Inversion ON */
20 #define GC9X01X_CMD_DISPOFF   0x28U /* Display OFF */
21 #define GC9X01X_CMD_DISPON    0x29U /* Display ON */
22 #define GC9X01X_CMD_COLSET    0x2AU /* Column Address Set */
23 #define GC9X01X_CMD_ROWSET    0x2BU /* Row Address Set */
24 #define GC9X01X_CMD_MEMWR     0x2CU /* Memory Write */
25 #define GC9X01X_CMD_PTLAR     0x30U /* Partial Area */
26 #define GC9X01X_CMD_VSCRDEF   0x33U /* Vertical Scrolling Definition */
27 #define GC9X01X_CMD_TEOFF     0x34U /* Tearing Effect Line OFF */
28 #define GC9X01X_CMD_TEON      0x35U /* Tearing Effect Line ON */
29 #define GC9X01X_CMD_MADCTL    0x36U /* Memory Access Control */
30 #define GC9X01X_CMD_VSCRSADD  0x37U /* Vertical Scrolling Start Address */
31 #define GC9X01X_CMD_PIXFMT    0x3AU /* Pixel Format Set */
32 #define GC9X01X_CMD_DFUNCTR   0xB6U /* Display Function Control */
33 #define GC9X01X_CMD_PWRCTRL1  0xC1U /* Power Control 1 */
34 #define GC9X01X_CMD_PWRCTRL2  0xC3U /* Power Control 2 */
35 #define GC9X01X_CMD_PWRCTRL3  0xC4U /* Power Control 3 */
36 #define GC9X01X_CMD_PWRCTRL4  0xC9U /* Power Control 4 */
37 #define GC9X01X_CMD_READID1   0xDAU /* Read ID 1 */
38 #define GC9X01X_CMD_READID2   0xDBU /* Read ID 2 */
39 #define GC9X01X_CMD_READID3   0xDCU /* Read ID 3 */
40 #define GC9X01X_CMD_GAMMA1    0xF0U /* Gamma1 (negative polarity) */
41 #define GC9X01X_CMD_GAMMA2    0xF1U /* Gamma2 */
42 #define GC9X01X_CMD_GAMMA3    0xF2U /* Gamma3  (positive polarity) */
43 #define GC9X01X_CMD_GAMMA4    0xF3U /* Gamma4 */
44 #define GC9X01X_CMD_INREGEN1  0xFEU /* Inter Register Enable 1 */
45 #define GC9X01X_CMD_INREGEN2  0xEFU /* Inter Register Enable 2 */
46 #define GC9X01X_CMD_FRAMERATE 0xE8U /* Frame Rate Control */
47 
48 /* GC9X01X_CMD_MADCTL register fields */
49 #define GC9X01X_MADCTL_VAL_MY  BIT(7U)
50 #define GC9X01X_MADCTL_VAL_MX  BIT(6U)
51 #define GC9X01X_MADCTL_VAL_MV  BIT(5U)
52 #define GC9X01X_MADCTL_VAL_ML  BIT(4U)
53 #define GC9X01X_MADCTL_VAL_BGR BIT(3U)
54 #define GC9X01X_MADCTL_VAL_MH  BIT(2U)
55 
56 /* GC9X01X_CMD_PIXFMT register fields */
57 #define GC9X01X_PIXFMT_VAL_RGB_18_BIT 0x60U
58 #define GC9X01X_PIXFMT_VAL_RGB_16_BIT 0x50U
59 #define GC9X01X_PIXFMT_VAL_MCU_18_BIT 0x06U
60 #define GC9X01X_PIXFMT_VAL_MCU_16_BIT 0x05U
61 
62 /* Duration to enter/exit  sleep mode (see 6.2.3 and 6.4.2 in datasheet) */
63 #define GC9X01X_SLEEP_IN_OUT_DURATION_MS 120
64 
65 /* GC9X01X registers to be intitialized */
66 #define GC9X01X_CMD_PWRCTRL1_LEN  1U
67 #define GC9X01X_CMD_PWRCTRL2_LEN  1U
68 #define GC9X01X_CMD_PWRCTRL3_LEN  1U
69 #define GC9X01X_CMD_PWRCTRL4_LEN  1U
70 #define GC9X01X_CMD_GAMMA1_LEN    6U
71 #define GC9X01X_CMD_GAMMA2_LEN    6U
72 #define GC9X01X_CMD_GAMMA3_LEN    6U
73 #define GC9X01X_CMD_GAMMA4_LEN    6U
74 #define GC9X01X_CMD_FRAMERATE_LEN 1U
75 
76 struct gc9x01x_regs {
77 	uint8_t pwrctrl1[GC9X01X_CMD_PWRCTRL1_LEN];
78 	uint8_t pwrctrl2[GC9X01X_CMD_PWRCTRL2_LEN];
79 	uint8_t pwrctrl3[GC9X01X_CMD_PWRCTRL3_LEN];
80 	uint8_t pwrctrl4[GC9X01X_CMD_PWRCTRL4_LEN];
81 	uint8_t gamma1[GC9X01X_CMD_GAMMA1_LEN];
82 	uint8_t gamma2[GC9X01X_CMD_GAMMA2_LEN];
83 	uint8_t gamma3[GC9X01X_CMD_GAMMA3_LEN];
84 	uint8_t gamma4[GC9X01X_CMD_GAMMA4_LEN];
85 	uint8_t framerate[GC9X01X_CMD_FRAMERATE_LEN];
86 };
87 
88 #define GC9X01X_REGS_INIT(inst)                                                                    \
89 	static const struct gc9x01x_regs gc9x01x_regs_##inst = {                                   \
90 		.pwrctrl1 = DT_INST_PROP(inst, pwrctrl1),                                          \
91 		.pwrctrl2 = DT_INST_PROP(inst, pwrctrl2),                                          \
92 		.pwrctrl3 = DT_INST_PROP(inst, pwrctrl3),                                          \
93 		.pwrctrl4 = DT_INST_PROP(inst, pwrctrl4),                                          \
94 		.gamma1 = DT_INST_PROP(inst, gamma1),                                              \
95 		.gamma2 = DT_INST_PROP(inst, gamma2),                                              \
96 		.gamma3 = DT_INST_PROP(inst, gamma3),                                              \
97 		.gamma4 = DT_INST_PROP(inst, gamma4),                                              \
98 		.framerate = DT_INST_PROP(inst, framerate),                                        \
99 	};
100 
101 #endif /* ZEPHYR_DRIVERS_DISPLAY_GC9X01X_H_ */
102