1 /* 2 * Copyright 2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 /** 8 * @file fxls896x.h 9 * @brief This file contains the FXLS896XAF Accelerometer register definitions, access macros, and 10 * device access functions. 11 */ 12 #ifndef FXLS896X_H_ 13 #define FXLS896X_H_ 14 #include <stddef.h> 15 #include <stdint.h> 16 #include <stdbool.h> 17 /** 18 * @brief The FXLS896x types 19 */ 20 21 /** 22 ** 23 ** @brief The FXLS896x Sensor Internal Register Map. 24 */ 25 enum 26 { 27 FXLS896x_INT_STATUS = 0x00, 28 FXLS896x_TEMP_OUT = 0x01, 29 FXLS896x_VECM_LSB = 0x02, 30 FXLS896x_VECM_MSB = 0x03, 31 FXLS896x_OUT_X_LSB = 0x04, 32 FXLS896x_OUT_X_MSB = 0x05, 33 FXLS896x_OUT_Y_LSB = 0x06, 34 FXLS896x_OUT_Y_MSB = 0x07, 35 FXLS896x_OUT_Z_LSB = 0x08, 36 FXLS896x_OUT_Z_MSB = 0x09, 37 FXLS896x_BUF_STATUS = 0x0B, 38 FXLS896x_BUF_X_LSB = 0x0C, 39 FXLS896x_BUF_X_MSB = 0x0D, 40 FXLS896x_BUF_Y_LSB = 0x0E, 41 FXLS896x_BUF_Y_MSB = 0x0F, 42 FXLS896x_BUF_Z_LSB = 0x10, 43 FXLS896x_BUF_Z_MSB = 0x11, 44 FXLS896x_PROD_REV = 0x12, 45 FXLS896x_WHO_AM_I = 0x13, 46 FXLS896x_SYS_MODE = 0x14, 47 FXLS896x_SENS_CONFIG1 = 0x15, 48 FXLS896x_SENS_CONFIG2 = 0x16, 49 FXLS896x_SENS_CONFIG3 = 0x17, 50 FXLS896x_SENS_CONFIG4 = 0x18, 51 FXLS896x_SENS_CONFIG5 = 0x19, 52 FXLS896x_WAKE_IDLE_LSB = 0x1A, 53 FXLS896x_WAKE_IDLE_MSB = 0x1B, 54 FXLS896x_SLEEP_IDLE_LSB = 0x1C, 55 FXLS896x_SLEEP_IDLE_MSB = 0x1D, 56 FXLS896x_ASLP_COUNT_LSB = 0x1E, 57 FXLS896x_ASLP_COUNT_MSB = 0x1F, 58 FXLS896x_INT_EN = 0x20, 59 FXLS896x_INT_PIN_SEL = 0x21, 60 FXLS896x_OFF_X = 0x22, 61 FXLS896x_OFF_Y = 0x23, 62 FXLS896x_OFF_Z = 0x24, 63 FXLS896x_BUF_CONFIG1 = 0x26, 64 FXLS896x_BUF_CONFIG2 = 0x27, 65 FXLS896x_ORIENT_STATUS = 0x28, 66 FXLS896x_ORIENT_CONFIG = 0x29, 67 FXLS896x_ORIENT_DBCOUNT = 0x2A, 68 FXLS896x_ORIENT_BF_ZCOMP = 0x2B, 69 FXLS896x_ORIENT_THS_REG = 0x2C, 70 FXLS896x_SDCD_INT_SRC1 = 0x2D, 71 FXLS896x_SDCD_INT_SRC2 = 0x2E, 72 FXLS896x_SDCD_CONFIG1 = 0x2F, 73 FXLS896x_SDCD_CONFIG2 = 0x30, 74 FXLS896x_SDCD_OT_DBCNT = 0x31, 75 FXLS896x_SDCD_WT_DBCNT = 0x32, 76 FXLS896x_SDCD_LTHS_LSB = 0x33, 77 FXLS896x_SDCD_LTHS_MSB = 0x34, 78 FXLS896x_SDCD_UTHS_LSB = 0x35, 79 FXLS896x_SDCD_UTHS_MSB = 0x36, 80 FXLS896x_SELF_TEST_CONFIG1 = 0x37, 81 FXLS896x_SELF_TEST_CONFIG2 = 0x38, 82 }; 83 84 #define FXLS896x_DEVICE_ADDRESS_SA0_0 (0x18) /*!< Device Address Value. */ 85 #define FXLS896x_DEVICE_ADDRESS_SA0_1 (0x19) /*!< Device Address Value. */ 86 #define FXLS8962_WHOAMI_VALUE (0x62) /*!< Who AM I Value. */ 87 #define FXLS8964_WHOAMI_VALUE (0x84) /*!< Who AM I Value of FXLS8964AF */ 88 #define FXLS8967_WHOAMI_VALUE (0x87) /*!< Who AM I Value of FXLS8967AF */ 89 #define FXLS8968_WHOAMI_VALUE (0x88) /*!< Who AM I Value of FXLS8968CF */ 90 #define FXLS8974_WHOAMI_VALUE (0x86) /*!< Who AM I Value of FXLS8974CF */ 91 #define FXLS8961_WHOAMI_VALUE (0x81) /*!< Who AM I Value of FXLS8961AF */ 92 #define FXLS8971_WHOAMI_VALUE (0x83) /*!< Who AM I Value of FXLS8971CF */ 93 #define FXLS896x_TBOOT_MAX 20 /*!< Maximum safe value for TBOOT1/2 in ms (1ms, 17.7ms)=~20ms. */ 94 95 /*-------------------------------- 96 ** Register: INT_STATUS 97 ** Enum: FXLS896x_INT_STATUS 98 ** -- 99 ** Offset : 0x00 Interrupt and system status event flags. 100 ** ------------------------------*/ 101 typedef union 102 { 103 struct 104 { 105 uint8_t src_boot : 1; /* System boot complete event flag. */ 106 107 uint8_t src_aslp : 1; /* Auto-Wake/Sleep event status flag. */ 108 109 uint8_t src_orient : 1; /* Orientation change event flag. */ 110 111 uint8_t src_sdcd_wt : 1; /* SDCD within thresholds condition event flag. */ 112 113 uint8_t src_sdcd_ot : 1; /* SDCD outside of threshold condition event flag. */ 114 115 uint8_t src_buf : 1;/* Output data buffer status event flag. */ 116 117 uint8_t src_ovf : 1; /* Output data overflow event flag. */ 118 119 uint8_t src_drdy : 1; /* Output data ready event flag. */ 120 121 } b; 122 uint8_t w; 123 } FXLS896x_INT_STATUS_t; 124 125 /* 126 ** INT_STATUS - Bit field mask definitions 127 */ 128 #define FXLS896x_INT_STATUS_SRC_BOOT_MASK ((uint8_t)0x01) 129 #define FXLS896x_INT_STATUS_SRC_BOOT_SHIFT ((uint8_t)0) 130 131 #define FXLS896x_INT_STATUS_SRC_ASLP_MASK ((uint8_t)0x02) 132 #define FXLS896x_INT_STATUS_SRC_ASLP_SHIFT ((uint8_t)1) 133 134 #define FXLS896x_INT_STATUS_SRC_ORIENT_MASK ((uint8_t)0x04) 135 #define FXLS896x_INT_STATUS_SRC_ORIENT_SHIFT ((uint8_t)2) 136 137 #define FXLS896x_INT_STATUS_SRC_SDCD_WT_MASK ((uint8_t)0x08) 138 #define FXLS896x_INT_STATUS_SRC_SDCD_WT_SHIFT ((uint8_t)3) 139 140 #define FXLS896x_INT_STATUS_SRC_SDCD_OT_MASK ((uint8_t)0x10) 141 #define FXLS896x_INT_STATUS_SRC_SDCD_OT_SHIFT ((uint8_t)4) 142 143 #define FXLS896x_INT_STATUS_SRC_BUF_MASK ((uint8_t)0x20) 144 #define FXLS896x_INT_STATUS_SRC_BUF_SHIFT ((uint8_t)5) 145 146 #define FXLS896x_INT_STATUS_SRC_OVF_MASK ((uint8_t)0x40) 147 #define FXLS896x_INT_STATUS_SRC_OVF_SHIFT ((uint8_t)6) 148 149 #define FXLS896x_INT_STATUS_SRC_DRDY_MASK ((uint8_t)0x80) 150 #define FXLS896x_INT_STATUS_SRC_DRDY_SHIFT ((uint8_t)7) 151 152 /*------------------------------*/ 153 154 /*-------------------------------- 155 ** Register: TEMP_OUT 156 ** Enum: FXLS896x_TEMP_OUT 157 ** -- 158 ** Offset : 0x01 Temperature output data. 159 ** ------------------------------*/ 160 typedef uint8_t FXLS896x_TEMP_OUT_t; 161 162 /*-------------------------------- 163 ** Register: VECM_LSB 164 ** Enum: FXLS896x_VECM_LSB 165 ** -- 166 ** Offset : 0x02 12-bit unsigned vector magnitude LSB. 167 ** ------------------------------*/ 168 typedef uint8_t FXLS896x_VECM_LSB_t; 169 170 /*-------------------------------- 171 ** Register: VECM_MSB 172 ** Enum: FXLS896x_VECM_MSB 173 ** -- 174 ** Offset : 0x03 12-bit unsigned vector magnitude MSB. 175 ** ------------------------------*/ 176 typedef uint8_t FXLS896x_VECM_MSB_t; 177 178 /*-------------------------------- 179 ** Register: OUT_X_LSB 180 ** Enum: FXLS896x_OUT_X_LSB 181 ** -- 182 ** Offset : 0x04 LSB of current 12-bit X-axis accelerometer output data. 183 ** ------------------------------*/ 184 typedef uint8_t FXLS896x_OUT_X_LSB_t; 185 186 /*-------------------------------- 187 ** Register: OUT_X_MSB 188 ** Enum: FXLS896x_OUT_X_MSB 189 ** -- 190 ** Offset : 0x05 MSB of current 12-bit X-axis accelerometer output data. 191 ** ------------------------------*/ 192 typedef uint8_t FXLS896x_OUT_X_MSB_t; 193 194 /*-------------------------------- 195 ** Register: OUT_Y_LSB 196 ** Enum: FXLS896x_OUT_Y_LSB 197 ** -- 198 ** Offset : 0x06 LSB of current 12-bit Y-axis accelerometer output data. 199 ** ------------------------------*/ 200 typedef uint8_t FXLS896x_OUT_Y_LSB_t; 201 202 /*-------------------------------- 203 ** Register: OUT_Y_MSB 204 ** Enum: FXLS896x_OUT_Y_MSB 205 ** -- 206 ** Offset : 0x07 MSB of current 12-bit Y-axis accelerometer output data. 207 ** ------------------------------*/ 208 typedef uint8_t FXLS896x_OUT_Y_MSB_t; 209 210 /*-------------------------------- 211 ** Register: OUT_Z_LSB 212 ** Enum: FXLS896x_OUT_Z_LSB 213 ** -- 214 ** Offset : 0x08 LSB of current 12-bit Z-axis accelerometer output data. 215 ** ------------------------------*/ 216 typedef uint8_t FXLS896x_OUT_Z_LSB_t; 217 218 /*-------------------------------- 219 ** Register: OUT_Z_MSB 220 ** Enum: FXLS896x_OUT_Z_MSB 221 ** -- 222 ** Offset : 0x09 MSB of current 12-bit Z-axis accelerometer output data. 223 ** ------------------------------*/ 224 typedef uint8_t FXLS896x_OUT_Z_MSB_t; 225 226 /*-------------------------------- 227 ** Register: BUF_STATUS 228 ** Enum: FXLS896x_BUF_STATUS 229 ** -- 230 ** Offset : 0x0B Buf status. 231 ** ------------------------------*/ 232 typedef union { 233 struct { 234 uint8_t buf_cnt : 6; /* Count of the acceleration data samples */ 235 236 uint8_t buf_ovf : 1; /* Buffer Overflow Event Flag */ 237 238 uint8_t buf_wmrk : 1; /* Buffer Watermark Event Flag */ 239 240 } b; 241 uint8_t w; 242 } FXLS896x_BUF_STATUS_t; 243 244 245 /* 246 ** BUF_STATUS - Bit field mask definitions 247 */ 248 #define FXLS896x_BUF_STATUS_BUF_CNT_MASK ((uint8_t) 0x3F) 249 #define FXLS896x_BUF_STATUS_BUF_CNT_SHIFT ((uint8_t) 0) 250 251 #define FXLS896x_BUF_STATUS_BUF_OVF_MASK ((uint8_t) 0x40) 252 #define FXLS896x_BUF_STATUS_BUF_OVF_SHIFT ((uint8_t) 6) 253 254 #define FXLS896x_BUF_STATUS_BUF_WMRK_MASK ((uint8_t) 0x80) 255 #define FXLS896x_BUF_STATUS_BUF_WMRK_SHIFT ((uint8_t) 7) 256 257 258 259 /*-------------------------------- 260 ** Register: BUF_X_LSB 261 ** Enum: FXLS896x_BUF_X_LSB 262 ** -- 263 ** Offset : 0x0C LSB Head Tail output buffer buffer X axis. 264 ** ------------------------------*/ 265 typedef uint8_t FXLS896x_BUF_X_LSB_t; 266 267 268 /*-------------------------------- 269 ** Register: BUF_X_MSB 270 ** Enum: FXLS896x_BUF_X_MSB 271 ** -- 272 ** Offset : 0x0D MSB Head Tail output buffer buffer Z axis. 273 ** ------------------------------*/ 274 typedef uint8_t FXLS896x_BUF_X_MSB_t; 275 276 277 /*-------------------------------- 278 ** Register: BUF_Y_LSB 279 ** Enum: FXLS896x_BUF_Y_LSB 280 ** -- 281 ** Offset : 0x0E LSB Head Tail output buffer buffer Y axis. 282 ** ------------------------------*/ 283 typedef uint8_t FXLS896x_BUF_Y_LSB_t; 284 285 286 /*-------------------------------- 287 ** Register: BUF_Y_MSB 288 ** Enum: FXLS896x_BUF_Y_MSB 289 ** -- 290 ** Offset : 0x0F MSB Head Tail output buffer buffer Y axis. 291 ** ------------------------------*/ 292 typedef uint8_t FXLS896x_BUF_Y_MSB_t; 293 294 295 /*-------------------------------- 296 ** Register: BUF_Z_LSB 297 ** Enum: FXLS896x_BUF_Z_LSB 298 ** -- 299 ** Offset : 0x10 LSB Head Tail output buffer buffer Z axis. 300 ** ------------------------------*/ 301 typedef uint8_t FXLS896x_BUF_Z_LSB_t; 302 303 304 /*-------------------------------- 305 ** Register: BUF_Z_MSB 306 ** Enum: FXLS896x_BUF_Z_MSB 307 ** -- 308 ** Offset : 0x11 MSB Head Tail output buffer buffer Z axis. 309 ** ------------------------------*/ 310 typedef uint8_t FXLS896x_BUF_Z_MSB_t; 311 312 /*-------------------------------- 313 ** Register: PROD_REV 314 ** Enum: FXLS896x_PROD_REV 315 ** -- 316 ** Offset : 0x12 Product revision number in BCD format. 317 ** ------------------------------*/ 318 typedef union 319 { 320 struct 321 { 322 uint8_t prod_rev_min : 4; /* Product revision info, minor product revision value with range 0 to 9 in */ 323 /* BCD format. */ 324 325 uint8_t prod_rev_maj : 4; /* Product revision info, major product revision value with range 1 to 9 in */ 326 /* BCD format. */ 327 328 } b; 329 uint8_t w; 330 } FXLS896x_PROD_REV_t; 331 332 /* 333 ** PROD_REV - Bit field mask definitions 334 */ 335 #define FXLS896x_PROD_REV_PROD_REV_MIN_MASK ((uint8_t)0x0F) 336 #define FXLS896x_PROD_REV_PROD_REV_MIN_SHIFT ((uint8_t)0) 337 338 #define FXLS896x_PROD_REV_PROD_REV_MAJ_MASK ((uint8_t)0xF0) 339 #define FXLS896x_PROD_REV_PROD_REV_MAJ_SHIFT ((uint8_t)4) 340 341 /*-------------------------------- 342 ** Register: WHO_AM_I 343 ** Enum: FXLS896x_WHO_AM_I 344 ** -- 345 ** Offset : 0x13 8-bit NXP unique sensor Product ID. 346 ** ------------------------------*/ 347 typedef uint8_t FXLS896x_WHO_AM_I_t; 348 349 /*-------------------------------- 350 ** Register: SYS_MODE 351 ** Enum: FXLS896x_SYS_MODE 352 ** -- 353 ** Offset : 0x14 Current System Operating Mode. 354 ** ------------------------------*/ 355 typedef union 356 { 357 struct 358 { 359 uint8_t sys_mode : 2; /* Current System operating mode. */ 360 361 uint8_t buf_gate_cnt : 5; /* number of OOR periods that have elapsed since the BUF _GATE_ERR flag was asserted. */ 362 363 uint8_t buf_gate_error : 1; /* Buffer gate error flag. */ 364 365 } b; 366 uint8_t w; 367 } FXLS896x_SYS_MODE_t; 368 369 /* 370 ** SYS_MODE - Bit field mask definitions 371 */ 372 #define FXLS896x_SYS_MODE_BUF_GATE_ERROR_MASK ((uint8_t)0x03) 373 #define FXLS896x_SYS_MODE_BUF_GATE_ERROR_SHIFT ((uint8_t)0) 374 375 #define FXLS896x_SYS_MODE_BUF_GATE_CNT_MASK ((uint8_t)0x7C) 376 #define FXLS896x_SYS_MODE_BUF_GATE_CNT_SHIFT ((uint8_t)2) 377 378 #define FXLS896x_SYS_MODE_SYS_MODE_MASK ((uint8_t)0x80) 379 #define FXLS896x_SYS_MODE_SYS_MODE_SHIFT ((uint8_t)7) 380 381 /* 382 ** SYS_MODE - Bit field value definitions 383 */ 384 #define FXLS896x_SYS_MODE_BUF_GARE_ERROR_NO ((uint8_t)0x00) /* Not Detected. */ 385 #define FXLS896x_SYS_MODE_BUF_GARE_ERROR_YES ((uint8_t)0x80)/* Detected. */ 386 #define FXLS896x_SYS_MODE_SYS_MODE_STANDBY ((uint8_t)0x00) /* Standby Mode. */ 387 #define FXLS896x_SYS_MODE_SYS_MODE_WAKE ((uint8_t)0x01) /* Wake Mode. */ 388 #define FXLS896x_SYS_MODE_SYS_MODE_SLEEP ((uint8_t)0x02) /* Sleep Mode. */ 389 #define FXLS896x_SYS_MODE_SYS_MODE_EXT_TRIG ((uint8_t)0x03) /* External Trigger Mode. */ 390 /*------------------------------*/ 391 392 /*-------------------------------- 393 ** Register: SENS_CONFIG1 394 ** Enum: FXLS896x_SENS_CONFIG1 395 ** -- 396 ** Offset : 0x15 Configuration register 1. 397 ** ------------------------------*/ 398 typedef union 399 { 400 struct 401 { 402 uint8_t active : 1; /* Standby/Active mode selection */ 403 404 uint8_t fsr : 2; /* Full-scale measurement range (FSR) selection. */ 405 406 uint8_t spi_m : 1; /* SPI interface mode selection; selects between 3- and 4-wire operating */ 407 /* modes for the SPI interface. */ 408 409 uint8_t st_pol : 1; /* Self-Test Displacement Polarity */ 410 411 uint8_t st_axis_sel : 2; /* Self-Test Axis Selection */ 412 413 uint8_t rst : 1; /* The RST bit may be used to initiate a software reset. */ 414 415 } b; 416 uint8_t w; 417 } FXLS896x_SENS_CONFIG1_t; 418 419 /* 420 ** SENS_CONFIG1 - Bit field mask definitions 421 */ 422 #define FXLS896x_SENS_CONFIG1_ACTIVE_MASK ((uint8_t)0x01) 423 #define FXLS896x_SENS_CONFIG1_ACTIVE_SHIFT ((uint8_t)0) 424 425 #define FXLS896x_SENS_CONFIG1_FSR_MASK ((uint8_t)0x06) 426 #define FXLS896x_SENS_CONFIG1_FSR_SHIFT ((uint8_t)1) 427 428 #define FXLS896x_SENS_CONFIG1_SPI_M_MASK ((uint8_t)0x08) 429 #define FXLS896x_SENS_CONFIG1_SPI_M_SHIFT ((uint8_t)3) 430 431 #define FXLS896x_SENS_CONFIG1_ST_POL_MASK ((uint8_t)0x10) 432 #define FXLS896x_SENS_CONFIG1_ST_POL_SHIFT ((uint8_t)4) 433 434 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_MASK ((uint8_t)0x60) 435 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_SHIFT ((uint8_t)5) 436 437 #define FXLS896x_SENS_CONFIG1_RST_MASK ((uint8_t)0x80) 438 #define FXLS896x_SENS_CONFIG1_RST_SHIFT ((uint8_t)7) 439 440 /* 441 ** SENS_CONFIG1 - Bit field value definitions 442 */ 443 #define FXLS896x_SENS_CONFIG1_RST_RST ((uint8_t)0x80) /* Trigger Reset */ 444 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_DISABLED \ 445 ((uint8_t)0x00) /* Self-Test function is disabled */ 446 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_X ((uint8_t)0x20) /* Self-Test function is enabled for X-axis */ 447 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_Y ((uint8_t)0x40) /* Self-Test function is enabled for Y-axis */ 448 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_Z ((uint8_t)0x60) /* Self-Test function is enabled for Z-axis */ 449 #define FXLS896x_SENS_CONFIG1_ST_POL_POSITIVE ((uint8_t)0x00) /* Proof mass displacement for the selected axis */ 450 /* is in the positive direction. */ 451 #define FXLS896x_SENS_CONFIG1_ST_POL_NEGATIVE ((uint8_t)0x10) /* Proof mass displacement for the selected axis */ 452 /* is in the negative direction. */ 453 #define FXLS896x_SENS_CONFIG1_SPI_M_FOUR ((uint8_t)0x00) /* 4-wire interface mode is selected. */ 454 #define FXLS896x_SENS_CONFIG1_SPI_M_THREE ((uint8_t)0x08) /* 3-wire interface mode is selected. */ 455 #define FXLS896x_SENS_CONFIG1_FSR_2G ((uint8_t)0x00) /* ±2g; 0.98 mg/LSB (1024 LSB/g) nominal */ 456 /* sensitivity. */ 457 #define FXLS896x_SENS_CONFIG1_FSR_4G ((uint8_t)0x02) /* ±4g; 1.95 mg/LSB (512 LSB/g) nominal */ 458 /* sensitivity. */ 459 #define FXLS896x_SENS_CONFIG1_FSR_8G ((uint8_t)0x04) /* ±8g; 3.91 mg/LSB (256 LSB/g) nominal */ 460 /* sensitivity. */ 461 #define FXLS896x_SENS_CONFIG1_FSR_16G ((uint8_t)0x06) /* ±16g; 7.81 mg/LSB (128 LSB/g) nominal */ 462 /* sensitivity. */ 463 #define FXLS896x_SENS_CONFIG1_ACTIVE_STANDBY ((uint8_t)0x00) /* Standby mode. */ 464 #define FXLS896x_SENS_CONFIG1_ACTIVE_ACTIVE ((uint8_t)0x01) /* Active mode. */ 465 /*------------------------------*/ 466 467 /*-------------------------------- 468 ** Register: SENS_CONFIG2 469 ** Enum: FXLS896x_SENS_CONFIG2 470 ** -- 471 ** Offset : 0x16 Configuration register 2. 472 ** ------------------------------*/ 473 typedef union 474 { 475 struct 476 { 477 uint8_t f_read : 1; /* Fast-read mode selection. */ 478 479 uint8_t anic_temp : 1; /* Temperature output data auto-increment control. */ 480 481 uint8_t _reserved_ : 1; 482 uint8_t le_be : 1; /* Little/Big-endian output mode selection. */ 483 484 uint8_t sleep_pm : 2; /* SLEEP power mode selection. */ 485 486 uint8_t wake_pm : 2; /* WAKE power mode selection. */ 487 488 } b; 489 uint8_t w; 490 } FXLS896x_SENS_CONFIG2_t; 491 492 /* 493 ** SENS_CONFIG2 - Bit field mask definitions 494 */ 495 #define FXLS896x_SENS_CONFIG2_F_READ_MASK ((uint8_t)0x01) 496 #define FXLS896x_SENS_CONFIG2_F_READ_SHIFT ((uint8_t)0) 497 498 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_MASK ((uint8_t)0x02) 499 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_SHIFT ((uint8_t)1) 500 501 #define FXLS896x_SENS_CONFIG2_LE_BE_MASK ((uint8_t)0x08) 502 #define FXLS896x_SENS_CONFIG2_LE_BE_SHIFT ((uint8_t)3) 503 504 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_MASK ((uint8_t)0x30) 505 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_SHIFT ((uint8_t)4) 506 507 #define FXLS896x_SENS_CONFIG2_WAKE_PM_MASK ((uint8_t)0xC0) 508 #define FXLS896x_SENS_CONFIG2_WAKE_PM_SHIFT ((uint8_t)6) 509 510 /* 511 ** SENS_CONFIG2 - Bit field value definitions 512 */ 513 #define FXLS896x_SENS_CONFIG2_WAKE_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */ 514 #define FXLS896x_SENS_CONFIG2_WAKE_PM_HIGH_PERF ((uint8_t)0x40) /* High Performance Mode is selected. */ 515 #define FXLS896x_SENS_CONFIG2_WAKE_PM_FLEX_PERF ((uint8_t)0x80) /* Flexible Performance Mode is selected. */ 516 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */ 517 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_HIGH_PERF ((uint8_t)0x10) /* High Performance Mode is selected. */ 518 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_FLEX_PERF ((uint8_t)0x20) /* Flexible Performance Mode is selected. */ 519 #define FXLS896x_SENS_CONFIG2_LE_BE_LE ((uint8_t)0x00) /* Little-endian output mode is selected. */ 520 #define FXLS896x_SENS_CONFIG2_LE_BE_BE ((uint8_t)0x08) /* Big-endian output mode is selected. */ 521 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_DIS ((uint8_t)0x00) /* TEMP_OUT register content is not included in */ 522 /* auto-increment address range. */ 523 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_EN ((uint8_t)0x02) /* TEMP_OUT register content is included in */ 524 /* auto-increment address range. */ 525 #define FXLS896x_SENS_CONFIG2_F_READ_NORMAL ((uint8_t)0x00) /* Normal read mode. */ 526 #define FXLS896x_SENS_CONFIG2_F_READ_FAST ((uint8_t)0x01) /* Fast read mode. */ 527 /*------------------------------*/ 528 529 /*-------------------------------- 530 ** Register: SENS_CONFIG3 531 ** Enum: FXLS896x_SENS_CONFIG3 532 ** -- 533 ** Offset : 0x17 Configuration register 3. 534 ** ------------------------------*/ 535 typedef union 536 { 537 struct 538 { 539 uint8_t sleep_odr : 4; /* Sleep ODR */ 540 541 uint8_t wake_odr : 4; /* Wake ODR */ 542 543 } b; 544 uint8_t w; 545 } FXLS896x_SENS_CONFIG3_t; 546 547 /* 548 ** SENS_CONFIG3 - Bit field mask definitions 549 */ 550 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_MASK ((uint8_t)0x0F) 551 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_SHIFT ((uint8_t)0) 552 553 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_MASK ((uint8_t)0xF0) 554 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_SHIFT ((uint8_t)4) 555 556 /* 557 ** SENS_CONFIG3 - Bit field value definitions 558 */ 559 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_3200HZ ((uint8_t)0x00) 560 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_1600HZ ((uint8_t)0x10) 561 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_800HZ ((uint8_t)0x20) 562 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_400HZ ((uint8_t)0x30) 563 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_200HZ ((uint8_t)0x40) 564 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_100HZ ((uint8_t)0x50) 565 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_50HZ ((uint8_t)0x60) 566 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_25HZ ((uint8_t)0x70) 567 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_12_5HZ ((uint8_t)0x80) 568 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_6_25HZ ((uint8_t)0x90) /* 6.25 HZ */ 569 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_3_125HZ ((uint8_t)0xa0) /* 3.125 HZ */ 570 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_1_563HZ ((uint8_t)0xb0) /* 1.563 HZ */ 571 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_0_781HZ ((uint8_t)0xc0) /* 0.781 HZ */ 572 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_3200HZ ((uint8_t)0x00) 573 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_1600HZ ((uint8_t)0x01) 574 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_800HZ ((uint8_t)0x02) 575 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_400HZ ((uint8_t)0x03) 576 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_200HZ ((uint8_t)0x04) 577 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_100HZ ((uint8_t)0x05) 578 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_50HZ ((uint8_t)0x06) 579 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_25HZ ((uint8_t)0x07) 580 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_12_5HZ ((uint8_t)0x08) 581 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_6_25HZ ((uint8_t)0x09) /* 6.25 HZ */ 582 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_3_125HZ ((uint8_t)0x0a) /* 3.125 HZ */ 583 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_1_563HZ ((uint8_t)0x0b) /* 1.563 HZ */ 584 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_0_781HZ ((uint8_t)0x0c) /* 0.781 HZ */ 585 /*------------------------------*/ 586 587 /*-------------------------------- 588 ** Register: SENS_CONFIG4 589 ** Enum: FXLS896x_SENS_CONFIG4 590 ** -- 591 ** Offset : 0x18 Configuration register 4. 592 ** ------------------------------*/ 593 typedef union 594 { 595 struct 596 { 597 uint8_t int_pol : 1; /* Interrupt logic polarity on INT1 and INT2 pins. */ 598 599 uint8_t int_pp_od : 1; /* INT1 and INT2 pins output driver selection. */ 600 601 uint8_t int2_func : 1; /* INT2 output / EXT_TRIG input pin selection. */ 602 603 uint8_t drdy_pul : 1; /* Pulse generation option for DRDY event. */ 604 605 uint8_t wk_orient : 1; /* Orientation change event Auto-WAKE/SLEEP transition source enable. */ 606 607 uint8_t wk_sdcd_ot : 1; /* SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable. */ 608 609 uint8_t wk_sdcd_wt : 1; /* SDCD within thresholds event Auto-WAKE/SLEEP transition source enable. */ 610 611 uint8_t ext_trig_m : 1; /* External trigger function acquisition mode. */ 612 613 } b; 614 uint8_t w; 615 } FXLS896x_SENS_CONFIG4_t; 616 617 /* 618 ** SENS_CONFIG4 - Bit field mask definitions 619 */ 620 #define FXLS896x_SENS_CONFIG4_INT_POL_MASK ((uint8_t)0x01) 621 #define FXLS896x_SENS_CONFIG4_INT_POL_SHIFT ((uint8_t)0) 622 623 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_MASK ((uint8_t)0x02) 624 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_SHIFT ((uint8_t)1) 625 626 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_MASK ((uint8_t)0x04) 627 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_SHIFT ((uint8_t)2) 628 629 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_MASK ((uint8_t)0x08) 630 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_SHIFT ((uint8_t)3) 631 632 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_MASK ((uint8_t)0x10) 633 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_SHIFT ((uint8_t)4) 634 635 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_MASK ((uint8_t)0x20) 636 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_SHIFT ((uint8_t)5) 637 638 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_MASK ((uint8_t)0x40) 639 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_SHIFT ((uint8_t)6) 640 641 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_MASK ((uint8_t)0x80) 642 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_SHIFT ((uint8_t)7) 643 644 /* 645 ** SENS_CONFIG4 - Bit field value definitions 646 */ 647 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_SINGLE ((uint8_t)0x00) /* Each positive going trigger edge causes a */ 648 /* single ADC acquisition to be made. */ 649 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_MULTIPLE ((uint8_t)0x80) /* Each positive going trigger edge causes the */ 650 /* number of acquisitions. */ 651 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_DIS ((uint8_t)0x00) /* SDCD within thresholds event is not used to */ 652 /* prevent entry into/trigger. */ 653 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_EN ((uint8_t)0x40) /* SDCD within thresholds event is used to prevent */ 654 /* entry into/trigger an exit from SLEEP mode. */ 655 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_DIS ((uint8_t)0x00) /* SDCD outside thresholds event is not used to */ 656 /* prevent entry into/trigger. */ 657 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_EN ((uint8_t)0x20) /* SDCD outside thresholds event is used to */ 658 /* prevent entry into/trigger an exit from SLEEP */ 659 /* mode. */ 660 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_DIS ((uint8_t)0x00) /* Orientation change condition is not used as an */ 661 /* event to prevent entry into /trigger an exit */ 662 /* from SLEEP mode. */ 663 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_EN ((uint8_t)0x10) /* Orientation change condition is used as an */ 664 /* event to prevent entry into/trigger an exit */ 665 /* from SLEEP mode. */ 666 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_DIS ((uint8_t)0x00) /* A SRC_DRDY event is output on the INTx pin as */ 667 /* an active high or active low signal. */ 668 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_EN ((uint8_t)0x08) /* A 32 μs (nominal) duration pulse is output on */ 669 /* the configured INTx pin once per ODR cycle. */ 670 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_INT2 ((uint8_t)0x00) /* INT2/EXT_TRIG pin is configured for the INT2 */ 671 /* output function. */ 672 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_EXT_TRIG \ 673 ((uint8_t)0x04) /* INT2/EXT_TRIG pin is configured as the EXT_TRIG \ \ \ 674 */ 675 /* input function. */ 676 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_PUSH_PULL ((uint8_t)0x00) /* INTx output pin driver is push-pull type. */ 677 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_OPEN_DRAIN \ 678 ((uint8_t)0x02) /* INTx output pin driver is */ 679 /* open-drain/open-source type. */ 680 #define FXLS896x_SENS_CONFIG4_INT_POL_ACT_LOW ((uint8_t)0x00) /* Active low:Interrupt events are signaled with a */ 681 /* logical 0 level. */ 682 #define FXLS896x_SENS_CONFIG4_INT_POL_ACT_HIGH ((uint8_t)0x01) /* Active high: interrupt events are signaled with */ 683 /* a logical 1 level. */ 684 /*------------------------------*/ 685 686 /*-------------------------------- 687 ** Register: SENS_CONFIG5 688 ** Enum: FXLS896x_SENS_CONFIG5 689 ** -- 690 ** Offset : 0x19 Configuration register 5. 691 ** ------------------------------*/ 692 typedef union 693 { 694 struct 695 { 696 uint8_t hibernate_en : 1; /* Hibernate mode enable. */ 697 698 uint8_t z_dis : 1; /* Z-axis auto-increment disable. */ 699 700 uint8_t y_dis : 1; /* Y-axis auto-increment disable. */ 701 702 uint8_t x_dis : 1; /* X-axis auto-increment disable. */ 703 704 uint8_t vecm_en : 1; /* Vector Magnitude calculation enable. */ 705 706 } b; 707 uint8_t w; 708 } FXLS896x_SENS_CONFIG5_t; 709 710 /* 711 ** SENS_CONFIG5 - Bit field mask definitions 712 */ 713 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_MASK ((uint8_t)0x01) 714 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_SHIFT ((uint8_t)0) 715 716 #define FXLS896x_SENS_CONFIG5_Z_DIS_MASK ((uint8_t)0x02) 717 #define FXLS896x_SENS_CONFIG5_Z_DIS_SHIFT ((uint8_t)1) 718 719 #define FXLS896x_SENS_CONFIG5_Y_DIS_MASK ((uint8_t)0x04) 720 #define FXLS896x_SENS_CONFIG5_Y_DIS_SHIFT ((uint8_t)2) 721 722 #define FXLS896x_SENS_CONFIG5_X_DIS_MASK ((uint8_t)0x08) 723 #define FXLS896x_SENS_CONFIG5_X_DIS_SHIFT ((uint8_t)3) 724 725 #define FXLS896x_SENS_CONFIG5_VECM_EN_MASK ((uint8_t)0x10) 726 #define FXLS896x_SENS_CONFIG5_VECM_EN_SHIFT ((uint8_t)4) 727 728 /* 729 ** SENS_CONFIG5 - Bit field value definitions 730 */ 731 #define FXLS896x_SENS_CONFIG5_VECM_EN_DIS ((uint8_t)0x00) /* 12-bit vector magnitude result is not */ 732 /* calculated on every ODR cycle. */ 733 #define FXLS896x_SENS_CONFIG5_VECM_EN_EN ((uint8_t)0x10) /* 12-bit vector magnitude result is calculated on */ 734 /* every ODR cycle. */ 735 #define FXLS896x_SENS_CONFIG5_X_DIS_EN ((uint8_t)0x00) /* X-axis measurement is included in the */ 736 /* auto-increment address range. */ 737 #define FXLS896x_SENS_CONFIG5_X_DIS_DIS ((uint8_t)0x08) /* X-axis measurement is excluded from the */ 738 /* auto-increment address range. */ 739 #define FXLS896x_SENS_CONFIG5_Y_DIS_EN ((uint8_t)0x00) /* Y-axis measurement is included in the */ 740 /* auto-increment address range. */ 741 #define FXLS896x_SENS_CONFIG5_Y_DIS_DIS ((uint8_t)0x04) /* Y-axis measurement is excluded from the */ 742 /* auto-increment address range. */ 743 #define FXLS896x_SENS_CONFIG5_Z_DIS_EN ((uint8_t)0x00) /* Z-axis measurement is included in the */ 744 /* auto-increment address range. */ 745 #define FXLS896x_SENS_CONFIG5_Z_DIS_DIS ((uint8_t)0x02) /* Z-axis measurement is excluded from the */ 746 /* auto-increment address range. */ 747 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_DIS ((uint8_t)0x00) /* Hibernate mode not enabled. */ 748 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_EN ((uint8_t)0x01) /* Commands device to enter Hibernate mode. */ 749 /*------------------------------*/ 750 751 /*-------------------------------- 752 ** Register: WAKE_IDLE_LSB 753 ** Enum: FXLS896x_WAKE_IDLE_LSB 754 ** -- 755 ** Offset : 0x1A LSB of 12-bit user programmable wake mode idle. 756 ** ------------------------------*/ 757 typedef uint8_t FXLS896x_WAKE_IDLE_LSB_t; 758 759 /*-------------------------------- 760 ** Register: WAKE_IDLE_MSB 761 ** Enum: FXLS896x_WAKE_IDLE_MSB 762 ** -- 763 ** Offset : 0x1B MSB of 12-bit user programmable wake mode idle. 764 ** ------------------------------*/ 765 typedef uint8_t FXLS896x_WAKE_IDLE_MSB_t; 766 767 /*-------------------------------- 768 ** Register: SLEEP_IDLE_LSB 769 ** Enum: FXLS896x_SLEEP_IDLE_LSB 770 ** -- 771 ** Offset : 0x1C LSB of 12-bit user programmable sleep mode idle. 772 ** ------------------------------*/ 773 typedef uint8_t FXLS896x_SLEEP_IDLE_LSB_t; 774 775 /*-------------------------------- 776 ** Register: SLEEP_IDLE_MSB 777 ** Enum: FXLS896x_SLEEP_IDLE_MSB 778 ** -- 779 ** Offset : 0x1D MSB of 12-bit user programmable sleep mode idle. 780 ** ------------------------------*/ 781 typedef uint8_t FXLS896x_SLEEP_IDLE_MSB_t; 782 783 /*-------------------------------- 784 ** Register: ASLP_COUNT_LSB 785 ** Enum: FXLS896x_ASLP_COUNT_LSB 786 ** -- 787 ** Offset : 0x1E LSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode. 788 ** ------------------------------*/ 789 typedef uint8_t FXLS896x_ASLP_COUNT_LSB_t; 790 791 /*-------------------------------- 792 ** Register: ASLP_COUNT_MSB 793 ** Enum: FXLS896x_ASLP_COUNT_MSB 794 ** -- 795 ** Offset : 0x1F MSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode. 796 ** ------------------------------*/ 797 typedef uint8_t FXLS896x_ASLP_COUNT_MSB_t; 798 799 /*-------------------------------- 800 ** Register: INT_EN 801 ** Enum: FXLS896x_INT_EN 802 ** -- 803 ** Offset : 0x20 Interrupt output enable register. 804 ** ------------------------------*/ 805 typedef union 806 { 807 struct 808 { 809 uint8_t wake_out_en : 1; /* WAKE power state output enable. */ 810 811 uint8_t boot_dis : 1; /* Boot interrupt output disable. */ 812 813 uint8_t aslp_en : 1; /* Auto-WAKE/SLEEP interrupt output enable. */ 814 815 uint8_t orient_en : 1; /* Orientation interrupt output enable. */ 816 817 uint8_t sdcd_wt_en : 1; /* SDCD within thresholds interrupt output enable. */ 818 819 uint8_t sdcd_ot_en : 1; /* SDCD outside of thresholds interrupt output enable. */ 820 821 uint8_t buf_en : 1; /* Output data buffer interrupt output enable */ 822 uint8_t drdy_en : 1; /* Data Ready interrupt output enable. */ 823 824 } b; 825 uint8_t w; 826 } FXLS896x_INT_EN_t; 827 828 /* 829 ** INT_EN - Bit field mask definitions 830 */ 831 #define FXLS896x_INT_EN_WAKE_OUT_EN_MASK ((uint8_t)0x01) 832 #define FXLS896x_INT_EN_WAKE_OUT_EN_SHIFT ((uint8_t)0) 833 834 #define FXLS896x_INT_EN_BOOT_DIS_MASK ((uint8_t)0x02) 835 #define FXLS896x_INT_EN_BOOT_DIS_SHIFT ((uint8_t)1) 836 837 #define FXLS896x_INT_EN_ASLP_EN_MASK ((uint8_t)0x04) 838 #define FXLS896x_INT_EN_ASLP_EN_SHIFT ((uint8_t)2) 839 840 #define FXLS896x_INT_EN_ORIENT_EN_MASK ((uint8_t)0x08) 841 #define FXLS896x_INT_EN_ORIENT_EN_SHIFT ((uint8_t)3) 842 843 #define FXLS896x_INT_EN_SDCD_WT_EN_MASK ((uint8_t)0x10) 844 #define FXLS896x_INT_EN_SDCD_WT_EN_SHIFT ((uint8_t)4) 845 846 #define FXLS896x_INT_EN_SDCD_OT_EN_MASK ((uint8_t)0x20) 847 #define FXLS896x_INT_EN_SDCD_OT_EN_SHIFT ((uint8_t)5) 848 849 #define FXLS896x_INT_EN_BUF_EN_MASK ((uint8_t)0x40) 850 #define FXLS896x_INT_EN_BUF_EN_SHIFT ((uint8_t)6) 851 852 #define FXLS896x_INT_EN_DRDY_EN_MASK ((uint8_t)0x80) 853 #define FXLS896x_INT_EN_DRDY_EN_SHIFT ((uint8_t)7) 854 855 /* 856 ** INT_EN - Bit field value definitions 857 */ 858 #define FXLS896x_INT_EN_DRDY_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */ 859 #define FXLS896x_INT_EN_DRDY_EN_EN ((uint8_t)0x80) /* Interrupt enabled. */ 860 #define FXLS896x_INT_EN_BUF_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */ 861 #define FXLS896x_INT_EN_BUF_EN_EN ((uint8_t)0x40) /* Interrupt enabled. */ 862 #define FXLS896x_INT_EN_SDCD_OT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */ 863 #define FXLS896x_INT_EN_SDCD_OT_EN_EN ((uint8_t)0x20) /* Interrupt is routed to either the INT1 or INT2. */ 864 #define FXLS896x_INT_EN_SDCD_WT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */ 865 #define FXLS896x_INT_EN_SDCD_WT_EN_EN ((uint8_t)0x10) /* Interrupt is routed to either the INT1 or INT2. */ 866 #define FXLS896x_INT_EN_ORIENT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */ 867 #define FXLS896x_INT_EN_ORIENT_EN_EN ((uint8_t)0x08) /* Interrupt is enabled and signaled on either the INT1 */ 868 /* or INT2. */ 869 #define FXLS896x_INT_EN_ASLP_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */ 870 #define FXLS896x_INT_EN_ASLP_EN_EN ((uint8_t)0x04) /* Interrupt is enabled and signaled on either the INT1 */ 871 /* or INT2. */ 872 #define FXLS896x_INT_EN_BOOT_DIS_EN ((uint8_t)0x00) /* Boot interrupt is enabled and routed to either the */ 873 /* INT1 or INT2. */ 874 #define FXLS896x_INT_EN_BOOT_DIS_DIS ((uint8_t)0x02) /* Interrupt is disabled and not routed to the INTx */ 875 /* output pins. */ 876 #define FXLS896x_INT_EN_WAKE_OUT_EN_DIS ((uint8_t)0x00) /* The device does not signal the WAKE operating mode on */ 877 /* the INTx output pin. */ 878 #define FXLS896x_INT_EN_WAKE_OUT_EN_EN ((uint8_t)0x01) /* The device signals that it is currently in WAKE mode */ 879 /* via the INT1 or INT2 pin. */ 880 /*------------------------------*/ 881 882 /*-------------------------------- 883 ** Register: INT_PIN_SEL 884 ** Enum: FXLS896x_INT_PIN_SEL 885 ** -- 886 ** Offset : 0x21 Interrupt output pin routing register, INT1 or INT2. 887 ** ------------------------------*/ 888 typedef union 889 { 890 struct 891 { 892 uint8_t wk_out_int2 : 1; /* WAKE power state interrupt routing. */ 893 894 uint8_t boot_int2 : 1; /* BOOT event interrupt routing. */ 895 896 uint8_t aslp_int2 : 1; /* Auto-WAKE/SLEEP event interrupt routing. */ 897 898 uint8_t orient_int2 : 1; /* ORIENT event interrupt routing. */ 899 900 uint8_t sdcd_wt_int2 : 1; /* SDCD within thresholds event interrupt routing. */ 901 902 uint8_t sdcd_ot_int2 : 1; /* SDCD outside of thresholds event interrupt routing. */ 903 904 uint8_t buf_int2 : 1; /* Output buffer interrupt routing. */ 905 906 uint8_t drdy_int2 : 1; /* Data Ready interrupt routing. */ 907 908 } b; 909 uint8_t w; 910 } FXLS896x_INT_PIN_SEL_t; 911 912 /* 913 ** INT_PIN_SEL - Bit field mask definitions 914 */ 915 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_MASK ((uint8_t)0x01) 916 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_SHIFT ((uint8_t)0) 917 918 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_MASK ((uint8_t)0x02) 919 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_SHIFT ((uint8_t)1) 920 921 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_MASK ((uint8_t)0x04) 922 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_SHIFT ((uint8_t)2) 923 924 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_MASK ((uint8_t)0x08) 925 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_SHIFT ((uint8_t)3) 926 927 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_MASK ((uint8_t)0x10) 928 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_SHIFT ((uint8_t)4) 929 930 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_MASK ((uint8_t)0x20) 931 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_SHIFT ((uint8_t)5) 932 933 #define FXLS896x_INT_PIN_SEL_BUF_INT2_MASK ((uint8_t)0x40) 934 #define FXLS896x_INT_PIN_SEL_BUF_INT2_SHIFT ((uint8_t)6) 935 936 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_MASK ((uint8_t)0x80) 937 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_SHIFT ((uint8_t)7) 938 939 /* 940 ** INT_PIN_SEL - Bit field value definitions 941 */ 942 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 943 /* enabled. */ 944 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_EN ((uint8_t)0x80) /* Interrupt signal is routed to INT2 pin if it is */ 945 /* enabled. */ 946 #define FXLS896x_INT_PIN_SEL_BUF_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 947 /* enabled. */ 948 #define FXLS896x_INT_PIN_SEL_BUF_INT2_EN ((uint8_t)0x40) /* Interrupt signal is routed to INT2 pin if it is */ 949 /* enabled. */ 950 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 951 /* enabled. */ 952 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_EN ((uint8_t)0x20) /* Interrupt signal is routed to INT2 pin if it is */ 953 /* enabled. */ 954 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 955 /* enabled. */ 956 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_EN ((uint8_t)0x10) /* Interrupt signal is routed to INT2 pin if it is */ 957 /* enabled. */ 958 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 959 /* enabled. */ 960 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_EN ((uint8_t)0x08) /* Interrupt signal is routed to INT2 pin if it is */ 961 /* enabled. */ 962 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 963 /* enabled. */ 964 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_EN ((uint8_t)0x04) /* Interrupt signal is routed to INT2 pin if it is */ 965 /* enabled. */ 966 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 967 /* enabled. */ 968 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_EN ((uint8_t)0x02) /* Interrupt signal is routed to INT2 pin if it is */ 969 /* enabled. */ 970 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */ 971 /* enabled. */ 972 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_EN ((uint8_t)0x01) /* Interrupt signal is routed to INT2 pin if it is */ 973 /* enabled. */ 974 /*------------------------------*/ 975 976 /*-------------------------------- 977 ** Register: OFF_X 978 ** Enum: FXLS896x_OFF_X 979 ** -- 980 ** Offset : 0x22 X-Acceleration zero-g offset. 981 ** ------------------------------*/ 982 typedef uint8_t FXLS896x_OFF_X_t; 983 984 /*-------------------------------- 985 ** Register: OFF_Y 986 ** Enum: FXLS896x_OFF_Y 987 ** -- 988 ** Offset : 0x23 Y-Acceleration zero-g offset. 989 ** ------------------------------*/ 990 typedef uint8_t FXLS896x_OFF_Y_t; 991 992 /*-------------------------------- 993 ** Register: OFF_Z 994 ** Enum: FXLS896x_OFF_Z 995 ** -- 996 ** Offset : 0x24 Z-Acceleration zero-g offset. 997 ** ------------------------------*/ 998 typedef uint8_t FXLS896x_OFF_Z_t; 999 1000 1001 1002 /*-------------------------------- 1003 ** Register: BUF_CONFIG1 1004 ** Enum: FXLS896x_BUF_CONFIG1 1005 ** -- 1006 ** Offset : 0x26 Buf configuration1. 1007 ** ------------------------------*/ 1008 typedef union { 1009 struct { 1010 uint8_t trg_orient : 1; /* Orientation change event trigger enable */ 1011 1012 uint8_t _reserved_ : 1; 1013 uint8_t trg_sdcd_ot : 1; /* SDCD outside-of-thresholds event buffer trigger enable */ 1014 1015 uint8_t trg_sdcd_wt : 1; /* SDCD within-thresholds event trigger enable */ 1016 1017 uint8_t buf_gate : 1; /* Output data buffer gate enable */ 1018 1019 uint8_t buf_mode : 2; /* Buffer data collection mode */ 1020 1021 uint8_t buf_type : 1; /* Buffer data read out order */ 1022 1023 } b; 1024 uint8_t w; 1025 } FXLS896x_BUF_CONFIG1_t; 1026 1027 1028 /* 1029 ** BUF_CONFIG1 - Bit field mask definitions 1030 */ 1031 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_MASK ((uint8_t) 0x01) 1032 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_SHIFT ((uint8_t) 0) 1033 1034 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_MASK ((uint8_t) 0x04) 1035 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_SHIFT ((uint8_t) 2) 1036 1037 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_MASK ((uint8_t) 0x08) 1038 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_SHIFT ((uint8_t) 3) 1039 1040 #define FXLS896x_BUF_CONFIG1_BUF_GATE_MASK ((uint8_t) 0x10) 1041 #define FXLS896x_BUF_CONFIG1_BUF_GATE_SHIFT ((uint8_t) 4) 1042 1043 #define FXLS896x_BUF_CONFIG1_BUF_MODE_MASK ((uint8_t) 0x60) 1044 #define FXLS896x_BUF_CONFIG1_BUF_MODE_SHIFT ((uint8_t) 5) 1045 1046 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_MASK ((uint8_t) 0x80) 1047 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_SHIFT ((uint8_t) 7) 1048 1049 1050 /* 1051 ** BUF_CONFIG1 - Bit field value definitions 1052 */ 1053 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_FIFO ((uint8_t) 0x00) /* In FIFO mode */ 1054 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_FILO ((uint8_t) 0x80) /* First In Last Out (FILO) */ 1055 #define FXLS896x_BUF_CONFIG1_BUF_MODE_DIS ((uint8_t) 0x00) /* Buffer is disabled */ 1056 #define FXLS896x_BUF_CONFIG1_BUF_MODE_STREAM_MODE ((uint8_t) 0x20) /* Stream Mode */ 1057 #define FXLS896x_BUF_CONFIG1_BUF_MODE_STOP_MODE ((uint8_t) 0x40) /* Stop mode */ 1058 #define FXLS896x_BUF_CONFIG1_BUF_MODE_TRIGGER_MODE ((uint8_t) 0x60) /* Trigger Mode */ 1059 #define FXLS896x_BUF_CONFIG1_BUF_GATE_BY_PASSED ((uint8_t) 0x00) /* Buffer gate is bypassed. */ 1060 #define FXLS896x_BUF_CONFIG1_BUF_GATE_ENABLED ((uint8_t) 0x10) /* The Buffer gate input is enabled. */ 1061 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */ 1062 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_EN ((uint8_t) 0x08) /* Trigger source is enabled. */ 1063 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */ 1064 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_EN ((uint8_t) 0x04) /* Trigger source is enabled. */ 1065 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */ 1066 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_EN ((uint8_t) 0x01) /* Trigger source is enabled. */ 1067 /*------------------------------*/ 1068 1069 1070 1071 /*-------------------------------- 1072 ** Register: BUF_CONFIG2 1073 ** Enum: FXLS896x_BUF_CONFIG2 1074 ** -- 1075 ** Offset : 0x27 buf configuration2. 1076 ** ------------------------------*/ 1077 typedef union { 1078 struct { 1079 uint8_t buf_wmrk : 6; /* Buffer sample count watermark */ 1080 1081 uint8_t wake_src_buf : 1; /* Buffer WAKE-to-SLEEP transition source enable */ 1082 1083 uint8_t buf_flush : 1; /* Buffer flush enable */ 1084 1085 } b; 1086 uint8_t w; 1087 } FXLS896x_BUF_CONFIG2_t; 1088 1089 1090 /* 1091 ** BUF_CONFIG2 - Bit field mask definitions 1092 */ 1093 #define FXLS896x_BUF_CONFIG2_BUF_WMRK_MASK ((uint8_t) 0x3F) 1094 #define FXLS896x_BUF_CONFIG2_BUF_WMRK_SHIFT ((uint8_t) 0) 1095 1096 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_MASK ((uint8_t) 0x40) 1097 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_SHIFT ((uint8_t) 6) 1098 1099 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_MASK ((uint8_t) 0x80) 1100 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_SHIFT ((uint8_t) 7) 1101 1102 1103 /* 1104 ** BUF_CONFIG2 - Bit field value definitions 1105 */ 1106 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_COMPLETED ((uint8_t) 0x00) /* Buffer flush operation not pending/completed. */ 1107 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_EN ((uint8_t) 0x80) /* Buffer flush enable. */ 1108 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_IGNORED ((uint8_t) 0x00) /* BUF_WMRK and BUF_OVF and event flags are ignored */ 1109 /* by the auto-WAKE/SLEEP function. */ 1110 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_EN ((uint8_t) 0x40) /* BUF_WMRK and BUF_OVF event flags are used by the */ 1111 /* auto-WAKE/SLEEP function */ 1112 1113 1114 /*-------------------------------- 1115 ** Register: ORIENT_STATUS 1116 ** Enum: FXLS896x_ORIENT_STATUS 1117 ** -- 1118 ** Offset : 0x28 Orientation event status. 1119 ** ------------------------------*/ 1120 typedef union 1121 { 1122 struct 1123 { 1124 uint8_t bafro : 1; /* Back or front orientation. */ 1125 1126 uint8_t lapo : 2; /* Landscape/Portrait orientation. */ 1127 1128 uint8_t _reserved_ : 3; 1129 uint8_t lo : 1; /* Z-tilt angle lockout. */ 1130 1131 uint8_t new_orient : 1; /* Orientation status change flag. */ 1132 1133 } b; 1134 uint8_t w; 1135 } FXLS896x_ORIENT_STATUS_t; 1136 1137 /* 1138 ** ORIENT_STATUS - Bit field mask definitions 1139 */ 1140 #define FXLS896x_ORIENT_STATUS_BAFRO_MASK ((uint8_t)0x01) 1141 #define FXLS896x_ORIENT_STATUS_BAFRO_SHIFT ((uint8_t)0) 1142 1143 #define FXLS896x_ORIENT_STATUS_LAPO_MASK ((uint8_t)0x06) 1144 #define FXLS896x_ORIENT_STATUS_LAPO_SHIFT ((uint8_t)1) 1145 1146 #define FXLS896x_ORIENT_STATUS_LO_MASK ((uint8_t)0x40) 1147 #define FXLS896x_ORIENT_STATUS_LO_SHIFT ((uint8_t)6) 1148 1149 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_MASK ((uint8_t)0x80) 1150 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_SHIFT ((uint8_t)7) 1151 1152 /* 1153 ** ORIENT_STATUS - Bit field value definitions 1154 */ 1155 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_NO_CHANGE \ 1156 ((uint8_t)0x00) /* No change in orientation detected. */ 1157 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_CHANGED ((uint8_t)0x80) /* BAFRO and/or LAPO and/or Z-tilt lockout value */ 1158 /* has changed. */ 1159 #define FXLS896x_ORIENT_STATUS_LO_NOT_DETECTED ((uint8_t)0x00) /* Lockout condition has not been detected. */ 1160 #define FXLS896x_ORIENT_STATUS_LO_DETECTED ((uint8_t)0x40) /* Z-tilt lockout trip angle has been exceeded. */ 1161 /* Lockout condition has been detected. */ 1162 #define FXLS896x_ORIENT_STATUS_LAPO_UP ((uint8_t)0x00) /* Portrait up. */ 1163 #define FXLS896x_ORIENT_STATUS_LAPO_DOWN ((uint8_t)0x02) /* Portrait down. */ 1164 #define FXLS896x_ORIENT_STATUS_LAPO_RIGHT ((uint8_t)0x04) /* Landscape right. */ 1165 #define FXLS896x_ORIENT_STATUS_LAPO_LEFT ((uint8_t)0x06) /* Landscape left. */ 1166 #define FXLS896x_ORIENT_STATUS_BAFRO_FRONT ((uint8_t)0x00) /* The device is in the front-facing orientation. */ 1167 #define FXLS896x_ORIENT_STATUS_BAFRO_BACK ((uint8_t)0x01) /* The device is in the back-facing orientation. */ 1168 /*------------------------------*/ 1169 1170 /*-------------------------------- 1171 ** Register: ORIENT_CONFIG 1172 ** Enum: FXLS896x_ORIENT_CONFIG 1173 ** -- 1174 ** Offset : 0x29 Orientation detection function configuration. 1175 ** ------------------------------*/ 1176 typedef union 1177 { 1178 struct 1179 { 1180 uint8_t _reserved_ : 6; 1181 uint8_t orient_enable : 1; /* Orientation detection function enable. */ 1182 1183 uint8_t orient_dbcntm : 1; /* Orientation debounce counter mode selection. */ 1184 1185 } b; 1186 uint8_t w; 1187 } FXLS896x_ORIENT_CONFIG_t; 1188 1189 /* 1190 ** ORIENT_CONFIG - Bit field mask definitions 1191 */ 1192 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_MASK ((uint8_t)0x40) 1193 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_SHIFT ((uint8_t)6) 1194 1195 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_MASK ((uint8_t)0x80) 1196 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_SHIFT ((uint8_t)7) 1197 1198 /* 1199 ** ORIENT_CONFIG - Bit field value definitions 1200 */ 1201 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_DEC ((uint8_t)0x00) /* Orientation debounce counter is decremented */ 1202 /* whenever the current orientation is different */ 1203 /* thanthe previous one. */ 1204 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_CLR ((uint8_t)0x80) /* Orientation debounce counter is cleared */ 1205 /* whenever the current orientation is different */ 1206 /* than the previous one. */ 1207 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_DIS ((uint8_t)0x00) /* Orientation detection function is disabled. */ 1208 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_EN ((uint8_t)0x40) /* Orientation detection function is enabled. */ 1209 /*------------------------------*/ 1210 1211 /*-------------------------------- 1212 ** Register: ORIENT_DBCOUNT 1213 ** Enum: FXLS896x_ORIENT_DBCOUNT 1214 ** -- 1215 ** Offset : 0x2A Orientation detection debounce counter. 1216 ** ------------------------------*/ 1217 typedef uint8_t FXLS896x_ORIENT_DBCOUNT_t; 1218 1219 /*-------------------------------- 1220 ** Register: ORIENT_BF_ZCOMP 1221 ** Enum: FXLS896x_ORIENT_BF_ZCOMP 1222 ** -- 1223 ** Offset : 0x2B Orientation back/front and Z-tilt angle compensation register. 1224 ** ------------------------------*/ 1225 typedef union 1226 { 1227 struct 1228 { 1229 uint8_t orient_zlock : 3; /* Z-lock out angle threshold. */ 1230 1231 uint8_t _reserved_ : 3; 1232 uint8_t orient_bkfr : 2; /* Back-Up / Front-Up trip angle threshold. */ 1233 1234 } b; 1235 uint8_t w; 1236 } FXLS896x_ORIENT_BF_ZCOMP_t; 1237 1238 /* 1239 ** ORIENT_BF_ZCOMP - Bit field mask definitions 1240 */ 1241 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_MASK ((uint8_t)0x07) 1242 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_SHIFT ((uint8_t)0) 1243 1244 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_MASK ((uint8_t)0xC0) 1245 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_SHIFT ((uint8_t)6) 1246 1247 /* 1248 ** ORIENT_BF_ZCOMP - Bit field value definitions 1249 */ 1250 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_80_280_FB_100_260 \ 1251 ((uint8_t)0x00) /* Back to front Z < 80° or Z > 280° */ 1252 /* and Front to back Z > 100° and Z */ 1253 /* < 260° */ 1254 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_75_285_FB_105_255 \ 1255 ((uint8_t)0x40) /* Back to front Z < 75° or Z > 285° */ 1256 /* and Front to back Z > 105° and Z */ 1257 /* < 255° */ 1258 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_70_290_FB_110_250 \ 1259 ((uint8_t)0x80) /* Back to front Z < 70° or Z > 290° */ 1260 /* and Front to back Z > 110° and Z */ 1261 /* < 250° */ 1262 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_65_295_FB_115_245 \ 1263 ((uint8_t)0xc0) /* Back to front Z < 65° or Z > 295° */ 1264 /* and Front to back Z > 115° and Z */ 1265 /* < 250° */ 1266 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_13_6 ((uint8_t)0x00) /* Resultant angle 13.6 */ 1267 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_17_1 ((uint8_t)0x01) /* Resultant angle 17.1 */ 1268 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_20_7 ((uint8_t)0x02) /* Resultant angle 20.7 */ 1269 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_24_4 ((uint8_t)0x03) /* Resultant angle 24.4 */ 1270 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_28_1 ((uint8_t)0x04) /* Resultant angle 28.1 */ 1271 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_32_0 ((uint8_t)0x05) /* Resultant angle 32.0 */ 1272 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_36_1 ((uint8_t)0x06) /* Resultant angle 36.1 */ 1273 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_40_4 ((uint8_t)0x07) /* Resultant angle 40.4 */ 1274 /*------------------------------*/ 1275 1276 /*-------------------------------- 1277 ** Register: ORIENT_THS_REG 1278 ** Enum: FXLS896x_ORIENT_THS_REG 1279 ** -- 1280 ** Offset : 0x2C Orientation detection state change threshold angle (Portrait/Landscape) and hysteresis settings. 1281 ** ------------------------------*/ 1282 typedef union 1283 { 1284 struct 1285 { 1286 uint8_t hys : 3; /* ORIENT_HYS[2:0] */ 1287 1288 uint8_t orient_ths : 5; /* ORIENT_THS[4:0] value */ 1289 1290 } b; 1291 uint8_t w; 1292 } FXLS896x_ORIENT_THS_REG_t; 1293 1294 /* 1295 ** ORIENT_THS_REG - Bit field mask definitions 1296 */ 1297 #define FXLS896x_ORIENT_THS_REG_HYS_MASK ((uint8_t)0x07) 1298 #define FXLS896x_ORIENT_THS_REG_HYS_SHIFT ((uint8_t)0) 1299 1300 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_MASK ((uint8_t)0xF8) 1301 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_SHIFT ((uint8_t)3) 1302 1303 /* 1304 ** ORIENT_THS_REG - Bit field value definitions 1305 */ 1306 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_0_0 ((uint8_t)0x00) /* 0.0° */ 1307 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_1_8 ((uint8_t)0x08) /* 1.8° */ 1308 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_3_8 ((uint8_t)0x10) /* 3.8° */ 1309 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_5_9 ((uint8_t)0x18) /* 5.9° */ 1310 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_8_1 ((uint8_t)0x20) /* 8.1° */ 1311 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_10_5 ((uint8_t)0x28) /* 10.5° */ 1312 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_13_0 ((uint8_t)0x30) /* 13.0° */ 1313 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_15_6 ((uint8_t)0x38) /* 15.6° */ 1314 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_18_4 ((uint8_t)0x40) /* 18.4° */ 1315 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_21_4 ((uint8_t)0x48) /* 21.4° */ 1316 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_24_4 ((uint8_t)0x50) /* 24.4° */ 1317 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_27_6 ((uint8_t)0x58) /* 27.6° */ 1318 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_31_0 ((uint8_t)0x60) /* 31.0° */ 1319 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_34_4 ((uint8_t)0x68) /* 34.4° */ 1320 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_37_9 ((uint8_t)0x70) /* 37.9° */ 1321 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_41_4 ((uint8_t)0x78) /* 41.4° */ 1322 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_45_0 ((uint8_t)0x80) /* 45.0° */ 1323 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_48_6 ((uint8_t)0x88) /* 48.6° */ 1324 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_52_1 ((uint8_t)0x90) /* 52.1° */ 1325 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_55_6 ((uint8_t)0x98) /* 55.6° */ 1326 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_59_0 ((uint8_t)0xa0) /* 59.0° */ 1327 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_62_4 ((uint8_t)0xa8) /* 62.4° */ 1328 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_65_6 ((uint8_t)0xb0) /* 65.6° */ 1329 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_68_6 ((uint8_t)0xb8) /* 68.6° */ 1330 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_71_6 ((uint8_t)0xc0) /* 71.6° */ 1331 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_74_4 ((uint8_t)0xc8) /* 74.4° */ 1332 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_77_0 ((uint8_t)0xd0) /* 77.0° */ 1333 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_79_5 ((uint8_t)0xd8) /* 79.5° */ 1334 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_81_9 ((uint8_t)0xe0) /* 81.9° */ 1335 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_84_1 ((uint8_t)0xe8) /* 84.1° */ 1336 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_86_2 ((uint8_t)0xf0) /* 86.2° */ 1337 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_88_2 ((uint8_t)0xf8) /* 88.2° */ 1338 #define FXLS896x_ORIENT_THS_REG_HYS_45_45 ((uint8_t)0x00) /* L-to-P 45° P-to-L 45° */ 1339 #define FXLS896x_ORIENT_THS_REG_HYS_49_41 ((uint8_t)0x01) /* L-to-P 49° P-to-L 41° */ 1340 #define FXLS896x_ORIENT_THS_REG_HYS_52_38 ((uint8_t)0x02) /* L-to-P 52° P-to-L 38° */ 1341 #define FXLS896x_ORIENT_THS_REG_HYS_56_34 ((uint8_t)0x03) /* L-to-P 56° P-to-L 34° */ 1342 #define FXLS896x_ORIENT_THS_REG_HYS_59_31 ((uint8_t)0x04) /* L-to-P 59° P-to-L 31° */ 1343 #define FXLS896x_ORIENT_THS_REG_HYS_62_28 ((uint8_t)0x05) /* L-to-P 62° P-to-L 28° */ 1344 #define FXLS896x_ORIENT_THS_REG_HYS_66_24 ((uint8_t)0x06) /* L-to-P 66° P-to-L 24° */ 1345 #define FXLS896x_ORIENT_THS_REG_HYS_69_21 ((uint8_t)0x07) /* L-to-P 69° P-to-L 21° */ 1346 /*------------------------------*/ 1347 1348 /*-------------------------------- 1349 ** Register: SDCD_INT_SRC1 1350 ** Enum: FXLS896x_SDCD_INT_SRC1 1351 ** -- 1352 ** Offset : 0x2D Sensor data change detection function 1. 1353 ** ------------------------------*/ 1354 typedef union 1355 { 1356 struct 1357 { 1358 uint8_t z_ot_pol : 1; /* Z-axis outside of thresholds polarity flag. */ 1359 1360 uint8_t z_ot_ef : 1; /* Z-axis data or delta outside of upper and lower thresholds event flag. */ 1361 1362 uint8_t y_ot_pol : 1; /* Y-axis outside of thresholds polarity flag. */ 1363 1364 uint8_t y_ot_ef : 1; /* Y-axis data or delta outside of upper and lower thresholds event flag. */ 1365 1366 uint8_t x_ot_pol : 1; /* X-axis outside of thresholds polarity flag. */ 1367 1368 uint8_t x_ot_ef : 1; /* X-axis data or delta outside of upper and lower thresholds event flag. */ 1369 1370 uint8_t _reserved_ : 1; 1371 uint8_t ot_ea : 1; /* SDCD outside of thresholds event active flag. */ 1372 1373 } b; 1374 uint8_t w; 1375 } FXLS896x_SDCD_INT_SRC1_t; 1376 1377 /* 1378 ** SDCD_INT_SRC1 - Bit field mask definitions 1379 */ 1380 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_MASK ((uint8_t)0x01) 1381 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_SHIFT ((uint8_t)0) 1382 1383 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_MASK ((uint8_t)0x02) 1384 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_SHIFT ((uint8_t)1) 1385 1386 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_MASK ((uint8_t)0x04) 1387 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_SHIFT ((uint8_t)2) 1388 1389 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_MASK ((uint8_t)0x08) 1390 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_SHIFT ((uint8_t)3) 1391 1392 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_MASK ((uint8_t)0x10) 1393 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_SHIFT ((uint8_t)4) 1394 1395 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_MASK ((uint8_t)0x20) 1396 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_SHIFT ((uint8_t)5) 1397 1398 #define FXLS896x_SDCD_INT_SRC1_OT_EA_MASK ((uint8_t)0x80) 1399 #define FXLS896x_SDCD_INT_SRC1_OT_EA_SHIFT ((uint8_t)7) 1400 1401 /* 1402 ** SDCD_INT_SRC1 - Bit field value definitions 1403 */ 1404 #define FXLS896x_SDCD_INT_SRC1_OT_EA_INSIDE ((uint8_t)0x00) /* Event flag has not been asserted. */ 1405 #define FXLS896x_SDCD_INT_SRC1_OT_EA_OUTSIDE ((uint8_t)0x80) /* Event flag has been asserted. */ 1406 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */ 1407 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_EVENT_YES ((uint8_t)0x20) /* Event has occured. */ 1408 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */ 1409 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_GT_THS ((uint8_t)0x10) /* Greater than upper threshold. */ 1410 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */ 1411 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_EVENT_YES ((uint8_t)0x08) /* Event has occured. */ 1412 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */ 1413 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_GT_THS ((uint8_t)0x04) /* Greater than upper threshold. */ 1414 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */ 1415 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_EVENT_YES ((uint8_t)0x02) /* Event has occured. */ 1416 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */ 1417 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_GT_THS ((uint8_t)0x01) /* Greater than upper threshold. */ 1418 /*------------------------------*/ 1419 1420 /*-------------------------------- 1421 ** Register: SDCD_INT_SRC2 1422 ** Enum: FXLS896x_SDCD_INT_SRC2 1423 ** -- 1424 ** Offset : 0x2E Sensor data change detection function 2. 1425 ** ------------------------------*/ 1426 typedef union 1427 { 1428 struct 1429 { 1430 uint8_t _reserved_ : 1; 1431 uint8_t z_wt_ef : 1; /* Z-axis data or delta inside of upper and lower thresholds event flag. */ 1432 1433 uint8_t _reserved_1 : 1; 1434 uint8_t y_wt_ef : 1; /* Y-axis data or delta inside of upper and lower thresholds event flag. */ 1435 1436 uint8_t _reserved_2 : 1; 1437 uint8_t x_wt_ef : 1; /* X-axis data or delta inside of upper and lower thresholds event flag. */ 1438 1439 uint8_t _reserved_3 : 1; 1440 uint8_t wt_ea : 1; /* SDCD within-thresholds event active flag. */ 1441 1442 } b; 1443 uint8_t w; 1444 } FXLS896x_SDCD_INT_SRC2_t; 1445 1446 /* 1447 ** SDCD_INT_SRC2 - Bit field mask definitions 1448 */ 1449 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_MASK ((uint8_t)0x02) 1450 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_SHIFT ((uint8_t)1) 1451 1452 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_MASK ((uint8_t)0x08) 1453 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_SHIFT ((uint8_t)3) 1454 1455 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_MASK ((uint8_t)0x20) 1456 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_SHIFT ((uint8_t)5) 1457 1458 #define FXLS896x_SDCD_INT_SRC2_WT_EA_MASK ((uint8_t)0x80) 1459 #define FXLS896x_SDCD_INT_SRC2_WT_EA_SHIFT ((uint8_t)7) 1460 1461 /* 1462 ** SDCD_INT_SRC2 - Bit field value definitions 1463 */ 1464 #define FXLS896x_SDCD_INT_SRC2_WT_EA_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */ 1465 #define FXLS896x_SDCD_INT_SRC2_WT_EA_EVENT_YES ((uint8_t)0x80) /* Event has occured. */ 1466 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_IN_RANGE ((uint8_t)0x00) /* X-axis data or delta is >= SDCD_UTHS or =< */ 1467 /* SDCD_LTHS values. */ 1468 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_OUT_RANGE ((uint8_t)0x20) /* X-axis data or delta is < SDCD_UTHS and > */ 1469 /* SDCD_LTHS value. */ 1470 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_IN_RANGE ((uint8_t)0x00) /* Y-axis data or delta is >= SDCD_UTHS or =< */ 1471 /* SDCD_LTHS values. */ 1472 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_OUT_RANGE ((uint8_t)0x08) /* Y-axis data or delta is < SDCD_UTHS and > */ 1473 /* SDCD_LTHS value. */ 1474 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_IN_RANGE ((uint8_t)0x00) /* Z-axis data or delta is >= SDCD_UTHS or =< */ 1475 /* SDCD_LTHS values. */ 1476 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_OUT_RANGE ((uint8_t)0x02) /* Z-axis data or delta is < SDCD_UTHS and > */ 1477 /* SDCD_LTHS value. */ 1478 /*------------------------------*/ 1479 1480 /*-------------------------------- 1481 ** Register: SDCD_CONFIG1 1482 ** Enum: FXLS896x_SDCD_CONFIG1 1483 ** -- 1484 ** Offset : 0x2F Sensor data change detection function 1 register. 1485 ** ------------------------------*/ 1486 typedef union 1487 { 1488 struct 1489 { 1490 uint8_t z_wt_en : 1; /* SDCD function Z-axis within thresholds condition enable. */ 1491 1492 uint8_t y_wt_en : 1; /* SDCD function Y-axis within thresholds condition enable. */ 1493 1494 uint8_t x_wt_en : 1; /* SDCD function X-axis within thresholds condition enable. */ 1495 1496 uint8_t z_ot_en : 1; /* SDCD function Z-axis outside of thresholds condition enable. */ 1497 1498 uint8_t y_ot_en : 1; /* SDCD function Y-axis outside of thresholds condition enable. */ 1499 1500 uint8_t x_ot_en : 1; /* SDCD function X-axis outside of thresholds condition enable. */ 1501 1502 uint8_t wt_ele : 1; /* SDCD within thresholds event latch enable. */ 1503 1504 uint8_t ot_ele : 1; /* SDCD outside of thresholds event latch enable. */ 1505 1506 } b; 1507 uint8_t w; 1508 } FXLS896x_SDCD_CONFIG1_t; 1509 1510 /* 1511 ** SDCD_CONFIG1 - Bit field mask definitions 1512 */ 1513 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_MASK ((uint8_t)0x01) 1514 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_SHIFT ((uint8_t)0) 1515 1516 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_MASK ((uint8_t)0x02) 1517 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_SHIFT ((uint8_t)1) 1518 1519 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_MASK ((uint8_t)0x04) 1520 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_SHIFT ((uint8_t)2) 1521 1522 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_MASK ((uint8_t)0x08) 1523 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_SHIFT ((uint8_t)3) 1524 1525 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_MASK ((uint8_t)0x10) 1526 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_SHIFT ((uint8_t)4) 1527 1528 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_MASK ((uint8_t)0x20) 1529 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_SHIFT ((uint8_t)5) 1530 1531 #define FXLS896x_SDCD_CONFIG1_WT_ELE_MASK ((uint8_t)0x40) 1532 #define FXLS896x_SDCD_CONFIG1_WT_ELE_SHIFT ((uint8_t)6) 1533 1534 #define FXLS896x_SDCD_CONFIG1_OT_ELE_MASK ((uint8_t)0x80) 1535 #define FXLS896x_SDCD_CONFIG1_OT_ELE_SHIFT ((uint8_t)7) 1536 1537 /* 1538 ** SDCD_CONFIG1 - Bit field value definitions 1539 */ 1540 #define FXLS896x_SDCD_CONFIG1_OT_ELE_DIS ((uint8_t)0x00) /* Outside of thresholds event flag latching is */ 1541 /* disabled. */ 1542 #define FXLS896x_SDCD_CONFIG1_OT_ELE_EN ((uint8_t)0x80) /* Outside of thresholds event flag latching is */ 1543 /* enabled. */ 1544 #define FXLS896x_SDCD_CONFIG1_WT_ELE_DIS ((uint8_t)0x00) /* Within thresholds event flag latching is */ 1545 /* disabled. */ 1546 #define FXLS896x_SDCD_CONFIG1_WT_ELE_EN ((uint8_t)0x40) /* Within thresholds event flag latching is */ 1547 /* enabled. */ 1548 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */ 1549 /* of thresholds condition evaluation. */ 1550 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_EN ((uint8_t)0x20) /* X-axis data or delta is used in the outside of */ 1551 /* thresholds condition evaluation. */ 1552 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */ 1553 /* of thresholds condition evaluation. */ 1554 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_EN ((uint8_t)0x10) /* Y-axis data or delta is used in the outside of */ 1555 /* thresholds condition evaluation. */ 1556 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */ 1557 /* of thresholds condition evaluation. */ 1558 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_EN ((uint8_t)0x08) /* Z-axis data or delta is used in the outside of */ 1559 /* thresholds condition evaluation. */ 1560 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */ 1561 /* of thresholds condition evaluation. */ 1562 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_EN ((uint8_t)0x04) /* X-axis data or delta is used in the outside of */ 1563 /* thresholds condition evaluation. */ 1564 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */ 1565 /* of thresholds condition evaluation. */ 1566 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_EN ((uint8_t)0x02) /* Y-axis data or delta is used in the outside of */ 1567 /* thresholds condition evaluation. */ 1568 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */ 1569 /* of thresholds condition evaluation. */ 1570 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_EN ((uint8_t)0x01) /* Z-axis data or delta is used in the outside of */ 1571 /* thresholds condition evaluation. */ 1572 /*------------------------------*/ 1573 1574 /*-------------------------------- 1575 ** Register: SDCD_CONFIG2 1576 ** Enum: FXLS896x_SDCD_CONFIG2 1577 ** -- 1578 ** Offset : 0x30 Sensor data change detection function 2 register. 1579 ** ------------------------------*/ 1580 typedef union 1581 { 1582 struct 1583 { 1584 uint8_t ref_upd : 1; /* SDCD synchronous X/Y/Z reference values update bit. */ 1585 1586 uint8_t mode : 1; /* SDCD input data mode. */ 1587 1588 uint8_t wt_log_sel : 1; /* SDCD within thresholds event logic selection. */ 1589 1590 uint8_t wt_dbctm : 1; /* SDCD within thresholds event debounce counter behavior. */ 1591 1592 uint8_t ot_dbctm : 1; /* SDCD outside of threshold event debounce counter behavior. */ 1593 1594 uint8_t ref_updm : 2; /* SDCD internal reference values update mode. */ 1595 1596 uint8_t sdcd_en : 1; /* SDCD function. */ 1597 1598 } b; 1599 uint8_t w; 1600 } FXLS896x_SDCD_CONFIG2_t; 1601 1602 /* 1603 ** SDCD_CONFIG2 - Bit field mask definitions 1604 */ 1605 #define FXLS896x_SDCD_CONFIG2_REF_UPD_MASK ((uint8_t)0x01) 1606 #define FXLS896x_SDCD_CONFIG2_REF_UPD_SHIFT ((uint8_t)0) 1607 1608 #define FXLS896x_SDCD_CONFIG2_MODE_MASK ((uint8_t)0x02) 1609 #define FXLS896x_SDCD_CONFIG2_MODE_SHIFT ((uint8_t)1) 1610 1611 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_MASK ((uint8_t)0x04) 1612 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_SHIFT ((uint8_t)2) 1613 1614 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_MASK ((uint8_t)0x08) 1615 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_SHIFT ((uint8_t)3) 1616 1617 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_MASK ((uint8_t)0x10) 1618 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_SHIFT ((uint8_t)4) 1619 1620 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_MASK ((uint8_t)0x60) 1621 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_SHIFT ((uint8_t)5) 1622 1623 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_MASK ((uint8_t)0x80) 1624 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_SHIFT ((uint8_t)7) 1625 1626 /* 1627 ** SDCD_CONFIG2 - Bit field value definitions 1628 */ 1629 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_DIS ((uint8_t)0x00) /* SDCD function is disabled. */ 1630 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_EN ((uint8_t)0x80) /* SDCD function is Enabled. */ 1631 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_12_BIT ((uint8_t)0x00) /* The function stores the first 12-bit X/Y/Z */ 1632 /* decimated and trimmed input data. */ 1633 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_FIRST ((uint8_t)0x20) /* The function stores the first decimated and */ 1634 /* trimmed X/Y/Z acceleration input data. */ 1635 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_SDCD_REF ((uint8_t)0x40) /* The function updates the SDCD_REF_X/Y/Z values */ 1636 /* with the current decimated and trimmed X/Y/Z */ 1637 /* acceleration input data after the function */ 1638 /* evaluation. */ 1639 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_FIXED_VAL ((uint8_t)0x60) /* The function uses a fixed value of 0 for each */ 1640 /* of the SDCD_REF_X/Y/Z registers. */ 1641 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */ 1642 /* current outside of thresholds result for the */ 1643 /* enabled axes is false. */ 1644 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_CLEARED ((uint8_t)0x10) /* Debounce counter is cleared whenever the */ 1645 /* current outside of thresholds result for the */ 1646 /* enabled axes is false. */ 1647 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */ 1648 /* current outside of thresholds result for the */ 1649 /* enabled axes is false. */ 1650 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_CLEARED ((uint8_t)0x08) /* Debounce counter is cleared whenever the */ 1651 /* current outside of thresholds result for the */ 1652 /* enabled axes is false. */ 1653 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_AND ((uint8_t)0x00) /* Function uses the logical AND of the enabled */ 1654 /* axes. */ 1655 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_OR ((uint8_t)0x04) /* Function uses the logical OR of the enabled */ 1656 /* axes. */ 1657 #define FXLS896x_SDCD_CONFIG2_MODE_XYZ ((uint8_t)0x00) /* Function uses X, Y, Z acceleration data for the */ 1658 /* window comparison. */ 1659 #define FXLS896x_SDCD_CONFIG2_MODE_VECM ((uint8_t)0x02) /* Function uses Vector magnitude data for the */ 1660 /* window comparison on the X-axis channel only. */ 1661 #define FXLS896x_SDCD_CONFIG2_REF_UPD_NO_PENDING \ 1662 ((uint8_t)0x00) /* No reference update pending or reference update \ \ \ 1663 */ 1664 /* has completed. */ 1665 #define FXLS896x_SDCD_CONFIG2_REF_UPD_SYNC_UPDATE ((uint8_t)0x01) /* Triggers a synchronous update of the internal */ 1666 /* X/Y/Z reference registers. */ 1667 /*------------------------------*/ 1668 1669 /*-------------------------------- 1670 ** Register: SDCD_OT_DBCNT 1671 ** Enum: FXLS896x_SDCD_OT_DBCNT 1672 ** -- 1673 ** Offset : 0x31 Sensor Data Change Detection outside of thresholds condition debounce count value. 1674 ** ------------------------------*/ 1675 typedef uint8_t FXLS896x_SDCD_OT_DBCNT_t; 1676 1677 /*-------------------------------- 1678 ** Register: SDCD_WT_DBCNT 1679 ** Enum: FXLS896x_SDCD_WT_DBCNT 1680 ** -- 1681 ** Offset : 0x32 Sensor Data Change Detection within thresholds condition debounce count value. 1682 ** ------------------------------*/ 1683 typedef uint8_t FXLS896x_SDCD_WT_DBCNT_t; 1684 1685 /*-------------------------------- 1686 ** Register: SDCD_LTHS_LSB 1687 ** Enum: FXLS896x_SDCD_LTHS_LSB 1688 ** -- 1689 ** Offset : 0x33 Sensor Data Change Detection lower threshold value LSB. 1690 ** ------------------------------*/ 1691 typedef uint8_t FXLS896x_SDCD_LTHS_LSB_t; 1692 1693 /*-------------------------------- 1694 ** Register: SDCD_LTHS_MSB 1695 ** Enum: FXLS896x_SDCD_LTHS_MSB 1696 ** -- 1697 ** Offset : 0x34 Sensor Data change Detection lower threshold value MSB. 1698 ** ------------------------------*/ 1699 typedef uint8_t FXLS896x_SDCD_LTHS_MSB_t; 1700 1701 /*-------------------------------- 1702 ** Register: SDCD_UTHS_LSB 1703 ** Enum: FXLS896x_SDCD_UTHS_LSB 1704 ** -- 1705 ** Offset : 0x35 Sensor Data change detection upper threshold value LSB. 1706 ** ------------------------------*/ 1707 typedef uint8_t FXLS896x_SDCD_UTHS_LSB_t; 1708 1709 /*-------------------------------- 1710 ** Register: SDCD_UTHS_MSB 1711 ** Enum: FXLS896x_SDCD_UTHS_MSB 1712 ** -- 1713 ** Offset : 0x36 Sensor Data change detection upper threshold value MSB. 1714 ** ------------------------------*/ 1715 typedef uint8_t FXLS896x_SDCD_UTHS_MSB_t; 1716 1717 1718 /*-------------------------------- 1719 ** Register: SELF_TEST_CONFIG1 1720 ** Enum: FXLS896x_SELF_TEST_CONFIG1 1721 ** -- 1722 ** Offset : 0x37 Self Test Configuration function 1 register. 1723 ** ------------------------------*/ 1724 typedef union 1725 { 1726 struct 1727 { 1728 uint8_t st_idle : 5; /* Self-Test Idle phase duration. */ 1729 1730 } b; 1731 uint8_t w; 1732 } FXLS896x_SELF_TEST_CONFIG1_t; 1733 1734 /* 1735 ** SELF_TEST_CONFIG1 - Bit field mask definitions 1736 */ 1737 #define FXLS896x_SELF_TEST_CONFIG1_ST_IDLE_MASK ((uint8_t)0x1f) 1738 #define FXLS896x_SELF_TEST_CONFIG1_ST_IDLE_SHIFT ((uint8_t)0) 1739 1740 1741 /*-------------------------------- 1742 ** Register: SELF_TEST_CONFIG2 1743 ** Enum: FXLS896x_SELF_TEST_CONFIG2 1744 ** -- 1745 ** Offset : 0x38 Self Test Configuration function 2 register. 1746 ** ------------------------------*/ 1747 typedef union 1748 { 1749 struct 1750 { 1751 uint8_t st_dec : 4; /* Self-Test measurement phase decimation factor. */ 1752 1753 } b; 1754 uint8_t w; 1755 } FXLS896x_SELF_TEST_CONFIG2_t; 1756 1757 /* 1758 ** SELF_TEST_CONFIG2 - Bit field mask definitions 1759 */ 1760 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_MASK ((uint8_t)0x0f) 1761 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_SHIFT ((uint8_t)0) 1762 1763 /* 1764 ** SELF_TEST_CONFIG2 - Bit field value definitions 1765 */ 1766 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_1 ((uint8_t)0x00) 1767 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_2 ((uint8_t)0x01) 1768 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_4 ((uint8_t)0x02) 1769 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_8 ((uint8_t)0x03) 1770 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_16 ((uint8_t)0x04) 1771 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_32 ((uint8_t)0x05) 1772 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_64 ((uint8_t)0x06) 1773 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_128 ((uint8_t)0x07) 1774 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_256 ((uint8_t)0x08) 1775 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_512 ((uint8_t)0x09) 1776 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_1024 ((uint8_t)0x0a) 1777 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_2048 ((uint8_t)0x0b) 1778 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_4096 ((uint8_t)0x0c) 1779 1780 1781 #endif /* FXLS896X_H_ */ 1782
