1 /* 2 * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 /** 10 * @file fxas21002.h 11 * @brief The fxas21002.h contains the fxas21002 sensor register definitions and its bit mask. 12 */ 13 14 #ifndef FXAS21002_H_ 15 #define FXAS21002_H_ 16 17 /** 18 ** FXAS21002 I2C Address 19 */ 20 #define FXAS21002_I2C_ADDRESS 0x20 21 22 /** 23 ** 24 ** @brief The FXAS21002 Sensor Register Map. 25 */ 26 enum { 27 FXAS21002_STATUS = 0x00, 28 FXAS21002_OUT_X_MSB = 0x01, 29 FXAS21002_OUT_X_LSB = 0x02, 30 FXAS21002_OUT_Y_MSB = 0x03, 31 FXAS21002_OUT_Y_LSB = 0x04, 32 FXAS21002_OUT_Z_MSB = 0x05, 33 FXAS21002_OUT_Z_LSB = 0x06, 34 FXAS21002_DR_STATUS = 0x07, 35 FXAS21002_F_STATUS = 0x08, 36 FXAS21002_F_SETUP = 0x09, 37 FXAS21002_F_EVENT = 0x0A, 38 FXAS21002_INT_SRC_FLAG = 0x0B, 39 FXAS21002_WHO_AM_I = 0x0C, 40 FXAS21002_CTRL_REG0 = 0x0D, 41 FXAS21002_RT_CFG = 0x0E, 42 FXAS21002_RT_SRC = 0x0F, 43 FXAS21002_RT_THS = 0x10, 44 FXAS21002_RT_COUNT = 0x11, 45 FXAS21002_TEMP = 0x12, 46 FXAS21002_CTRL_REG1 = 0x13, 47 FXAS21002_CTRL_REG2 = 0x14, 48 FXAS21002_CTRL_REG3 = 0x15, 49 }; 50 51 52 /*-------------------------------- 53 ** Register: STATUS 54 ** Enum: FXAS21002_STATUS 55 ** -- 56 ** Offset : 0x00 - Alias for DR_STATUS or F_STATUS. 57 ** ------------------------------*/ 58 typedef uint8_t FXAS21002_STATUS_t; 59 60 61 62 /*-------------------------------- 63 ** Register: OUT_X_MSB 64 ** Enum: FXAS21002_OUT_X_MSB 65 ** -- 66 ** Offset : 0x01 - 8 MSBs of 16 bit X-axis data sample 67 ** ------------------------------*/ 68 typedef uint8_t FXAS21002_OUT_X_MSB_t; 69 70 71 /*-------------------------------- 72 ** Register: OUT_X_LSB 73 ** Enum: FXAS21002_OUT_X_LSB 74 ** -- 75 ** Offset : 0x02 - 8 LSBs of 16 bit X-axis data sample 76 ** ------------------------------*/ 77 typedef uint8_t FXAS21002_OUT_X_LSB_t; 78 79 80 81 /*-------------------------------- 82 ** Register: OUT_Y_MSB 83 ** Enum: FXAS21002_OUT_Y_MSB 84 ** -- 85 ** Offset : 0x03 - 8 MSBs of 16 bit Y-axis data sample 86 ** ------------------------------*/ 87 typedef uint8_t FXAS21002_OUT_Y_MSB_t; 88 89 90 /*-------------------------------- 91 ** Register: OUT_Y_LSB 92 ** Enum: FXAS21002_OUT_Y_LSB 93 ** -- 94 ** Offset : 0x04 - 8 LSBs of 16 bit Y-axis data sample 95 ** ------------------------------*/ 96 typedef uint8_t FXAS21002_OUT_Y_LSB_t; 97 98 99 100 /*-------------------------------- 101 ** Register: OUT_Z_MSB 102 ** Enum: FXAS21002_OUT_Z_MSB 103 ** -- 104 ** Offset : 0x05 - 8 MSBs of 16 bit Z-axis data sample 105 ** ------------------------------*/ 106 typedef uint8_t FXAS21002_OUT_Z_MSB_t; 107 108 109 /*-------------------------------- 110 ** Register: OUT_Z_LSB 111 ** Enum: FXAS21002_OUT_Z_LSB 112 ** -- 113 ** Offset : 0x06 - 8 LSBs of 16 bit Z-axis data sample 114 ** ------------------------------*/ 115 typedef uint8_t FXAS21002_OUT_Z_LSB_t; 116 117 118 119 /*-------------------------------- 120 ** Register: DR_STATUS 121 ** Enum: FXAS21002_DR_STATUS 122 ** -- 123 ** Offset : 0x07 - Data-ready status information (FIFO disabled by setting F_SETUP :: F_MODE = 0) 124 ** ------------------------------*/ 125 typedef union { 126 struct { 127 uint8_t xdr : 1; /* X-axis new data available. */ 128 129 uint8_t ydr : 1; /* Y-axis new data available. */ 130 131 uint8_t zdr : 1; /* Z-axis new data available. */ 132 133 uint8_t zyxdr : 1; /* X-, Y-, and Z-axis data available. */ 134 135 uint8_t xow : 1; /* X-axis data overwrite. */ 136 137 uint8_t yow : 1; /* Y-axis data overwrite. */ 138 139 uint8_t zow : 1; /* Z-axis data overwrite. */ 140 141 uint8_t zyxow : 1; /* X-, Y-, Z-axis data overwrite. */ 142 143 } b; 144 uint8_t w; 145 } FXAS21002_DR_STATUS_t; 146 147 148 /* 149 ** DR_STATUS - Bit field mask definitions 150 */ 151 #define FXAS21002_DR_STATUS_XDR_MASK ((uint8_t) 0x01) 152 #define FXAS21002_DR_STATUS_XDR_SHIFT ((uint8_t) 0) 153 154 #define FXAS21002_DR_STATUS_YDR_MASK ((uint8_t) 0x02) 155 #define FXAS21002_DR_STATUS_YDR_SHIFT ((uint8_t) 1) 156 157 #define FXAS21002_DR_STATUS_ZDR_MASK ((uint8_t) 0x04) 158 #define FXAS21002_DR_STATUS_ZDR_SHIFT ((uint8_t) 2) 159 160 #define FXAS21002_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08) 161 #define FXAS21002_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3) 162 163 #define FXAS21002_DR_STATUS_XOW_MASK ((uint8_t) 0x10) 164 #define FXAS21002_DR_STATUS_XOW_SHIFT ((uint8_t) 4) 165 166 #define FXAS21002_DR_STATUS_YOW_MASK ((uint8_t) 0x20) 167 #define FXAS21002_DR_STATUS_YOW_SHIFT ((uint8_t) 5) 168 169 #define FXAS21002_DR_STATUS_ZOW_MASK ((uint8_t) 0x40) 170 #define FXAS21002_DR_STATUS_ZOW_SHIFT ((uint8_t) 6) 171 172 #define FXAS21002_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80) 173 #define FXAS21002_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7) 174 175 176 /* 177 ** DR_STATUS - Bit field value definitions 178 */ 179 #define FXAS21002_DR_STATUS_XDR_DRDY ((uint8_t) 0x01) /* Set to 1 whenever a new X-axis data acquisition */ 180 /* is completed. Cleared anytime the OUT_X_MSB */ 181 /* register is read. */ 182 #define FXAS21002_DR_STATUS_YDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a new Y-axis data acquisition */ 183 /* is completed. Cleared anytime the OUT_Y_MSB */ 184 /* register is read. */ 185 #define FXAS21002_DR_STATUS_ZDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Z-axis data acquisition */ 186 /* is completed. Cleared anytime the OUT_Z_MSB */ 187 /* register is read. */ 188 #define FXAS21002_DR_STATUS_ZYXDR_DRDY ((uint8_t) 0x08) /* Cleared when the high-bytes of the acceleration */ 189 /* data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. */ 190 #define FXAS21002_DR_STATUS_XOW_OWR ((uint8_t) 0x10) /* Asserted whenever a new X-axis acquisition is */ 191 /* completed before the retrieval of the previous */ 192 /* data. */ 193 #define FXAS21002_DR_STATUS_YOW_OWR ((uint8_t) 0x20) /* Asserted whenever a new Y-axis acquisition is */ 194 /* completed before the retrieval of the previous */ 195 /* data. */ 196 #define FXAS21002_DR_STATUS_ZOW_OWR ((uint8_t) 0x40) /* Asserted whenever a new Z-axis acquisition is */ 197 /* completed before the retrieval of the previous */ 198 /* data. */ 199 #define FXAS21002_DR_STATUS_ZYXOW_OWR ((uint8_t) 0x80) /* Asserted whenever new X-, Y-, and Z-axis data is */ 200 /* acquired before completing the retrieval of the */ 201 /* previous set. */ 202 /*------------------------------*/ 203 204 205 206 /*-------------------------------- 207 ** Register: F_STATUS 208 ** Enum: FXAS21002_F_STATUS 209 ** -- 210 ** Offset : 0x08 - FIFO status information (FIFO enabled by setting F_SETUP :: F_MODE > 0) 211 ** ------------------------------*/ 212 typedef union { 213 struct { 214 uint8_t f_cnt : 6; /* FIFO sample counter; indicates the number of samples currently stored in */ 215 /* the FIFO. */ 216 217 uint8_t f_wmkf : 1; /* FIFO sample count greater than or equal to the watermark count (F_SETUP :: */ 218 /* F_WMRK) has been detected. */ 219 220 uint8_t f_ovf : 1; /* FIFO overflow event, such as when F_CNT = 32 and a new sample arrives, */ 221 /* asserts the F_OVF flag. */ 222 223 } b; 224 uint8_t w; 225 } FXAS21002_F_STATUS_t; 226 227 228 /* 229 ** F_STATUS - Bit field mask definitions 230 */ 231 #define FXAS21002_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F) 232 #define FXAS21002_F_STATUS_F_CNT_SHIFT ((uint8_t) 0) 233 234 #define FXAS21002_F_STATUS_F_WMKF_MASK ((uint8_t) 0x40) 235 #define FXAS21002_F_STATUS_F_WMKF_SHIFT ((uint8_t) 6) 236 237 #define FXAS21002_F_STATUS_F_OVF_MASK ((uint8_t) 0x80) 238 #define FXAS21002_F_STATUS_F_OVF_SHIFT ((uint8_t) 7) 239 240 241 /* 242 ** F_STATUS - Bit field value definitions 243 */ 244 #define FXAS21002_F_STATUS_F_WMKF_DETECT ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */ 245 #define FXAS21002_F_STATUS_F_OVF_DETECT ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */ 246 /*------------------------------*/ 247 248 249 250 /*-------------------------------- 251 ** Register: F_SETUP 252 ** Enum: FXAS21002_F_SETUP 253 ** -- 254 ** Offset : 0x09 - FIFO configuration 255 ** ------------------------------*/ 256 typedef union { 257 struct { 258 uint8_t f_wmrk : 6; /* FIFO operating mode selection. */ 259 260 uint8_t f_mode : 2; /* FIFO sample count watermark setting. */ 261 262 } b; 263 uint8_t w; 264 } FXAS21002_F_SETUP_t; 265 266 267 /* 268 ** F_SETUP - Bit field mask definitions 269 */ 270 #define FXAS21002_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F) 271 #define FXAS21002_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0) 272 273 #define FXAS21002_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0) 274 #define FXAS21002_F_SETUP_F_MODE_SHIFT ((uint8_t) 6) 275 276 277 /* 278 ** F_SETUP - Bit field value definitions 279 */ 280 #define FXAS21002_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */ 281 #define FXAS21002_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO is in Circular Buffer mode. */ 282 #define FXAS21002_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO is in Stop mode. */ 283 /*------------------------------*/ 284 285 286 287 /*-------------------------------- 288 ** Register: F_EVENT 289 ** Enum: FXAS21002_F_EVENT 290 ** -- 291 ** Offset : 0x0A - FIFO event status 292 ** ------------------------------*/ 293 typedef union { 294 struct { 295 uint8_t fe_time : 5; /* Number of ODR periods elapsed since F_EVENT was set. */ 296 297 uint8_t f_event : 1; /* FIFO Event: Indicates if either F_WMKF or F_OVF flags are set (logical */ 298 /* OR). */ 299 300 } b; 301 uint8_t w; 302 } FXAS21002_F_EVENT_t; 303 304 305 /* 306 ** F_EVENT - Bit field mask definitions 307 */ 308 #define FXAS21002_F_EVENT_FE_TIME_MASK ((uint8_t) 0x1F) 309 #define FXAS21002_F_EVENT_FE_TIME_SHIFT ((uint8_t) 0) 310 311 #define FXAS21002_F_EVENT_F_EVENT_MASK ((uint8_t) 0x20) 312 #define FXAS21002_F_EVENT_F_EVENT_SHIFT ((uint8_t) 5) 313 314 315 /* 316 ** F_EVENT - Bit field value definitions 317 */ 318 #define FXAS21002_F_EVENT_F_EVENT_DETECTED ((uint8_t) 0x20) /* FIFO event was detected */ 319 /*------------------------------*/ 320 321 322 323 /*-------------------------------- 324 ** Register: INT_SRC_FLAG 325 ** Enum: FXAS21002_INT_SRC_FLAG 326 ** -- 327 ** Offset : 0x0B - Interrupt source status 328 ** ------------------------------*/ 329 typedef union { 330 struct { 331 uint8_t src_drdy : 1; /* Data ready event source flag. */ 332 333 uint8_t src_rt : 1; /* Rate threshold event source flag. */ 334 335 uint8_t src_fifo : 1; /* FIFO event source flag. */ 336 337 uint8_t bootend : 1; /* Boot sequence complete event flag. */ 338 339 } b; 340 uint8_t w; 341 } FXAS21002_INT_SRC_FLAG_t; 342 343 344 /* 345 ** INT_SRC_FLAG - Bit field mask definitions 346 */ 347 #define FXAS21002_INT_SRC_FLAG_SRC_DRDY_MASK ((uint8_t) 0x01) 348 #define FXAS21002_INT_SRC_FLAG_SRC_DRDY_SHIFT ((uint8_t) 0) 349 350 #define FXAS21002_INT_SRC_FLAG_SRC_RT_MASK ((uint8_t) 0x02) 351 #define FXAS21002_INT_SRC_FLAG_SRC_RT_SHIFT ((uint8_t) 1) 352 353 #define FXAS21002_INT_SRC_FLAG_SRC_FIFO_MASK ((uint8_t) 0x04) 354 #define FXAS21002_INT_SRC_FLAG_SRC_FIFO_SHIFT ((uint8_t) 2) 355 356 #define FXAS21002_INT_SRC_FLAG_BOOTEND_MASK ((uint8_t) 0x08) 357 #define FXAS21002_INT_SRC_FLAG_BOOTEND_SHIFT ((uint8_t) 3) 358 359 360 /* 361 ** INT_SRC_FLAG - Bit field value definitions 362 */ 363 #define FXAS21002_INT_SRC_FLAG_SRC_DRDY_READY ((uint8_t) 0x01) /* Asserted whenever a data-ready event triggers */ 364 /* the interrupt. */ 365 #define FXAS21002_INT_SRC_FLAG_SRC_RT_THRESH ((uint8_t) 0x02) /* Indicates that the rate threshold event flag */ 366 /* triggered the interrupt. */ 367 #define FXAS21002_INT_SRC_FLAG_SRC_FIFO_EVENT ((uint8_t) 0x04) /* F_OVF or F_WMKF are set, provided the FIFO */ 368 /* interrupt is enabled. */ 369 #define FXAS21002_INT_SRC_FLAG_BOOTEND_BOOT_DONE ((uint8_t) 0x08) /* Boot sequence is complete. */ 370 /*------------------------------*/ 371 372 373 374 /*-------------------------------- 375 ** Register: WHO_AM_I 376 ** Enum: FXAS21002_WHO_AM_I 377 ** -- 378 ** Offset : 0x0C - The WHO_AM_I register contains the device idenifier. 379 ** ------------------------------*/ 380 typedef union { 381 struct { 382 uint8_t whoami; /* The WHO_AM_I register contains the device identifier which is factory */ 383 /* programmed. */ 384 385 } b; 386 uint8_t w; 387 } FXAS21002_WHO_AM_I_t; 388 389 390 /* 391 ** WHO_AM_I - Bit field mask definitions 392 */ 393 #define FXAS21002_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF) 394 #define FXAS21002_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0) 395 396 397 /* 398 ** WHO_AM_I - Bit field value definitions 399 */ 400 #define FXAS21002_WHO_AM_I_WHOAMI_OLD_VALUE ((uint8_t) 0xd1) /* FXAS21000 */ 401 #define FXAS21002_WHO_AM_I_WHOAMI_PRE_VALUE ((uint8_t) 0xd6) /* Engineering Samples */ 402 #define FXAS21002_WHO_AM_I_WHOAMI_PROD_VALUE ((uint8_t) 0xd7) /* FXAS21002 Rev 2.1 (production) */ 403 /*------------------------------*/ 404 405 406 407 /*-------------------------------- 408 ** Register: CTRL_REG0 409 ** -- 410 ** Offset : 0x0D - Used for general control and configuration. 411 ** ------------------------------*/ 412 typedef union { 413 struct { 414 uint8_t fs : 2; /* Full-scale range selection. */ 415 416 uint8_t hpf_en : 1; /* High-pass filter enable. The high-pass filter is initialized on operating */ 417 /* mode and ODR change. When enabled, the HPF is applied to the angular rate */ 418 /* data supplied to the output registers/FIFO and the embedded rate threshold */ 419 /* algorithm. */ 420 421 uint8_t sel : 2; /* High-pass filter cutoff frequency selection. */ 422 423 uint8_t spiw : 1; /* SPI interface mode selection. */ 424 425 uint8_t bw : 2; /* Bandwidth selects the cut-off frequency of the digital low-pass filter. */ 426 427 } b; 428 uint8_t w; 429 } FXAS21002_CTRL_REG0_t; 430 431 432 /* 433 ** CTRL_REG0 - Bit field mask definitions 434 */ 435 #define FXAS21002_CTRL_REG0_FS_MASK ((uint8_t) 0x03) 436 #define FXAS21002_CTRL_REG0_FS_SHIFT ((uint8_t) 0) 437 438 #define FXAS21002_CTRL_REG0_HPF_EN_MASK ((uint8_t) 0x04) 439 #define FXAS21002_CTRL_REG0_HPF_EN_SHIFT ((uint8_t) 2) 440 441 #define FXAS21002_CTRL_REG0_SEL_MASK ((uint8_t) 0x18) 442 #define FXAS21002_CTRL_REG0_SEL_SHIFT ((uint8_t) 3) 443 444 #define FXAS21002_CTRL_REG0_SPIW_MASK ((uint8_t) 0x20) 445 #define FXAS21002_CTRL_REG0_SPIW_SHIFT ((uint8_t) 5) 446 447 #define FXAS21002_CTRL_REG0_BW_MASK ((uint8_t) 0xC0) 448 #define FXAS21002_CTRL_REG0_BW_SHIFT ((uint8_t) 6) 449 450 451 /* 452 ** CTRL_REG0 - Bit field value definitions 453 */ 454 #define FXAS21002_CTRL_REG0_FS_DPS2000 ((uint8_t) 0x00) /* 2000 degrees per second (4000 dps if CTRL_REG3 : */ 455 /* FS_DOUBLE = 1). */ 456 #define FXAS21002_CTRL_REG0_FS_DPS1000 ((uint8_t) 0x01) /* 1000 degrees per second (2000 dps if CTRL_REG3 : */ 457 /* FS_DOUBLE = 1). */ 458 #define FXAS21002_CTRL_REG0_FS_DPS500 ((uint8_t) 0x02) /* 500 degrees per second (1000 dps if CTRL_REG3 : */ 459 /* FS_DOUBLE = 1). */ 460 #define FXAS21002_CTRL_REG0_FS_DPS250 ((uint8_t) 0x03) /* 250 degrees per second (500 dps if CTRL_REG3 : */ 461 /* FS_DOUBLE = 1). */ 462 #define FXAS21002_CTRL_REG0_HPF_EN_ENABLE ((uint8_t) 0x04) 463 #define FXAS21002_CTRL_REG0_HPF_EN_DISABLE ((uint8_t) 0x00) 464 #define FXAS21002_CTRL_REG0_SPIW_4WIRE ((uint8_t) 0x00) /* SPI 4-wire mode (default). */ 465 #define FXAS21002_CTRL_REG0_SPIW_3WIRE ((uint8_t) 0x20) /* SPI 3-wire mode (MOSI pin is used for SPI input */ 466 /* and output signals). */ 467 /*------------------------------*/ 468 469 470 471 /*-------------------------------- 472 ** Register: RT_CFG 473 ** Enum: FXAS21002_RT_CFG 474 ** -- 475 ** Offset : 0x0E - Used to enable the Rate Threshold interrupt generation. 476 ** ------------------------------*/ 477 typedef union { 478 struct { 479 uint8_t xtefe : 1; /* Event flag enable on X rate. */ 480 481 uint8_t ytefe : 1; /* Event flag enable on Y rate. */ 482 483 uint8_t ztefe : 1; /* Event flag enable on Z rate. */ 484 485 uint8_t ele : 1; /* Event latch enable. */ 486 487 } b; 488 uint8_t w; 489 } FXAS21002_RT_CFG_t; 490 491 492 /* 493 ** RT_CFG - Bit field mask definitions 494 */ 495 #define FXAS21002_RT_CFG_XTEFE_MASK ((uint8_t) 0x01) 496 #define FXAS21002_RT_CFG_XTEFE_SHIFT ((uint8_t) 0) 497 498 #define FXAS21002_RT_CFG_YTEFE_MASK ((uint8_t) 0x02) 499 #define FXAS21002_RT_CFG_YTEFE_SHIFT ((uint8_t) 1) 500 501 #define FXAS21002_RT_CFG_ZTEFE_MASK ((uint8_t) 0x04) 502 #define FXAS21002_RT_CFG_ZTEFE_SHIFT ((uint8_t) 2) 503 504 #define FXAS21002_RT_CFG_ELE_MASK ((uint8_t) 0x08) 505 #define FXAS21002_RT_CFG_ELE_SHIFT ((uint8_t) 3) 506 507 508 /* 509 ** RT_CFG - Bit field value definitions 510 */ 511 #define FXAS21002_RT_CFG_XTEFE_ENABLE ((uint8_t) 0x01) /* X event detection enabled. */ 512 #define FXAS21002_RT_CFG_XTEFE_DISABLE ((uint8_t) 0x00) /* X event detection disabled. */ 513 #define FXAS21002_RT_CFG_YTEFE_ENABLE ((uint8_t) 0x02) /* Y event detection enabled. */ 514 #define FXAS21002_RT_CFG_YTEFE_DISABLE ((uint8_t) 0x00) /* Y event detection disabled. */ 515 #define FXAS21002_RT_CFG_ZTEFE_ENABLE ((uint8_t) 0x04) /* Z event detection enabled. */ 516 #define FXAS21002_RT_CFG_ZTEFE_DISABLE ((uint8_t) 0x00) /* Z event detection disabled. */ 517 #define FXAS21002_RT_CFG_ELE_ENABLE ((uint8_t) 0x08) /* Event flag latch enabled. */ 518 #define FXAS21002_RT_CFG_ELE_DISABLE ((uint8_t) 0x00) /* Event flag latch disabled. */ 519 /*------------------------------*/ 520 521 522 523 /*-------------------------------- 524 ** Register: RT_SRC 525 ** Enum: FXAS21002_RT_SRC 526 ** -- 527 ** Offset : 0x0F - Indicates the source of the Rate Threshold event. It also clears the RT_SRC flag in the INT_SOURCE_FLAG register. 528 ** ------------------------------*/ 529 typedef union { 530 struct { 531 uint8_t x_rt_pol : 1; /* Polarity of X event. */ 532 533 uint8_t xrt : 1; /* X rate Event. */ 534 535 uint8_t y_rt_pol : 1; /* Polarity of Y event. */ 536 537 uint8_t yrt : 1; /* Y rate event. */ 538 539 uint8_t z_rt_pol : 1; /* Polarity of Z event. */ 540 541 uint8_t zrt : 1; /* Z rate event. */ 542 543 uint8_t ea : 1; /* Event active flag. */ 544 545 } b; 546 uint8_t w; 547 } FXAS21002_RT_SRC_t; 548 549 550 /* 551 ** RT_SRC - Bit field mask definitions 552 */ 553 #define FXAS21002_RT_SRC_X_RT_POL_MASK ((uint8_t) 0x01) 554 #define FXAS21002_RT_SRC_X_RT_POL_SHIFT ((uint8_t) 0) 555 556 #define FXAS21002_RT_SRC_XRT_MASK ((uint8_t) 0x02) 557 #define FXAS21002_RT_SRC_XRT_SHIFT ((uint8_t) 1) 558 559 #define FXAS21002_RT_SRC_Y_RT_POL_MASK ((uint8_t) 0x04) 560 #define FXAS21002_RT_SRC_Y_RT_POL_SHIFT ((uint8_t) 2) 561 562 #define FXAS21002_RT_SRC_YRT_MASK ((uint8_t) 0x08) 563 #define FXAS21002_RT_SRC_YRT_SHIFT ((uint8_t) 3) 564 565 #define FXAS21002_RT_SRC_Z_RT_POL_MASK ((uint8_t) 0x10) 566 #define FXAS21002_RT_SRC_Z_RT_POL_SHIFT ((uint8_t) 4) 567 568 #define FXAS21002_RT_SRC_ZRT_MASK ((uint8_t) 0x20) 569 #define FXAS21002_RT_SRC_ZRT_SHIFT ((uint8_t) 5) 570 571 #define FXAS21002_RT_SRC_EA_MASK ((uint8_t) 0x40) 572 #define FXAS21002_RT_SRC_EA_SHIFT ((uint8_t) 6) 573 574 575 /* 576 ** RT_SRC - Bit field value definitions 577 */ 578 #define FXAS21002_RT_SRC_X_RT_POL_POS ((uint8_t) 0x00) /* Rate Event was Positive. */ 579 #define FXAS21002_RT_SRC_X_RT_POL_NEG ((uint8_t) 0x01) /* Rate Event was Negative. */ 580 #define FXAS21002_RT_SRC_XRT_LOWER ((uint8_t) 0x00) /* Rate lower than RT_THS value. */ 581 #define FXAS21002_RT_SRC_XRT_GREATER ((uint8_t) 0x02) /* Rate greater than RT_THS value. Event has occured. */ 582 #define FXAS21002_RT_SRC_Y_RT_POL_POS ((uint8_t) 0x00) /* Rate Event was Positive. */ 583 #define FXAS21002_RT_SRC_Y_RT_POL_NEG ((uint8_t) 0x04) /* Rate Event was Negative. */ 584 #define FXAS21002_RT_SRC_YRT_LOWER ((uint8_t) 0x00) /* Rate lower than RT_THS value. */ 585 #define FXAS21002_RT_SRC_YRT_GREATER ((uint8_t) 0x08) /* Rate greater than RT_THS value. Event has occured. */ 586 #define FXAS21002_RT_SRC_Z_RT_POL_POS ((uint8_t) 0x00) /* Rate Event was Positive. */ 587 #define FXAS21002_RT_SRC_Z_RT_POL_NEG ((uint8_t) 0x10) /* Rate Event was Negative. */ 588 #define FXAS21002_RT_SRC_ZRT_LOWER ((uint8_t) 0x00) /* Rate lower than RT_THS value. */ 589 #define FXAS21002_RT_SRC_ZRT_GREATER ((uint8_t) 0x20) /* Rate greater than RT_THS value. Event has occured. */ 590 #define FXAS21002_RT_SRC_EA_NOEVENT ((uint8_t) 0x00) /* No event flags have been asserted. */ 591 #define FXAS21002_RT_SRC_EA_EVENT ((uint8_t) 0x40) /* One or more event flags have been asserted. */ 592 /*------------------------------*/ 593 594 595 596 /*-------------------------------- 597 ** Register: RT_THS 598 ** Enum: FXAS21002_RT_THS 599 ** -- 600 ** Offset : 0x10 - The RT_THS register sets the threshold limit for the detection of the rate and the debounce counter mode. 601 ** ------------------------------*/ 602 typedef union { 603 struct { 604 uint8_t ths : 7; /* Unsigned 7-bit rate threshold value; The contents should only be modified */ 605 /* when the device is in Standby mode; The internal state of the Rate */ 606 /* Threshold function is reset when a transition from Standby to Active or */ 607 /* Ready to Active modes occurs. */ 608 609 uint8_t dbcntm : 1; /* Debounce counter mode selection. */ 610 611 } b; 612 uint8_t w; 613 } FXAS21002_RT_THS_t; 614 615 616 /* 617 ** RT_THS - Bit field mask definitions 618 */ 619 #define FXAS21002_RT_THS_THS_MASK ((uint8_t) 0x7F) 620 #define FXAS21002_RT_THS_THS_SHIFT ((uint8_t) 0) 621 622 #define FXAS21002_RT_THS_DBCNTM_MASK ((uint8_t) 0x80) 623 #define FXAS21002_RT_THS_DBCNTM_SHIFT ((uint8_t) 7) 624 625 626 /* 627 ** RT_THS - Bit field value definitions 628 */ 629 #define FXAS21002_RT_THS_DBCNTM_CLEAR ((uint8_t) 0x80) /* Clear counter when angular rate is below the */ 630 /* threshold value. */ 631 #define FXAS21002_RT_THS_DBCNTM_DECREMENT ((uint8_t) 0x00) /* Decrement counter on every ODR cycle that the */ 632 /* angular rate is below the threshold value. */ 633 /*------------------------------*/ 634 635 636 637 /*-------------------------------- 638 ** Register: RT_COUNT 639 ** Enum: FXAS21002_RT_COUNT 640 ** -- 641 ** Offset : 0x11 - Sets the number of debounce counts. 642 ** ------------------------------*/ 643 typedef uint8_t FXAS21002_RT_COUNT_t; 644 645 646 647 /*-------------------------------- 648 ** Register: TEMP 649 ** Enum: FXAS21002_TEMP 650 ** -- 651 ** Offset : 0x12 - The TEMP register contains an 8-bit 2's complement temperature value with a range of �128 �C to +127 �C and a scaling of 1 �C/LSB. 652 ** ------------------------------*/ 653 typedef uint8_t FXAS21002_TEMP_t; 654 655 656 657 /*-------------------------------- 658 ** Register: CTRL_REG1 659 ** Enum: FXAS21002_CTRL_REG1 660 ** -- 661 ** Offset : 0x13 - The CTRL_REG1 register is used to configure the device ODR, set the operating mode, soft-reset the device, and exercise the Self-Test function. 662 ** ------------------------------*/ 663 typedef union { 664 struct { 665 uint8_t mode : 2; /* Operational Mode. */ 666 667 uint8_t dr : 3; /* Output Data Rate selection. */ 668 669 uint8_t st : 1; /* Self-Test Enable. */ 670 671 uint8_t rst : 1; /* Software Reset. */ 672 673 } b; 674 uint8_t w; 675 } FXAS21002_CTRL_REG1_t; 676 677 678 /* 679 ** CTRL_REG1 - Bit field mask definitions 680 */ 681 #define FXAS21002_CTRL_REG1_MODE_MASK ((uint8_t) 0x03) 682 #define FXAS21002_CTRL_REG1_MODE_SHIFT ((uint8_t) 0) 683 684 #define FXAS21002_CTRL_REG1_DR_MASK ((uint8_t) 0x1C) 685 #define FXAS21002_CTRL_REG1_DR_SHIFT ((uint8_t) 2) 686 687 #define FXAS21002_CTRL_REG1_ST_MASK ((uint8_t) 0x20) 688 #define FXAS21002_CTRL_REG1_ST_SHIFT ((uint8_t) 5) 689 690 #define FXAS21002_CTRL_REG1_RST_MASK ((uint8_t) 0x40) 691 #define FXAS21002_CTRL_REG1_RST_SHIFT ((uint8_t) 6) 692 693 694 /* 695 ** CTRL_REG1 - Bit field value definitions 696 */ 697 #define FXAS21002_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* Standby Mode. Register setting allowed. Lowest */ 698 /* power. */ 699 #define FXAS21002_CTRL_REG1_MODE_READY ((uint8_t) 0x01) /* Ready Mode. The device is ready to measure */ 700 /* angular rate but no data acquisitions are being */ 701 /* made. Register reads only. Reduced power. */ 702 #define FXAS21002_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x02) /* Active Mode. The device is fully functional. */ 703 /* Register reads only. Maximum power. */ 704 #define FXAS21002_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) 705 #define FXAS21002_CTRL_REG1_DR_400HZ ((uint8_t) 0x04) 706 #define FXAS21002_CTRL_REG1_DR_200HZ ((uint8_t) 0x08) 707 #define FXAS21002_CTRL_REG1_DR_100HZ ((uint8_t) 0x0c) 708 #define FXAS21002_CTRL_REG1_DR_50HZ ((uint8_t) 0x10) 709 #define FXAS21002_CTRL_REG1_DR_25HZ ((uint8_t) 0x14) 710 #define FXAS21002_CTRL_REG1_DR_12_5HZ ((uint8_t) 0x18) 711 #define FXAS21002_CTRL_REG1_ST_ENABLE ((uint8_t) 0x20) 712 #define FXAS21002_CTRL_REG1_ST_DISABLE ((uint8_t) 0x00) 713 #define FXAS21002_CTRL_REG1_RST_TRIGGER ((uint8_t) 0x40) 714 #define FXAS21002_CTRL_REG1_RST_NOTTRIGGERED ((uint8_t) 0x00) 715 /*------------------------------*/ 716 717 718 719 /*-------------------------------- 720 ** Register: CTRL_REG2 721 ** Enum: FXAS21002_CTRL_REG2 722 ** -- 723 ** Offset : 0x14 - This register enables and assigns the output pin(s) and logic polarities for the various interrupt sources available on the device. 724 ** ------------------------------*/ 725 typedef union { 726 struct { 727 uint8_t pp_od : 1; /* INT1 and INT2 pin output driver configuration. */ 728 729 uint8_t ipol : 1; /* Interrupt logic polarity. */ 730 731 uint8_t int_en_drdy : 1; /* Data ready interrupt enable. */ 732 733 uint8_t int_cfg_drdy : 1; /* Data-ready interrupt pin routing. */ 734 735 uint8_t int_en_rt : 1; /* Rate threshold interrupt enable. */ 736 737 uint8_t int_cfg_rt : 1; /* Rate threshold interrupt pin routing. */ 738 739 uint8_t int_en_fifo : 1; /* FIFO Interrupt Enable. */ 740 741 uint8_t int_cfg_fifo : 1; /* FIFO interrupt pin routing. */ 742 743 } b; 744 uint8_t w; 745 } FXAS21002_CTRL_REG2_t; 746 747 748 /* 749 ** CTRL_REG2 - Bit field mask definitions 750 */ 751 #define FXAS21002_CTRL_REG2_PP_OD_MASK ((uint8_t) 0x01) 752 #define FXAS21002_CTRL_REG2_PP_OD_SHIFT ((uint8_t) 0) 753 754 #define FXAS21002_CTRL_REG2_IPOL_MASK ((uint8_t) 0x02) 755 #define FXAS21002_CTRL_REG2_IPOL_SHIFT ((uint8_t) 1) 756 757 #define FXAS21002_CTRL_REG2_INT_EN_DRDY_MASK ((uint8_t) 0x04) 758 #define FXAS21002_CTRL_REG2_INT_EN_DRDY_SHIFT ((uint8_t) 2) 759 760 #define FXAS21002_CTRL_REG2_INT_CFG_DRDY_MASK ((uint8_t) 0x08) 761 #define FXAS21002_CTRL_REG2_INT_CFG_DRDY_SHIFT ((uint8_t) 3) 762 763 #define FXAS21002_CTRL_REG2_INT_EN_RT_MASK ((uint8_t) 0x10) 764 #define FXAS21002_CTRL_REG2_INT_EN_RT_SHIFT ((uint8_t) 4) 765 766 #define FXAS21002_CTRL_REG2_INT_CFG_RT_MASK ((uint8_t) 0x20) 767 #define FXAS21002_CTRL_REG2_INT_CFG_RT_SHIFT ((uint8_t) 5) 768 769 #define FXAS21002_CTRL_REG2_INT_EN_FIFO_MASK ((uint8_t) 0x40) 770 #define FXAS21002_CTRL_REG2_INT_EN_FIFO_SHIFT ((uint8_t) 6) 771 772 #define FXAS21002_CTRL_REG2_INT_CFG_FIFO_MASK ((uint8_t) 0x80) 773 #define FXAS21002_CTRL_REG2_INT_CFG_FIFO_SHIFT ((uint8_t) 7) 774 775 776 /* 777 ** CTRL_REG2 - Bit field value definitions 778 */ 779 #define FXAS21002_CTRL_REG2_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-pull output driver. */ 780 #define FXAS21002_CTRL_REG2_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open-drain output driver. */ 781 #define FXAS21002_CTRL_REG2_IPOL_ACTIVE_LOW ((uint8_t) 0x00) 782 #define FXAS21002_CTRL_REG2_IPOL_ACTIVE_HIGH ((uint8_t) 0x02) 783 #define FXAS21002_CTRL_REG2_INT_EN_DRDY_ENABLE ((uint8_t) 0x04) 784 #define FXAS21002_CTRL_REG2_INT_EN_DRDY_DISABLE ((uint8_t) 0x00) 785 #define FXAS21002_CTRL_REG2_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ 786 #define FXAS21002_CTRL_REG2_INT_CFG_DRDY_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */ 787 #define FXAS21002_CTRL_REG2_INT_EN_RT_ENABLE ((uint8_t) 0x10) 788 #define FXAS21002_CTRL_REG2_INT_EN_RT_DISABLE ((uint8_t) 0x00) 789 #define FXAS21002_CTRL_REG2_INT_CFG_RT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ 790 #define FXAS21002_CTRL_REG2_INT_CFG_RT_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */ 791 #define FXAS21002_CTRL_REG2_INT_EN_FIFO_ENABLE ((uint8_t) 0x40) 792 #define FXAS21002_CTRL_REG2_INT_EN_FIFO_DISABLE ((uint8_t) 0x00) 793 #define FXAS21002_CTRL_REG2_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ 794 #define FXAS21002_CTRL_REG2_INT_CFG_FIFO_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */ 795 /*------------------------------*/ 796 797 798 799 /*-------------------------------- 800 ** Register: CTRL_REG3 801 ** Enum: FXAS21002_CTRL_REG3 802 ** -- 803 ** Offset : 0x15 - Auto-increment address configuration, external power control, Full Scale Range (FSR) expansion 804 ** ------------------------------*/ 805 typedef union { 806 struct { 807 uint8_t fs_double : 1; /* Increases the dynamic range for each CTRL_REG0 : FS selection by a factor */ 808 /* of two. */ 809 810 uint8_t _reserved_ : 1; 811 uint8_t extctrlen : 1; /* External power mode control input. */ 812 813 uint8_t wraptoone : 1; /* Auto-increment read address pointer roll-over behavior. */ 814 815 } b; 816 uint8_t w; 817 } FXAS21002_CTRL_REG3_t; 818 819 820 /* 821 ** CTRL_REG3 - Bit field mask definitions 822 */ 823 #define FXAS21002_CTRL_REG3_FS_DOUBLE_MASK ((uint8_t) 0x01) 824 #define FXAS21002_CTRL_REG3_FS_DOUBLE_SHIFT ((uint8_t) 0) 825 826 #define FXAS21002_CTRL_REG3_EXTCTRLEN_MASK ((uint8_t) 0x04) 827 #define FXAS21002_CTRL_REG3_EXTCTRLEN_SHIFT ((uint8_t) 2) 828 829 #define FXAS21002_CTRL_REG3_WRAPTOONE_MASK ((uint8_t) 0x08) 830 #define FXAS21002_CTRL_REG3_WRAPTOONE_SHIFT ((uint8_t) 3) 831 832 833 /* 834 ** CTRL_REG3 - Bit field value definitions 835 */ 836 #define FXAS21002_CTRL_REG3_FS_DOUBLE_ENABLE ((uint8_t) 0x01) /* Maximum full-scale range selections are doubled */ 837 /* (4000, 2000, 1000, 500 dps). */ 838 #define FXAS21002_CTRL_REG3_FS_DOUBLE_DISABLE ((uint8_t) 0x00) /* Maximum full-scale range selections are as per */ 839 /* selectable full-scale ranges (2000, 1000, 500, */ 840 /* 250 dps). */ 841 #define FXAS21002_CTRL_REG3_EXTCTRLEN_INT2 ((uint8_t) 0x00) /* INT2 pin is used as an interrupt output */ 842 /* (default). */ 843 #define FXAS21002_CTRL_REG3_EXTCTRLEN_POWER_CONTROL ((uint8_t) 0x04) /* INT2 pin becomes an input pin that may be used */ 844 /* to control the power mode. */ 845 #define FXAS21002_CTRL_REG3_WRAPTOONE_ROLL_STATUS ((uint8_t) 0x00) /* The auto-increment read address pointer rolls */ 846 /* over to address 0x00 (STATUS) after the Z-axis */ 847 /* LSB is read (default). */ 848 #define FXAS21002_CTRL_REG3_WRAPTOONE_ROLL_DATA ((uint8_t) 0x08) /* The auto-increment pointer rolls over to address */ 849 /* 0x01 (X-axis MSB) in order to facilitate the */ 850 /* faster read out of the FIFO data in a single */ 851 /* burst read operation. */ 852 /*------------------------------*/ 853 854 855 #endif /* FXAS21002_H_ */ 856
