1 /* 2 ** ################################################################### 3 ** Processors: MKE02Z16VFM4 4 ** MKE02Z16VLC4 5 ** MKE02Z16VLD4 6 ** MKE02Z32VFM4 7 ** MKE02Z32VLC4 8 ** MKE02Z32VLD4 9 ** MKE02Z32VLH4 10 ** MKE02Z32VQH4 11 ** MKE02Z64VFM4 12 ** MKE02Z64VLC4 13 ** MKE02Z64VLD4 14 ** MKE02Z64VLH4 15 ** MKE02Z64VQH4 16 ** 17 ** Compilers: Keil ARM C/C++ Compiler 18 ** Freescale C/C++ for Embedded ARM 19 ** GNU C Compiler 20 ** IAR ANSI C/C++ Compiler for ARM 21 ** MCUXpresso Compiler 22 ** 23 ** Reference manual: MKE02P64M40SF0RM Rev 4 24 ** Version: rev. 1.0, 2017-05-19 25 ** Build: b180802 26 ** 27 ** Abstract: 28 ** CMSIS Peripheral Access Layer for MKE02Z4 29 ** 30 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 31 ** Copyright 2016-2018 NXP 32 ** 33 ** SPDX-License-Identifier: BSD-3-Clause 34 ** 35 ** http: www.nxp.com 36 ** mail: support@nxp.com 37 ** 38 ** Revisions: 39 ** - rev. 1.0 (2017-05-19) 40 ** Initial version. 41 ** 42 ** ################################################################### 43 */ 44 45 /*! 46 * @file MKE02Z4.h 47 * @version 1.0 48 * @date 2017-05-19 49 * @brief CMSIS Peripheral Access Layer for MKE02Z4 50 * 51 * CMSIS Peripheral Access Layer for MKE02Z4 52 */ 53 54 #ifndef _MKE02Z4_H_ 55 #define _MKE02Z4_H_ /**< Symbol preventing repeated inclusion */ 56 57 /** Memory map major version (memory maps with equal major version number are 58 * compatible) */ 59 #define MCU_MEM_MAP_VERSION 0x0100U 60 /** Memory map minor version */ 61 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 62 63 64 /* ---------------------------------------------------------------------------- 65 -- Interrupt vector numbers 66 ---------------------------------------------------------------------------- */ 67 68 /*! 69 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 70 * @{ 71 */ 72 73 /** Interrupt Number Definitions */ 74 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 75 76 typedef enum IRQn { 77 /* Auxiliary constants */ 78 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 79 80 /* Core interrupts */ 81 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 82 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 83 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 84 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 85 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 86 87 /* Device specific interrupts */ 88 Reserved16_IRQn = 0, /**< Reserved interrupt */ 89 Reserved17_IRQn = 1, /**< Reserved interrupt */ 90 Reserved18_IRQn = 2, /**< Reserved interrupt */ 91 Reserved19_IRQn = 3, /**< Reserved interrupt */ 92 Reserved20_IRQn = 4, /**< Reserved interrupt */ 93 FTMRH_IRQn = 5, /**< Command complete and error interrupt */ 94 PMC_IRQn = 6, /**< Low-voltage warning */ 95 IRQ_IRQn = 7, /**< External interrupt */ 96 I2C0_IRQn = 8, /**< Single interrupt vector for all sources */ 97 Reserved25_IRQn = 9, /**< Reserved interrupt */ 98 SPI0_IRQn = 10, /**< Single interrupt vector for all sources */ 99 SPI1_IRQn = 11, /**< Single interrupt vector for all sources */ 100 UART0_IRQn = 12, /**< Status and error */ 101 UART1_IRQn = 13, /**< Status and error */ 102 UART2_IRQn = 14, /**< Status and error */ 103 ADC_IRQn = 15, /**< ADC conversion complete interrupt */ 104 ACMP0_IRQn = 16, /**< Analog comparator 0 interrupt */ 105 FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */ 106 FTM1_IRQn = 18, /**< FTM1 single interrupt vector for all sources */ 107 FTM2_IRQn = 19, /**< FTM2 single interrupt vector for all sources */ 108 RTC_IRQn = 20, /**< RTC overflow */ 109 ACMP1_IRQn = 21, /**< Analog comparator 1 interrupt */ 110 PIT_CH0_IRQn = 22, /**< PIT CH0 overflow */ 111 PIT_CH1_IRQn = 23, /**< PIT CH1 overflow */ 112 KBI0_IRQn = 24, /**< Keyboard interrupt0 */ 113 KBI1_IRQn = 25, /**< Keyboard interrupt1 */ 114 Reserved42_IRQn = 26, /**< Reserved interrupt */ 115 ICS_IRQn = 27, /**< Clock loss of lock */ 116 WDOG_IRQn = 28, /**< Watchdog timeout */ 117 Reserved45_IRQn = 29, /**< Reserved interrupt */ 118 Reserved46_IRQn = 30, /**< Reserved interrupt */ 119 Reserved47_IRQn = 31 /**< Reserved interrupt */ 120 } IRQn_Type; 121 122 /*! 123 * @} 124 */ /* end of group Interrupt_vector_numbers */ 125 126 127 /* ---------------------------------------------------------------------------- 128 -- Cortex M0 Core Configuration 129 ---------------------------------------------------------------------------- */ 130 131 /*! 132 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 133 * @{ 134 */ 135 136 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 137 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 138 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 139 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 140 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 141 142 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 143 #include "system_MKE02Z4.h" /* Device specific configuration file */ 144 145 /*! 146 * @} 147 */ /* end of group Cortex_Core_Configuration */ 148 149 150 /* ---------------------------------------------------------------------------- 151 -- Device Peripheral Access Layer 152 ---------------------------------------------------------------------------- */ 153 154 /*! 155 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 156 * @{ 157 */ 158 159 160 /* 161 ** Start of section using anonymous unions 162 */ 163 164 #if defined(__ARMCC_VERSION) 165 #if (__ARMCC_VERSION >= 6010050) 166 #pragma clang diagnostic push 167 #else 168 #pragma push 169 #pragma anon_unions 170 #endif 171 #elif defined(__CWCC__) 172 #pragma push 173 #pragma cpp_extensions on 174 #elif defined(__GNUC__) 175 /* anonymous unions are enabled by default */ 176 #elif defined(__IAR_SYSTEMS_ICC__) 177 #pragma language=extended 178 #else 179 #error Not supported compiler type 180 #endif 181 182 /* ---------------------------------------------------------------------------- 183 -- ACMP Peripheral Access Layer 184 ---------------------------------------------------------------------------- */ 185 186 /*! 187 * @addtogroup ACMP_Peripheral_Access_Layer ACMP Peripheral Access Layer 188 * @{ 189 */ 190 191 /** ACMP - Register Layout Typedef */ 192 typedef struct { 193 __IO uint8_t CS; /**< ACMP Control and Status Register, offset: 0x0 */ 194 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ 195 __IO uint8_t C1; /**< ACMP Control Register 1, offset: 0x2 */ 196 __IO uint8_t C2; /**< ACMP Control Register 2, offset: 0x3 */ 197 } ACMP_Type; 198 199 /* ---------------------------------------------------------------------------- 200 -- ACMP Register Masks 201 ---------------------------------------------------------------------------- */ 202 203 /*! 204 * @addtogroup ACMP_Register_Masks ACMP Register Masks 205 * @{ 206 */ 207 208 /*! @name CS - ACMP Control and Status Register */ 209 /*! @{ */ 210 #define ACMP_CS_ACMOD_MASK (0x3U) 211 #define ACMP_CS_ACMOD_SHIFT (0U) 212 /*! ACMOD - ACMP MOD 213 * 0b00..ACMP interrupt on output falling edge. 214 * 0b01..ACMP interrupt on output rising edge. 215 * 0b10..ACMP interrupt on output falling edge. 216 * 0b11..ACMP interrupt on output falling or rising edge. 217 */ 218 #define ACMP_CS_ACMOD(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACMOD_SHIFT)) & ACMP_CS_ACMOD_MASK) 219 #define ACMP_CS_ACOPE_MASK (0x4U) 220 #define ACMP_CS_ACOPE_SHIFT (2U) 221 /*! ACOPE - ACMP Output Pin Enable 222 * 0b0..ACMP output cannot be placed onto external pin. 223 * 0b1..ACMP output can be placed onto external pin. 224 */ 225 #define ACMP_CS_ACOPE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACOPE_SHIFT)) & ACMP_CS_ACOPE_MASK) 226 #define ACMP_CS_ACO_MASK (0x8U) 227 #define ACMP_CS_ACO_SHIFT (3U) 228 #define ACMP_CS_ACO(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACO_SHIFT)) & ACMP_CS_ACO_MASK) 229 #define ACMP_CS_ACIE_MASK (0x10U) 230 #define ACMP_CS_ACIE_SHIFT (4U) 231 /*! ACIE - ACMP Interrupt Enable 232 * 0b0..Disable the ACMP Interrupt. 233 * 0b1..Enable the ACMP Interrupt. 234 */ 235 #define ACMP_CS_ACIE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACIE_SHIFT)) & ACMP_CS_ACIE_MASK) 236 #define ACMP_CS_ACF_MASK (0x20U) 237 #define ACMP_CS_ACF_SHIFT (5U) 238 #define ACMP_CS_ACF(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACF_SHIFT)) & ACMP_CS_ACF_MASK) 239 #define ACMP_CS_HYST_MASK (0x40U) 240 #define ACMP_CS_HYST_SHIFT (6U) 241 /*! HYST - Analog Comparator Hysterisis Selection 242 * 0b0..20 mV. 243 * 0b1..30 mV. 244 */ 245 #define ACMP_CS_HYST(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_HYST_SHIFT)) & ACMP_CS_HYST_MASK) 246 #define ACMP_CS_ACE_MASK (0x80U) 247 #define ACMP_CS_ACE_SHIFT (7U) 248 /*! ACE - Analog Comparator Enable 249 * 0b0..The ACMP is disabled. 250 * 0b1..The ACMP is enabled. 251 */ 252 #define ACMP_CS_ACE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACE_SHIFT)) & ACMP_CS_ACE_MASK) 253 /*! @} */ 254 255 /*! @name C0 - ACMP Control Register 0 */ 256 /*! @{ */ 257 #define ACMP_C0_ACNSEL_MASK (0x3U) 258 #define ACMP_C0_ACNSEL_SHIFT (0U) 259 /*! ACNSEL - ACMP Negative Input Select 260 * 0b00..External reference 0 261 * 0b01..External reference 1 262 * 0b10..External reference 2 263 * 0b11..DAC output 264 */ 265 #define ACMP_C0_ACNSEL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C0_ACNSEL_SHIFT)) & ACMP_C0_ACNSEL_MASK) 266 #define ACMP_C0_ACPSEL_MASK (0x30U) 267 #define ACMP_C0_ACPSEL_SHIFT (4U) 268 /*! ACPSEL - ACMP Positive Input Select 269 * 0b00..External reference 0 270 * 0b01..External reference 1 271 * 0b10..External reference 2 272 * 0b11..DAC output 273 */ 274 #define ACMP_C0_ACPSEL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C0_ACPSEL_SHIFT)) & ACMP_C0_ACPSEL_MASK) 275 /*! @} */ 276 277 /*! @name C1 - ACMP Control Register 1 */ 278 /*! @{ */ 279 #define ACMP_C1_DACVAL_MASK (0x3FU) 280 #define ACMP_C1_DACVAL_SHIFT (0U) 281 #define ACMP_C1_DACVAL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACVAL_SHIFT)) & ACMP_C1_DACVAL_MASK) 282 #define ACMP_C1_DACREF_MASK (0x40U) 283 #define ACMP_C1_DACREF_SHIFT (6U) 284 /*! DACREF - DAC Reference Select 285 * 0b0..The DAC selects Bandgap as the reference. 286 * 0b1..The DAC selects VDDA as the reference. 287 */ 288 #define ACMP_C1_DACREF(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACREF_SHIFT)) & ACMP_C1_DACREF_MASK) 289 #define ACMP_C1_DACEN_MASK (0x80U) 290 #define ACMP_C1_DACEN_SHIFT (7U) 291 /*! DACEN - DAC Enable 292 * 0b0..The DAC is disabled. 293 * 0b1..The DAC is enabled. 294 */ 295 #define ACMP_C1_DACEN(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACEN_SHIFT)) & ACMP_C1_DACEN_MASK) 296 /*! @} */ 297 298 /*! @name C2 - ACMP Control Register 2 */ 299 /*! @{ */ 300 #define ACMP_C2_ACIPE_MASK (0x7U) 301 #define ACMP_C2_ACIPE_SHIFT (0U) 302 /*! ACIPE - ACMP Input Pin Enable 303 * 0b000..The corresponding external analog input is not allowed. 304 * 0b001..The corresponding external analog input is allowed. 305 */ 306 #define ACMP_C2_ACIPE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C2_ACIPE_SHIFT)) & ACMP_C2_ACIPE_MASK) 307 /*! @} */ 308 309 310 /*! 311 * @} 312 */ /* end of group ACMP_Register_Masks */ 313 314 315 /* ACMP - Peripheral instance base addresses */ 316 /** Peripheral ACMP0 base address */ 317 #define ACMP0_BASE (0x40073000u) 318 /** Peripheral ACMP0 base pointer */ 319 #define ACMP0 ((ACMP_Type *)ACMP0_BASE) 320 /** Peripheral ACMP1 base address */ 321 #define ACMP1_BASE (0x40074000u) 322 /** Peripheral ACMP1 base pointer */ 323 #define ACMP1 ((ACMP_Type *)ACMP1_BASE) 324 /** Array initializer of ACMP peripheral base addresses */ 325 #define ACMP_BASE_ADDRS { ACMP0_BASE, ACMP1_BASE } 326 /** Array initializer of ACMP peripheral base pointers */ 327 #define ACMP_BASE_PTRS { ACMP0, ACMP1 } 328 /** Interrupt vectors for the ACMP peripheral type */ 329 #define ACMP_IRQS { ACMP0_IRQn, ACMP1_IRQn } 330 331 /*! 332 * @} 333 */ /* end of group ACMP_Peripheral_Access_Layer */ 334 335 336 /* ---------------------------------------------------------------------------- 337 -- ADC Peripheral Access Layer 338 ---------------------------------------------------------------------------- */ 339 340 /*! 341 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 342 * @{ 343 */ 344 345 /** ADC - Register Layout Typedef */ 346 typedef struct { 347 __IO uint32_t SC1; /**< Status and Control Register 1, offset: 0x0 */ 348 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x4 */ 349 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x8 */ 350 __IO uint32_t SC4; /**< Status and Control Register 4, offset: 0xC */ 351 __I uint32_t R; /**< Conversion Result Register, offset: 0x10 */ 352 __IO uint32_t CV; /**< Compare Value Register, offset: 0x14 */ 353 __IO uint32_t APCTL1; /**< Pin Control 1 Register, offset: 0x18 */ 354 } ADC_Type; 355 356 /* ---------------------------------------------------------------------------- 357 -- ADC Register Masks 358 ---------------------------------------------------------------------------- */ 359 360 /*! 361 * @addtogroup ADC_Register_Masks ADC Register Masks 362 * @{ 363 */ 364 365 /*! @name SC1 - Status and Control Register 1 */ 366 /*! @{ */ 367 #define ADC_SC1_ADCH_MASK (0x1FU) 368 #define ADC_SC1_ADCH_SHIFT (0U) 369 /*! ADCH - Input Channel Select 370 * 0b10110..Temperature Sensor 371 * 0b10111..Bandgap 372 * 0b11101..VREFH 373 * 0b11110..VREFL 374 * 0b11111..Module disabled Reset FIFO in FIFO mode. 375 */ 376 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 377 #define ADC_SC1_ADCO_MASK (0x20U) 378 #define ADC_SC1_ADCO_SHIFT (5U) 379 /*! ADCO - Continuous Conversion Enable 380 * 0b0..One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversion are triggered when ADC_SC2[ADTRG]=0. 381 * 0b1..Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. 382 */ 383 #define ADC_SC1_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCO_SHIFT)) & ADC_SC1_ADCO_MASK) 384 #define ADC_SC1_AIEN_MASK (0x40U) 385 #define ADC_SC1_AIEN_SHIFT (6U) 386 /*! AIEN - Interrupt Enable 387 * 0b0..Conversion complete interrupt disabled. 388 * 0b1..Conversion complete interrupt enabled. 389 */ 390 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 391 #define ADC_SC1_COCO_MASK (0x80U) 392 #define ADC_SC1_COCO_SHIFT (7U) 393 /*! COCO - Conversion Complete Flag 394 * 0b0..Conversion not completed. 395 * 0b1..Conversion completed. 396 */ 397 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 398 /*! @} */ 399 400 /*! @name SC2 - Status and Control Register 2 */ 401 /*! @{ */ 402 #define ADC_SC2_REFSEL_MASK (0x3U) 403 #define ADC_SC2_REFSEL_SHIFT (0U) 404 /*! REFSEL - Voltage Reference Selection 405 * 0b00..Default voltage reference pin pair (VREFH/VREFL). 406 * 0b01..Analog supply pin pair (VDDA/VSSA). 407 * 0b10..Reserved. 408 * 0b11..Reserved - Selects default voltage reference (VREFH/VREFL) pin pair. 409 */ 410 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 411 #define ADC_SC2_FFULL_MASK (0x4U) 412 #define ADC_SC2_FFULL_SHIFT (2U) 413 /*! FFULL - Result FIFO full 414 * 0b0..Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO. 415 * 0b1..Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action. 416 */ 417 #define ADC_SC2_FFULL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_FFULL_SHIFT)) & ADC_SC2_FFULL_MASK) 418 #define ADC_SC2_FEMPTY_MASK (0x8U) 419 #define ADC_SC2_FEMPTY_SHIFT (3U) 420 /*! FEMPTY - Result FIFO empty 421 * 0b0..Indicates that ADC result FIFO have at least one valid new data. 422 * 0b1..Indicates that ADC result FIFO have no valid new data. 423 */ 424 #define ADC_SC2_FEMPTY(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_FEMPTY_SHIFT)) & ADC_SC2_FEMPTY_MASK) 425 #define ADC_SC2_ACFGT_MASK (0x10U) 426 #define ADC_SC2_ACFGT_SHIFT (4U) 427 /*! ACFGT - Compare Function Greater Than Enable 428 * 0b0..Compare triggers when input is less than compare level. 429 * 0b1..Compare triggers when input is greater than or equal to compare level. 430 */ 431 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 432 #define ADC_SC2_ACFE_MASK (0x20U) 433 #define ADC_SC2_ACFE_SHIFT (5U) 434 /*! ACFE - Compare Function Enable 435 * 0b0..Compare function disabled. 436 * 0b1..Compare function enabled. 437 */ 438 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 439 #define ADC_SC2_ADTRG_MASK (0x40U) 440 #define ADC_SC2_ADTRG_SHIFT (6U) 441 /*! ADTRG - Conversion Trigger Select 442 * 0b0..Software trigger selected. 443 * 0b1..Hardware trigger selected. 444 */ 445 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 446 #define ADC_SC2_ADACT_MASK (0x80U) 447 #define ADC_SC2_ADACT_SHIFT (7U) 448 /*! ADACT - Conversion Active 449 * 0b0..Conversion not in progress. 450 * 0b1..Conversion in progress. 451 */ 452 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 453 /*! @} */ 454 455 /*! @name SC3 - Status and Control Register 3 */ 456 /*! @{ */ 457 #define ADC_SC3_ADICLK_MASK (0x3U) 458 #define ADC_SC3_ADICLK_SHIFT (0U) 459 /*! ADICLK - Input Clock Select 460 * 0b00..Bus clock 461 * 0b01..Bus clock divided by 2 462 * 0b10..Alternate clock (ALTCLK) 463 * 0b11..Asynchronous clock (ADACK) 464 */ 465 #define ADC_SC3_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADICLK_SHIFT)) & ADC_SC3_ADICLK_MASK) 466 #define ADC_SC3_MODE_MASK (0xCU) 467 #define ADC_SC3_MODE_SHIFT (2U) 468 /*! MODE - Conversion Mode Selection 469 * 0b00..8-bit conversion (N = 8) 470 * 0b01..10-bit conversion (N = 10) 471 * 0b10..12-bit conversion (N = 12) 472 * 0b11..Reserved 473 */ 474 #define ADC_SC3_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_MODE_SHIFT)) & ADC_SC3_MODE_MASK) 475 #define ADC_SC3_ADLSMP_MASK (0x10U) 476 #define ADC_SC3_ADLSMP_SHIFT (4U) 477 /*! ADLSMP - Long Sample Time Configuration 478 * 0b0..Short sample time. 479 * 0b1..Long sample time. 480 */ 481 #define ADC_SC3_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADLSMP_SHIFT)) & ADC_SC3_ADLSMP_MASK) 482 #define ADC_SC3_ADIV_MASK (0x60U) 483 #define ADC_SC3_ADIV_SHIFT (5U) 484 /*! ADIV - Clock Divide Select 485 * 0b00..Divide ration = 1, and clock rate = Input clock. 486 * 0b01..Divide ration = 2, and clock rate = Input clock * 2. 487 * 0b10..Divide ration = 3, and clock rate = Input clock * 4. 488 * 0b11..Divide ration = 4, and clock rate = Input clock * 8. 489 */ 490 #define ADC_SC3_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADIV_SHIFT)) & ADC_SC3_ADIV_MASK) 491 #define ADC_SC3_ADLPC_MASK (0x80U) 492 #define ADC_SC3_ADLPC_SHIFT (7U) 493 /*! ADLPC - Low-Power Configuration 494 * 0b0..High speed configuration. 495 * 0b1..Low power configuration:The power is reduced at the expense of maximum clock speed. 496 */ 497 #define ADC_SC3_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADLPC_SHIFT)) & ADC_SC3_ADLPC_MASK) 498 /*! @} */ 499 500 /*! @name SC4 - Status and Control Register 4 */ 501 /*! @{ */ 502 #define ADC_SC4_AFDEP_MASK (0x7U) 503 #define ADC_SC4_AFDEP_SHIFT (0U) 504 /*! AFDEP - FIFO Depth 505 * 0b000..FIFO is disabled. 506 * 0b001..2-level FIFO is enabled. 507 * 0b010..3-level FIFO is enabled.. 508 * 0b011..4-level FIFO is enabled. 509 * 0b100..5-level FIFO is enabled. 510 * 0b101..6-level FIFO is enabled. 511 * 0b110..7-level FIFO is enabled. 512 * 0b111..8-level FIFO is enabled. 513 */ 514 #define ADC_SC4_AFDEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_AFDEP_SHIFT)) & ADC_SC4_AFDEP_MASK) 515 #define ADC_SC4_ACFSEL_MASK (0x20U) 516 #define ADC_SC4_ACFSEL_SHIFT (5U) 517 /*! ACFSEL - Compare Function Selection 518 * 0b0..OR all of compare trigger. 519 * 0b1..AND all of compare trigger. 520 */ 521 #define ADC_SC4_ACFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_ACFSEL_SHIFT)) & ADC_SC4_ACFSEL_MASK) 522 #define ADC_SC4_ASCANE_MASK (0x40U) 523 #define ADC_SC4_ASCANE_SHIFT (6U) 524 /*! ASCANE - FIFO Scan Mode Enable 525 * 0b0..FIFO scan mode disabled. 526 * 0b1..FIFO scan mode enabled. 527 */ 528 #define ADC_SC4_ASCANE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_ASCANE_SHIFT)) & ADC_SC4_ASCANE_MASK) 529 /*! @} */ 530 531 /*! @name R - Conversion Result Register */ 532 /*! @{ */ 533 #define ADC_R_ADR_MASK (0xFFFU) 534 #define ADC_R_ADR_SHIFT (0U) 535 #define ADC_R_ADR(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_ADR_SHIFT)) & ADC_R_ADR_MASK) 536 /*! @} */ 537 538 /*! @name CV - Compare Value Register */ 539 /*! @{ */ 540 #define ADC_CV_CV_MASK (0xFFFU) 541 #define ADC_CV_CV_SHIFT (0U) 542 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) 543 /*! @} */ 544 545 /*! @name APCTL1 - Pin Control 1 Register */ 546 /*! @{ */ 547 #define ADC_APCTL1_ADPC_MASK (0xFFFFU) 548 #define ADC_APCTL1_ADPC_SHIFT (0U) 549 /*! ADPC - ADC Pin Control 550 * 0b0000000000000000..ADx pin I/O control enabled. 551 * 0b0000000000000001..ADx pin I/O control disabled. 552 */ 553 #define ADC_APCTL1_ADPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_APCTL1_ADPC_SHIFT)) & ADC_APCTL1_ADPC_MASK) 554 /*! @} */ 555 556 557 /*! 558 * @} 559 */ /* end of group ADC_Register_Masks */ 560 561 562 /* ADC - Peripheral instance base addresses */ 563 /** Peripheral ADC base address */ 564 #define ADC_BASE (0x4003B000u) 565 /** Peripheral ADC base pointer */ 566 #define ADC ((ADC_Type *)ADC_BASE) 567 /** Array initializer of ADC peripheral base addresses */ 568 #define ADC_BASE_ADDRS { ADC_BASE } 569 /** Array initializer of ADC peripheral base pointers */ 570 #define ADC_BASE_PTRS { ADC } 571 /** Interrupt vectors for the ADC peripheral type */ 572 #define ADC_IRQS { ADC_IRQn } 573 574 /*! 575 * @} 576 */ /* end of group ADC_Peripheral_Access_Layer */ 577 578 579 /* ---------------------------------------------------------------------------- 580 -- CRC Peripheral Access Layer 581 ---------------------------------------------------------------------------- */ 582 583 /*! 584 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 585 * @{ 586 */ 587 588 /** CRC - Register Layout Typedef */ 589 typedef struct { 590 union { /* offset: 0x0 */ 591 struct { /* offset: 0x0 */ 592 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 593 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 594 } ACCESS16BIT; 595 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 596 struct { /* offset: 0x0 */ 597 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 598 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 599 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 600 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 601 } ACCESS8BIT; 602 }; 603 union { /* offset: 0x4 */ 604 struct { /* offset: 0x4 */ 605 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 606 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 607 } GPOLY_ACCESS16BIT; 608 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 609 struct { /* offset: 0x4 */ 610 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 611 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 612 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 613 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 614 } GPOLY_ACCESS8BIT; 615 }; 616 union { /* offset: 0x8 */ 617 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 618 struct { /* offset: 0x8 */ 619 uint8_t RESERVED_0[3]; 620 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 621 } CTRL_ACCESS8BIT; 622 }; 623 } CRC_Type; 624 625 /* ---------------------------------------------------------------------------- 626 -- CRC Register Masks 627 ---------------------------------------------------------------------------- */ 628 629 /*! 630 * @addtogroup CRC_Register_Masks CRC Register Masks 631 * @{ 632 */ 633 634 /*! @name DATAL - CRC_DATAL register. */ 635 /*! @{ */ 636 #define CRC_DATAL_DATAL_MASK (0xFFFFU) 637 #define CRC_DATAL_DATAL_SHIFT (0U) 638 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) 639 /*! @} */ 640 641 /*! @name DATAH - CRC_DATAH register. */ 642 /*! @{ */ 643 #define CRC_DATAH_DATAH_MASK (0xFFFFU) 644 #define CRC_DATAH_DATAH_SHIFT (0U) 645 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) 646 /*! @} */ 647 648 /*! @name DATA - CRC Data register */ 649 /*! @{ */ 650 #define CRC_DATA_LL_MASK (0xFFU) 651 #define CRC_DATA_LL_SHIFT (0U) 652 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 653 #define CRC_DATA_LU_MASK (0xFF00U) 654 #define CRC_DATA_LU_SHIFT (8U) 655 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 656 #define CRC_DATA_HL_MASK (0xFF0000U) 657 #define CRC_DATA_HL_SHIFT (16U) 658 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 659 #define CRC_DATA_HU_MASK (0xFF000000U) 660 #define CRC_DATA_HU_SHIFT (24U) 661 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 662 /*! @} */ 663 664 /*! @name DATALL - CRC_DATALL register. */ 665 /*! @{ */ 666 #define CRC_DATALL_DATALL_MASK (0xFFU) 667 #define CRC_DATALL_DATALL_SHIFT (0U) 668 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) 669 /*! @} */ 670 671 /*! @name DATALU - CRC_DATALU register. */ 672 /*! @{ */ 673 #define CRC_DATALU_DATALU_MASK (0xFFU) 674 #define CRC_DATALU_DATALU_SHIFT (0U) 675 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) 676 /*! @} */ 677 678 /*! @name DATAHL - CRC_DATAHL register. */ 679 /*! @{ */ 680 #define CRC_DATAHL_DATAHL_MASK (0xFFU) 681 #define CRC_DATAHL_DATAHL_SHIFT (0U) 682 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) 683 /*! @} */ 684 685 /*! @name DATAHU - CRC_DATAHU register. */ 686 /*! @{ */ 687 #define CRC_DATAHU_DATAHU_MASK (0xFFU) 688 #define CRC_DATAHU_DATAHU_SHIFT (0U) 689 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) 690 /*! @} */ 691 692 /*! @name GPOLYL - CRC_GPOLYL register. */ 693 /*! @{ */ 694 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 695 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 696 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 697 /*! @} */ 698 699 /*! @name GPOLYH - CRC_GPOLYH register. */ 700 /*! @{ */ 701 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 702 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 703 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 704 /*! @} */ 705 706 /*! @name GPOLY - CRC Polynomial register */ 707 /*! @{ */ 708 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 709 #define CRC_GPOLY_LOW_SHIFT (0U) 710 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 711 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 712 #define CRC_GPOLY_HIGH_SHIFT (16U) 713 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 714 /*! @} */ 715 716 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 717 /*! @{ */ 718 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 719 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 720 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 721 /*! @} */ 722 723 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 724 /*! @{ */ 725 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 726 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 727 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 728 /*! @} */ 729 730 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 731 /*! @{ */ 732 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 733 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 734 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 735 /*! @} */ 736 737 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 738 /*! @{ */ 739 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 740 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 741 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 742 /*! @} */ 743 744 /*! @name CTRL - CRC Control register */ 745 /*! @{ */ 746 #define CRC_CTRL_TCRC_MASK (0x1000000U) 747 #define CRC_CTRL_TCRC_SHIFT (24U) 748 /*! TCRC 749 * 0b0..16-bit CRC protocol. 750 * 0b1..32-bit CRC protocol. 751 */ 752 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 753 #define CRC_CTRL_WAS_MASK (0x2000000U) 754 #define CRC_CTRL_WAS_SHIFT (25U) 755 /*! WAS - Write CRC Data Register As Seed 756 * 0b0..Writes to the CRC data register are data values. 757 * 0b1..Writes to the CRC data register are seed values. 758 */ 759 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 760 #define CRC_CTRL_FXOR_MASK (0x4000000U) 761 #define CRC_CTRL_FXOR_SHIFT (26U) 762 /*! FXOR - Complement Read Of CRC Data Register 763 * 0b0..No XOR on reading. 764 * 0b1..Invert or complement the read value of the CRC Data register. 765 */ 766 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 767 #define CRC_CTRL_TOTR_MASK (0x30000000U) 768 #define CRC_CTRL_TOTR_SHIFT (28U) 769 /*! TOTR - Type Of Transpose For Read 770 * 0b00..No transposition. 771 * 0b01..Bits in bytes are transposed; bytes are not transposed. 772 * 0b10..Both bits in bytes and bytes are transposed. 773 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 774 */ 775 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 776 #define CRC_CTRL_TOT_MASK (0xC0000000U) 777 #define CRC_CTRL_TOT_SHIFT (30U) 778 /*! TOT - Type Of Transpose For Writes 779 * 0b00..No transposition. 780 * 0b01..Bits in bytes are transposed; bytes are not transposed. 781 * 0b10..Both bits in bytes and bytes are transposed. 782 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 783 */ 784 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 785 /*! @} */ 786 787 /*! @name CTRLHU - CRC_CTRLHU register. */ 788 /*! @{ */ 789 #define CRC_CTRLHU_TCRC_MASK (0x1U) 790 #define CRC_CTRLHU_TCRC_SHIFT (0U) 791 /*! TCRC 792 * 0b0..16-bit CRC protocol. 793 * 0b1..32-bit CRC protocol. 794 */ 795 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 796 #define CRC_CTRLHU_WAS_MASK (0x2U) 797 #define CRC_CTRLHU_WAS_SHIFT (1U) 798 /*! WAS 799 * 0b0..Writes to CRC data register are data values. 800 * 0b1..Writes to CRC data reguster are seed values. 801 */ 802 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 803 #define CRC_CTRLHU_FXOR_MASK (0x4U) 804 #define CRC_CTRLHU_FXOR_SHIFT (2U) 805 /*! FXOR 806 * 0b0..No XOR on reading. 807 * 0b1..Invert or complement the read value of CRC data register. 808 */ 809 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 810 #define CRC_CTRLHU_TOTR_MASK (0x30U) 811 #define CRC_CTRLHU_TOTR_SHIFT (4U) 812 /*! TOTR 813 * 0b00..No Transposition. 814 * 0b01..Bits in bytes are transposed, bytes are not transposed. 815 * 0b10..Both bits in bytes and bytes are transposed. 816 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 817 */ 818 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 819 #define CRC_CTRLHU_TOT_MASK (0xC0U) 820 #define CRC_CTRLHU_TOT_SHIFT (6U) 821 /*! TOT 822 * 0b00..No Transposition. 823 * 0b01..Bits in bytes are transposed, bytes are not transposed. 824 * 0b10..Both bits in bytes and bytes are transposed. 825 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 826 */ 827 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 828 /*! @} */ 829 830 831 /*! 832 * @} 833 */ /* end of group CRC_Register_Masks */ 834 835 836 /* CRC - Peripheral instance base addresses */ 837 /** Peripheral CRC base address */ 838 #define CRC_BASE (0x40032000u) 839 /** Peripheral CRC base pointer */ 840 #define CRC0 ((CRC_Type *)CRC_BASE) 841 /** Array initializer of CRC peripheral base addresses */ 842 #define CRC_BASE_ADDRS { CRC_BASE } 843 /** Array initializer of CRC peripheral base pointers */ 844 #define CRC_BASE_PTRS { CRC0 } 845 846 /*! 847 * @} 848 */ /* end of group CRC_Peripheral_Access_Layer */ 849 850 851 /* ---------------------------------------------------------------------------- 852 -- FGPIO Peripheral Access Layer 853 ---------------------------------------------------------------------------- */ 854 855 /*! 856 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 857 * @{ 858 */ 859 860 /** FGPIO - Register Layout Typedef */ 861 typedef struct { 862 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 863 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 864 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 865 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 866 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 867 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 868 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 869 } FGPIO_Type; 870 871 /* ---------------------------------------------------------------------------- 872 -- FGPIO Register Masks 873 ---------------------------------------------------------------------------- */ 874 875 /*! 876 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 877 * @{ 878 */ 879 880 /*! @name PDOR - Port Data Output Register */ 881 /*! @{ */ 882 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 883 #define FGPIO_PDOR_PDO_SHIFT (0U) 884 /*! PDO - Port Data Output 885 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 886 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 887 */ 888 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 889 /*! @} */ 890 891 /*! @name PSOR - Port Set Output Register */ 892 /*! @{ */ 893 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 894 #define FGPIO_PSOR_PTSO_SHIFT (0U) 895 /*! PTSO - Port Set Output 896 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 897 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 898 */ 899 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 900 /*! @} */ 901 902 /*! @name PCOR - Port Clear Output Register */ 903 /*! @{ */ 904 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 905 #define FGPIO_PCOR_PTCO_SHIFT (0U) 906 /*! PTCO - Port Clear Output 907 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 908 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 909 */ 910 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 911 /*! @} */ 912 913 /*! @name PTOR - Port Toggle Output Register */ 914 /*! @{ */ 915 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 916 #define FGPIO_PTOR_PTTO_SHIFT (0U) 917 /*! PTTO - Port Toggle Output 918 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 919 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 920 */ 921 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 922 /*! @} */ 923 924 /*! @name PDIR - Port Data Input Register */ 925 /*! @{ */ 926 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 927 #define FGPIO_PDIR_PDI_SHIFT (0U) 928 /*! PDI - Port Data Input 929 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 930 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 931 */ 932 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 933 /*! @} */ 934 935 /*! @name PDDR - Port Data Direction Register */ 936 /*! @{ */ 937 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 938 #define FGPIO_PDDR_PDD_SHIFT (0U) 939 /*! PDD - Port Data Direction 940 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register. 941 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 942 */ 943 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 944 /*! @} */ 945 946 /*! @name PIDR - Port Input Disable Register */ 947 /*! @{ */ 948 #define FGPIO_PIDR_PID_MASK (0xFFFFFFFFU) 949 #define FGPIO_PIDR_PID_SHIFT (0U) 950 /*! PID - Port Input Disable 951 * 0b00000000000000000000000000000000..Pin is configured for General Purpose Input, provided the pin is configured for any digital function. 952 * 0b00000000000000000000000000000001..Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will read zero. 953 */ 954 #define FGPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PIDR_PID_SHIFT)) & FGPIO_PIDR_PID_MASK) 955 /*! @} */ 956 957 958 /*! 959 * @} 960 */ /* end of group FGPIO_Register_Masks */ 961 962 963 /* FGPIO - Peripheral instance base addresses */ 964 /** Peripheral FGPIOA base address */ 965 #define FGPIOA_BASE (0xF8000000u) 966 /** Peripheral FGPIOA base pointer */ 967 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 968 /** Peripheral FGPIOB base address */ 969 #define FGPIOB_BASE (0xF8000040u) 970 /** Peripheral FGPIOB base pointer */ 971 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 972 /** Array initializer of FGPIO peripheral base addresses */ 973 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE } 974 /** Array initializer of FGPIO peripheral base pointers */ 975 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB } 976 977 /*! 978 * @} 979 */ /* end of group FGPIO_Peripheral_Access_Layer */ 980 981 982 /* ---------------------------------------------------------------------------- 983 -- FTM Peripheral Access Layer 984 ---------------------------------------------------------------------------- */ 985 986 /*! 987 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 988 * @{ 989 */ 990 991 /** FTM - Register Layout Typedef */ 992 typedef struct { 993 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 994 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 995 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 996 struct { /* offset: 0xC, array step: 0x8 */ 997 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 998 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 999 } CONTROLS[8]; 1000 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 1001 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 1002 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 1003 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 1004 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 1005 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 1006 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 1007 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ 1008 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 1009 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 1010 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 1011 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 1012 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 1013 uint8_t RESERVED_0[4]; 1014 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 1015 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 1016 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 1017 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 1018 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 1019 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 1020 } FTM_Type; 1021 1022 /* ---------------------------------------------------------------------------- 1023 -- FTM Register Masks 1024 ---------------------------------------------------------------------------- */ 1025 1026 /*! 1027 * @addtogroup FTM_Register_Masks FTM Register Masks 1028 * @{ 1029 */ 1030 1031 /*! @name SC - Status And Control */ 1032 /*! @{ */ 1033 #define FTM_SC_PS_MASK (0x7U) 1034 #define FTM_SC_PS_SHIFT (0U) 1035 /*! PS - Prescale Factor Selection 1036 * 0b000..Divide by 1 1037 * 0b001..Divide by 2 1038 * 0b010..Divide by 4 1039 * 0b011..Divide by 8 1040 * 0b100..Divide by 16 1041 * 0b101..Divide by 32 1042 * 0b110..Divide by 64 1043 * 0b111..Divide by 128 1044 */ 1045 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 1046 #define FTM_SC_CLKS_MASK (0x18U) 1047 #define FTM_SC_CLKS_SHIFT (3U) 1048 /*! CLKS - Clock Source Selection 1049 * 0b00..No clock selected. This in effect disables the FTM counter. 1050 * 0b01..System clock 1051 * 0b10..Fixed frequency clock 1052 * 0b11..External clock 1053 */ 1054 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 1055 #define FTM_SC_CPWMS_MASK (0x20U) 1056 #define FTM_SC_CPWMS_SHIFT (5U) 1057 /*! CPWMS - Center-Aligned PWM Select 1058 * 0b0..FTM counter operates in Up Counting mode. 1059 * 0b1..FTM counter operates in Up-Down Counting mode. 1060 */ 1061 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 1062 #define FTM_SC_TOIE_MASK (0x40U) 1063 #define FTM_SC_TOIE_SHIFT (6U) 1064 /*! TOIE - Timer Overflow Interrupt Enable 1065 * 0b0..Disable TOF interrupts. Use software polling. 1066 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. 1067 */ 1068 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 1069 #define FTM_SC_TOF_MASK (0x80U) 1070 #define FTM_SC_TOF_SHIFT (7U) 1071 /*! TOF - Timer Overflow Flag 1072 * 0b0..FTM counter has not overflowed. 1073 * 0b1..FTM counter has overflowed. 1074 */ 1075 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 1076 /*! @} */ 1077 1078 /*! @name CNT - Counter */ 1079 /*! @{ */ 1080 #define FTM_CNT_COUNT_MASK (0xFFFFU) 1081 #define FTM_CNT_COUNT_SHIFT (0U) 1082 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 1083 /*! @} */ 1084 1085 /*! @name MOD - Modulo */ 1086 /*! @{ */ 1087 #define FTM_MOD_MOD_MASK (0xFFFFU) 1088 #define FTM_MOD_MOD_SHIFT (0U) 1089 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 1090 /*! @} */ 1091 1092 /*! @name CnSC - Channel (n) Status And Control */ 1093 /*! @{ */ 1094 #define FTM_CnSC_ELSA_MASK (0x4U) 1095 #define FTM_CnSC_ELSA_SHIFT (2U) 1096 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 1097 #define FTM_CnSC_ELSB_MASK (0x8U) 1098 #define FTM_CnSC_ELSB_SHIFT (3U) 1099 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 1100 #define FTM_CnSC_MSA_MASK (0x10U) 1101 #define FTM_CnSC_MSA_SHIFT (4U) 1102 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 1103 #define FTM_CnSC_MSB_MASK (0x20U) 1104 #define FTM_CnSC_MSB_SHIFT (5U) 1105 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 1106 #define FTM_CnSC_CHIE_MASK (0x40U) 1107 #define FTM_CnSC_CHIE_SHIFT (6U) 1108 /*! CHIE - Channel Interrupt Enable 1109 * 0b0..Disable channel interrupts. Use software polling. 1110 * 0b1..Enable channel interrupts. 1111 */ 1112 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 1113 #define FTM_CnSC_CHF_MASK (0x80U) 1114 #define FTM_CnSC_CHF_SHIFT (7U) 1115 /*! CHF - Channel Flag 1116 * 0b0..No channel event has occurred. 1117 * 0b1..A channel event has occurred. 1118 */ 1119 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 1120 /*! @} */ 1121 1122 /* The count of FTM_CnSC */ 1123 #define FTM_CnSC_COUNT (8U) 1124 1125 /*! @name CnV - Channel (n) Value */ 1126 /*! @{ */ 1127 #define FTM_CnV_VAL_MASK (0xFFFFU) 1128 #define FTM_CnV_VAL_SHIFT (0U) 1129 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 1130 /*! @} */ 1131 1132 /* The count of FTM_CnV */ 1133 #define FTM_CnV_COUNT (8U) 1134 1135 /*! @name CNTIN - Counter Initial Value */ 1136 /*! @{ */ 1137 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 1138 #define FTM_CNTIN_INIT_SHIFT (0U) 1139 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 1140 /*! @} */ 1141 1142 /*! @name STATUS - Capture And Compare Status */ 1143 /*! @{ */ 1144 #define FTM_STATUS_CH0F_MASK (0x1U) 1145 #define FTM_STATUS_CH0F_SHIFT (0U) 1146 /*! CH0F - Channel 0 Flag 1147 * 0b0..No channel event has occurred. 1148 * 0b1..A channel event has occurred. 1149 */ 1150 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 1151 #define FTM_STATUS_CH1F_MASK (0x2U) 1152 #define FTM_STATUS_CH1F_SHIFT (1U) 1153 /*! CH1F - Channel 1 Flag 1154 * 0b0..No channel event has occurred. 1155 * 0b1..A channel event has occurred. 1156 */ 1157 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 1158 #define FTM_STATUS_CH2F_MASK (0x4U) 1159 #define FTM_STATUS_CH2F_SHIFT (2U) 1160 /*! CH2F - Channel 2 Flag 1161 * 0b0..No channel event has occurred. 1162 * 0b1..A channel event has occurred. 1163 */ 1164 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 1165 #define FTM_STATUS_CH3F_MASK (0x8U) 1166 #define FTM_STATUS_CH3F_SHIFT (3U) 1167 /*! CH3F - Channel 3 Flag 1168 * 0b0..No channel event has occurred. 1169 * 0b1..A channel event has occurred. 1170 */ 1171 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 1172 #define FTM_STATUS_CH4F_MASK (0x10U) 1173 #define FTM_STATUS_CH4F_SHIFT (4U) 1174 /*! CH4F - Channel 4 Flag 1175 * 0b0..No channel event has occurred. 1176 * 0b1..A channel event has occurred. 1177 */ 1178 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 1179 #define FTM_STATUS_CH5F_MASK (0x20U) 1180 #define FTM_STATUS_CH5F_SHIFT (5U) 1181 /*! CH5F - Channel 5 Flag 1182 * 0b0..No channel event has occurred. 1183 * 0b1..A channel event has occurred. 1184 */ 1185 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 1186 #define FTM_STATUS_CH6F_MASK (0x40U) 1187 #define FTM_STATUS_CH6F_SHIFT (6U) 1188 /*! CH6F - Channel 6 Flag 1189 * 0b0..No channel event has occurred. 1190 * 0b1..A channel event has occurred. 1191 */ 1192 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 1193 #define FTM_STATUS_CH7F_MASK (0x80U) 1194 #define FTM_STATUS_CH7F_SHIFT (7U) 1195 /*! CH7F - Channel 7 Flag 1196 * 0b0..No channel event has occurred. 1197 * 0b1..A channel event has occurred. 1198 */ 1199 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 1200 /*! @} */ 1201 1202 /*! @name MODE - Features Mode Selection */ 1203 /*! @{ */ 1204 #define FTM_MODE_FTMEN_MASK (0x1U) 1205 #define FTM_MODE_FTMEN_SHIFT (0U) 1206 /*! FTMEN - FTM Enable 1207 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 1208 * 0b1..Free running counter and synchronization are different from TPM behavior. 1209 */ 1210 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 1211 #define FTM_MODE_INIT_MASK (0x2U) 1212 #define FTM_MODE_INIT_SHIFT (1U) 1213 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 1214 #define FTM_MODE_WPDIS_MASK (0x4U) 1215 #define FTM_MODE_WPDIS_SHIFT (2U) 1216 /*! WPDIS - Write Protection Disable 1217 * 0b0..Write protection is enabled. 1218 * 0b1..Write protection is disabled. 1219 */ 1220 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 1221 #define FTM_MODE_PWMSYNC_MASK (0x8U) 1222 #define FTM_MODE_PWMSYNC_SHIFT (3U) 1223 /*! PWMSYNC - PWM Synchronization Mode 1224 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 1225 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. 1226 */ 1227 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 1228 #define FTM_MODE_CAPTEST_MASK (0x10U) 1229 #define FTM_MODE_CAPTEST_SHIFT (4U) 1230 /*! CAPTEST - Capture Test Mode Enable 1231 * 0b0..Capture test mode is disabled. 1232 * 0b1..Capture test mode is enabled. 1233 */ 1234 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 1235 #define FTM_MODE_FAULTM_MASK (0x60U) 1236 #define FTM_MODE_FAULTM_SHIFT (5U) 1237 /*! FAULTM - Fault Control Mode 1238 * 0b00..Fault control is disabled for all channels. 1239 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 1240 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 1241 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 1242 */ 1243 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 1244 #define FTM_MODE_FAULTIE_MASK (0x80U) 1245 #define FTM_MODE_FAULTIE_SHIFT (7U) 1246 /*! FAULTIE - Fault Interrupt Enable 1247 * 0b0..Fault control interrupt is disabled. 1248 * 0b1..Fault control interrupt is enabled. 1249 */ 1250 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 1251 /*! @} */ 1252 1253 /*! @name SYNC - Synchronization */ 1254 /*! @{ */ 1255 #define FTM_SYNC_CNTMIN_MASK (0x1U) 1256 #define FTM_SYNC_CNTMIN_SHIFT (0U) 1257 /*! CNTMIN - Minimum Loading Point Enable 1258 * 0b0..The minimum loading point is disabled. 1259 * 0b1..The minimum loading point is enabled. 1260 */ 1261 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 1262 #define FTM_SYNC_CNTMAX_MASK (0x2U) 1263 #define FTM_SYNC_CNTMAX_SHIFT (1U) 1264 /*! CNTMAX - Maximum Loading Point Enable 1265 * 0b0..The maximum loading point is disabled. 1266 * 0b1..The maximum loading point is enabled. 1267 */ 1268 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 1269 #define FTM_SYNC_REINIT_MASK (0x4U) 1270 #define FTM_SYNC_REINIT_SHIFT (2U) 1271 /*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 1272 * 0b0..FTM counter continues to count normally. 1273 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. 1274 */ 1275 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 1276 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 1277 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 1278 /*! SYNCHOM - Output Mask Synchronization 1279 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 1280 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 1281 */ 1282 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 1283 #define FTM_SYNC_TRIG0_MASK (0x10U) 1284 #define FTM_SYNC_TRIG0_SHIFT (4U) 1285 /*! TRIG0 - PWM Synchronization Hardware Trigger 0 1286 * 0b0..Trigger is disabled. 1287 * 0b1..Trigger is enabled. 1288 */ 1289 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 1290 #define FTM_SYNC_TRIG1_MASK (0x20U) 1291 #define FTM_SYNC_TRIG1_SHIFT (5U) 1292 /*! TRIG1 - PWM Synchronization Hardware Trigger 1 1293 * 0b0..Trigger is disabled. 1294 * 0b1..Trigger is enabled. 1295 */ 1296 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 1297 #define FTM_SYNC_TRIG2_MASK (0x40U) 1298 #define FTM_SYNC_TRIG2_SHIFT (6U) 1299 /*! TRIG2 - PWM Synchronization Hardware Trigger 2 1300 * 0b0..Trigger is disabled. 1301 * 0b1..Trigger is enabled. 1302 */ 1303 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 1304 #define FTM_SYNC_SWSYNC_MASK (0x80U) 1305 #define FTM_SYNC_SWSYNC_SHIFT (7U) 1306 /*! SWSYNC - PWM Synchronization Software Trigger 1307 * 0b0..Software trigger is not selected. 1308 * 0b1..Software trigger is selected. 1309 */ 1310 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 1311 /*! @} */ 1312 1313 /*! @name OUTINIT - Initial State For Channels Output */ 1314 /*! @{ */ 1315 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 1316 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 1317 /*! CH0OI - Channel 0 Output Initialization Value 1318 * 0b0..The initialization value is 0. 1319 * 0b1..The initialization value is 1. 1320 */ 1321 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 1322 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 1323 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 1324 /*! CH1OI - Channel 1 Output Initialization Value 1325 * 0b0..The initialization value is 0. 1326 * 0b1..The initialization value is 1. 1327 */ 1328 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 1329 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 1330 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 1331 /*! CH2OI - Channel 2 Output Initialization Value 1332 * 0b0..The initialization value is 0. 1333 * 0b1..The initialization value is 1. 1334 */ 1335 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 1336 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 1337 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 1338 /*! CH3OI - Channel 3 Output Initialization Value 1339 * 0b0..The initialization value is 0. 1340 * 0b1..The initialization value is 1. 1341 */ 1342 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 1343 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 1344 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 1345 /*! CH4OI - Channel 4 Output Initialization Value 1346 * 0b0..The initialization value is 0. 1347 * 0b1..The initialization value is 1. 1348 */ 1349 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 1350 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 1351 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 1352 /*! CH5OI - Channel 5 Output Initialization Value 1353 * 0b0..The initialization value is 0. 1354 * 0b1..The initialization value is 1. 1355 */ 1356 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 1357 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 1358 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 1359 /*! CH6OI - Channel 6 Output Initialization Value 1360 * 0b0..The initialization value is 0. 1361 * 0b1..The initialization value is 1. 1362 */ 1363 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 1364 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 1365 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 1366 /*! CH7OI - Channel 7 Output Initialization Value 1367 * 0b0..The initialization value is 0. 1368 * 0b1..The initialization value is 1. 1369 */ 1370 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 1371 /*! @} */ 1372 1373 /*! @name OUTMASK - Output Mask */ 1374 /*! @{ */ 1375 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 1376 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 1377 /*! CH0OM - Channel 0 Output Mask 1378 * 0b0..Channel output is not masked. It continues to operate normally. 1379 * 0b1..Channel output is masked. It is forced to its inactive state. 1380 */ 1381 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 1382 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 1383 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 1384 /*! CH1OM - Channel 1 Output Mask 1385 * 0b0..Channel output is not masked. It continues to operate normally. 1386 * 0b1..Channel output is masked. It is forced to its inactive state. 1387 */ 1388 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 1389 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 1390 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 1391 /*! CH2OM - Channel 2 Output Mask 1392 * 0b0..Channel output is not masked. It continues to operate normally. 1393 * 0b1..Channel output is masked. It is forced to its inactive state. 1394 */ 1395 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 1396 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 1397 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 1398 /*! CH3OM - Channel 3 Output Mask 1399 * 0b0..Channel output is not masked. It continues to operate normally. 1400 * 0b1..Channel output is masked. It is forced to its inactive state. 1401 */ 1402 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 1403 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 1404 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 1405 /*! CH4OM - Channel 4 Output Mask 1406 * 0b0..Channel output is not masked. It continues to operate normally. 1407 * 0b1..Channel output is masked. It is forced to its inactive state. 1408 */ 1409 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 1410 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 1411 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 1412 /*! CH5OM - Channel 5 Output Mask 1413 * 0b0..Channel output is not masked. It continues to operate normally. 1414 * 0b1..Channel output is masked. It is forced to its inactive state. 1415 */ 1416 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 1417 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 1418 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 1419 /*! CH6OM - Channel 6 Output Mask 1420 * 0b0..Channel output is not masked. It continues to operate normally. 1421 * 0b1..Channel output is masked. It is forced to its inactive state. 1422 */ 1423 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 1424 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 1425 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 1426 /*! CH7OM - Channel 7 Output Mask 1427 * 0b0..Channel output is not masked. It continues to operate normally. 1428 * 0b1..Channel output is masked. It is forced to its inactive state. 1429 */ 1430 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 1431 /*! @} */ 1432 1433 /*! @name COMBINE - Function For Linked Channels */ 1434 /*! @{ */ 1435 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 1436 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 1437 /*! COMBINE0 - Combine Channels For n = 0 1438 * 0b0..Channels (n) and (n+1) are independent. 1439 * 0b1..Channels (n) and (n+1) are combined. 1440 */ 1441 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 1442 #define FTM_COMBINE_COMP0_MASK (0x2U) 1443 #define FTM_COMBINE_COMP0_SHIFT (1U) 1444 /*! COMP0 - Complement Of Channel (n) For n = 0 1445 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1446 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1447 */ 1448 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 1449 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 1450 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 1451 /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 1452 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1453 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1454 */ 1455 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 1456 #define FTM_COMBINE_DECAP0_MASK (0x8U) 1457 #define FTM_COMBINE_DECAP0_SHIFT (3U) 1458 /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 1459 * 0b0..The dual edge captures are inactive. 1460 * 0b1..The dual edge captures are active. 1461 */ 1462 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 1463 #define FTM_COMBINE_DTEN0_MASK (0x10U) 1464 #define FTM_COMBINE_DTEN0_SHIFT (4U) 1465 /*! DTEN0 - Deadtime Enable For n = 0 1466 * 0b0..The deadtime insertion in this pair of channels is disabled. 1467 * 0b1..The deadtime insertion in this pair of channels is enabled. 1468 */ 1469 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 1470 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 1471 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 1472 /*! SYNCEN0 - Synchronization Enable For n = 0 1473 * 0b0..The PWM synchronization in this pair of channels is disabled. 1474 * 0b1..The PWM synchronization in this pair of channels is enabled. 1475 */ 1476 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 1477 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 1478 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 1479 /*! FAULTEN0 - Fault Control Enable For n = 0 1480 * 0b0..The fault control in this pair of channels is disabled. 1481 * 0b1..The fault control in this pair of channels is enabled. 1482 */ 1483 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 1484 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 1485 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 1486 /*! COMBINE1 - Combine Channels For n = 2 1487 * 0b0..Channels (n) and (n+1) are independent. 1488 * 0b1..Channels (n) and (n+1) are combined. 1489 */ 1490 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 1491 #define FTM_COMBINE_COMP1_MASK (0x200U) 1492 #define FTM_COMBINE_COMP1_SHIFT (9U) 1493 /*! COMP1 - Complement Of Channel (n) For n = 2 1494 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1495 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1496 */ 1497 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 1498 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 1499 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 1500 /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 1501 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1502 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1503 */ 1504 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 1505 #define FTM_COMBINE_DECAP1_MASK (0x800U) 1506 #define FTM_COMBINE_DECAP1_SHIFT (11U) 1507 /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 1508 * 0b0..The dual edge captures are inactive. 1509 * 0b1..The dual edge captures are active. 1510 */ 1511 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 1512 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 1513 #define FTM_COMBINE_DTEN1_SHIFT (12U) 1514 /*! DTEN1 - Deadtime Enable For n = 2 1515 * 0b0..The deadtime insertion in this pair of channels is disabled. 1516 * 0b1..The deadtime insertion in this pair of channels is enabled. 1517 */ 1518 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 1519 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 1520 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 1521 /*! SYNCEN1 - Synchronization Enable For n = 2 1522 * 0b0..The PWM synchronization in this pair of channels is disabled. 1523 * 0b1..The PWM synchronization in this pair of channels is enabled. 1524 */ 1525 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 1526 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 1527 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 1528 /*! FAULTEN1 - Fault Control Enable For n = 2 1529 * 0b0..The fault control in this pair of channels is disabled. 1530 * 0b1..The fault control in this pair of channels is enabled. 1531 */ 1532 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 1533 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 1534 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 1535 /*! COMBINE2 - Combine Channels For n = 4 1536 * 0b0..Channels (n) and (n+1) are independent. 1537 * 0b1..Channels (n) and (n+1) are combined. 1538 */ 1539 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 1540 #define FTM_COMBINE_COMP2_MASK (0x20000U) 1541 #define FTM_COMBINE_COMP2_SHIFT (17U) 1542 /*! COMP2 - Complement Of Channel (n) For n = 4 1543 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1544 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1545 */ 1546 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 1547 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 1548 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 1549 /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 1550 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1551 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1552 */ 1553 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 1554 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 1555 #define FTM_COMBINE_DECAP2_SHIFT (19U) 1556 /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 1557 * 0b0..The dual edge captures are inactive. 1558 * 0b1..The dual edge captures are active. 1559 */ 1560 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 1561 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 1562 #define FTM_COMBINE_DTEN2_SHIFT (20U) 1563 /*! DTEN2 - Deadtime Enable For n = 4 1564 * 0b0..The deadtime insertion in this pair of channels is disabled. 1565 * 0b1..The deadtime insertion in this pair of channels is enabled. 1566 */ 1567 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 1568 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 1569 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 1570 /*! SYNCEN2 - Synchronization Enable For n = 4 1571 * 0b0..The PWM synchronization in this pair of channels is disabled. 1572 * 0b1..The PWM synchronization in this pair of channels is enabled. 1573 */ 1574 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 1575 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 1576 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 1577 /*! FAULTEN2 - Fault Control Enable For n = 4 1578 * 0b0..The fault control in this pair of channels is disabled. 1579 * 0b1..The fault control in this pair of channels is enabled. 1580 */ 1581 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 1582 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 1583 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 1584 /*! COMBINE3 - Combine Channels For n = 6 1585 * 0b0..Channels (n) and (n+1) are independent. 1586 * 0b1..Channels (n) and (n+1) are combined. 1587 */ 1588 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 1589 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 1590 #define FTM_COMBINE_COMP3_SHIFT (25U) 1591 /*! COMP3 - Complement Of Channel (n) for n = 6 1592 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1593 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1594 */ 1595 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 1596 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 1597 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 1598 /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 1599 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1600 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1601 */ 1602 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 1603 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 1604 #define FTM_COMBINE_DECAP3_SHIFT (27U) 1605 /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 1606 * 0b0..The dual edge captures are inactive. 1607 * 0b1..The dual edge captures are active. 1608 */ 1609 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 1610 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 1611 #define FTM_COMBINE_DTEN3_SHIFT (28U) 1612 /*! DTEN3 - Deadtime Enable For n = 6 1613 * 0b0..The deadtime insertion in this pair of channels is disabled. 1614 * 0b1..The deadtime insertion in this pair of channels is enabled. 1615 */ 1616 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 1617 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 1618 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 1619 /*! SYNCEN3 - Synchronization Enable For n = 6 1620 * 0b0..The PWM synchronization in this pair of channels is disabled. 1621 * 0b1..The PWM synchronization in this pair of channels is enabled. 1622 */ 1623 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 1624 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 1625 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 1626 /*! FAULTEN3 - Fault Control Enable For n = 6 1627 * 0b0..The fault control in this pair of channels is disabled. 1628 * 0b1..The fault control in this pair of channels is enabled. 1629 */ 1630 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 1631 /*! @} */ 1632 1633 /*! @name DEADTIME - Deadtime Insertion Control */ 1634 /*! @{ */ 1635 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 1636 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 1637 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 1638 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 1639 #define FTM_DEADTIME_DTPS_SHIFT (6U) 1640 /*! DTPS - Deadtime Prescaler Value 1641 * 0b0x..Divide the system clock by 1. 1642 * 0b10..Divide the system clock by 4. 1643 * 0b11..Divide the system clock by 16. 1644 */ 1645 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 1646 /*! @} */ 1647 1648 /*! @name EXTTRIG - FTM External Trigger */ 1649 /*! @{ */ 1650 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 1651 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 1652 /*! CH2TRIG - Channel 2 Trigger Enable 1653 * 0b0..The generation of the channel trigger is disabled. 1654 * 0b1..The generation of the channel trigger is enabled. 1655 */ 1656 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 1657 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 1658 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 1659 /*! CH3TRIG - Channel 3 Trigger Enable 1660 * 0b0..The generation of the channel trigger is disabled. 1661 * 0b1..The generation of the channel trigger is enabled. 1662 */ 1663 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 1664 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 1665 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 1666 /*! CH4TRIG - Channel 4 Trigger Enable 1667 * 0b0..The generation of the channel trigger is disabled. 1668 * 0b1..The generation of the channel trigger is enabled. 1669 */ 1670 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 1671 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 1672 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 1673 /*! CH5TRIG - Channel 5 Trigger Enable 1674 * 0b0..The generation of the channel trigger is disabled. 1675 * 0b1..The generation of the channel trigger is enabled. 1676 */ 1677 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 1678 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 1679 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 1680 /*! CH0TRIG - Channel 0 Trigger Enable 1681 * 0b0..The generation of the channel trigger is disabled. 1682 * 0b1..The generation of the channel trigger is enabled. 1683 */ 1684 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 1685 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 1686 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 1687 /*! CH1TRIG - Channel 1 Trigger Enable 1688 * 0b0..The generation of the channel trigger is disabled. 1689 * 0b1..The generation of the channel trigger is enabled. 1690 */ 1691 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 1692 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 1693 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 1694 /*! INITTRIGEN - Initialization Trigger Enable 1695 * 0b0..The generation of initialization trigger is disabled. 1696 * 0b1..The generation of initialization trigger is enabled. 1697 */ 1698 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 1699 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 1700 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 1701 /*! TRIGF - Channel Trigger Flag 1702 * 0b0..No channel trigger was generated. 1703 * 0b1..A channel trigger was generated. 1704 */ 1705 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 1706 /*! @} */ 1707 1708 /*! @name POL - Channels Polarity */ 1709 /*! @{ */ 1710 #define FTM_POL_POL0_MASK (0x1U) 1711 #define FTM_POL_POL0_SHIFT (0U) 1712 /*! POL0 - Channel 0 Polarity 1713 * 0b0..The channel polarity is active high. 1714 * 0b1..The channel polarity is active low. 1715 */ 1716 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 1717 #define FTM_POL_POL1_MASK (0x2U) 1718 #define FTM_POL_POL1_SHIFT (1U) 1719 /*! POL1 - Channel 1 Polarity 1720 * 0b0..The channel polarity is active high. 1721 * 0b1..The channel polarity is active low. 1722 */ 1723 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 1724 #define FTM_POL_POL2_MASK (0x4U) 1725 #define FTM_POL_POL2_SHIFT (2U) 1726 /*! POL2 - Channel 2 Polarity 1727 * 0b0..The channel polarity is active high. 1728 * 0b1..The channel polarity is active low. 1729 */ 1730 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 1731 #define FTM_POL_POL3_MASK (0x8U) 1732 #define FTM_POL_POL3_SHIFT (3U) 1733 /*! POL3 - Channel 3 Polarity 1734 * 0b0..The channel polarity is active high. 1735 * 0b1..The channel polarity is active low. 1736 */ 1737 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 1738 #define FTM_POL_POL4_MASK (0x10U) 1739 #define FTM_POL_POL4_SHIFT (4U) 1740 /*! POL4 - Channel 4 Polarity 1741 * 0b0..The channel polarity is active high. 1742 * 0b1..The channel polarity is active low. 1743 */ 1744 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 1745 #define FTM_POL_POL5_MASK (0x20U) 1746 #define FTM_POL_POL5_SHIFT (5U) 1747 /*! POL5 - Channel 5 Polarity 1748 * 0b0..The channel polarity is active high. 1749 * 0b1..The channel polarity is active low. 1750 */ 1751 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 1752 #define FTM_POL_POL6_MASK (0x40U) 1753 #define FTM_POL_POL6_SHIFT (6U) 1754 /*! POL6 - Channel 6 Polarity 1755 * 0b0..The channel polarity is active high. 1756 * 0b1..The channel polarity is active low. 1757 */ 1758 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 1759 #define FTM_POL_POL7_MASK (0x80U) 1760 #define FTM_POL_POL7_SHIFT (7U) 1761 /*! POL7 - Channel 7 Polarity 1762 * 0b0..The channel polarity is active high. 1763 * 0b1..The channel polarity is active low. 1764 */ 1765 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 1766 /*! @} */ 1767 1768 /*! @name FMS - Fault Mode Status */ 1769 /*! @{ */ 1770 #define FTM_FMS_FAULTF0_MASK (0x1U) 1771 #define FTM_FMS_FAULTF0_SHIFT (0U) 1772 /*! FAULTF0 - Fault Detection Flag 0 1773 * 0b0..No fault condition was detected at the fault input. 1774 * 0b1..A fault condition was detected at the fault input. 1775 */ 1776 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 1777 #define FTM_FMS_FAULTF1_MASK (0x2U) 1778 #define FTM_FMS_FAULTF1_SHIFT (1U) 1779 /*! FAULTF1 - Fault Detection Flag 1 1780 * 0b0..No fault condition was detected at the fault input. 1781 * 0b1..A fault condition was detected at the fault input. 1782 */ 1783 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 1784 #define FTM_FMS_FAULTF2_MASK (0x4U) 1785 #define FTM_FMS_FAULTF2_SHIFT (2U) 1786 /*! FAULTF2 - Fault Detection Flag 2 1787 * 0b0..No fault condition was detected at the fault input. 1788 * 0b1..A fault condition was detected at the fault input. 1789 */ 1790 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 1791 #define FTM_FMS_FAULTF3_MASK (0x8U) 1792 #define FTM_FMS_FAULTF3_SHIFT (3U) 1793 /*! FAULTF3 - Fault Detection Flag 3 1794 * 0b0..No fault condition was detected at the fault input. 1795 * 0b1..A fault condition was detected at the fault input. 1796 */ 1797 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 1798 #define FTM_FMS_FAULTIN_MASK (0x20U) 1799 #define FTM_FMS_FAULTIN_SHIFT (5U) 1800 /*! FAULTIN - Fault Inputs 1801 * 0b0..The logic OR of the enabled fault inputs is 0. 1802 * 0b1..The logic OR of the enabled fault inputs is 1. 1803 */ 1804 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 1805 #define FTM_FMS_WPEN_MASK (0x40U) 1806 #define FTM_FMS_WPEN_SHIFT (6U) 1807 /*! WPEN - Write Protection Enable 1808 * 0b0..Write protection is disabled. Write protected bits can be written. 1809 * 0b1..Write protection is enabled. Write protected bits cannot be written. 1810 */ 1811 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 1812 #define FTM_FMS_FAULTF_MASK (0x80U) 1813 #define FTM_FMS_FAULTF_SHIFT (7U) 1814 /*! FAULTF - Fault Detection Flag 1815 * 0b0..No fault condition was detected. 1816 * 0b1..A fault condition was detected. 1817 */ 1818 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 1819 /*! @} */ 1820 1821 /*! @name FILTER - Input Capture Filter Control */ 1822 /*! @{ */ 1823 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 1824 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 1825 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 1826 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 1827 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 1828 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 1829 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 1830 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 1831 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 1832 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 1833 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 1834 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 1835 /*! @} */ 1836 1837 /*! @name FLTCTRL - Fault Control */ 1838 /*! @{ */ 1839 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 1840 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 1841 /*! FAULT0EN - Fault Input 0 Enable 1842 * 0b0..Fault input is disabled. 1843 * 0b1..Fault input is enabled. 1844 */ 1845 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 1846 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 1847 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 1848 /*! FAULT1EN - Fault Input 1 Enable 1849 * 0b0..Fault input is disabled. 1850 * 0b1..Fault input is enabled. 1851 */ 1852 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 1853 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 1854 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 1855 /*! FAULT2EN - Fault Input 2 Enable 1856 * 0b0..Fault input is disabled. 1857 * 0b1..Fault input is enabled. 1858 */ 1859 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 1860 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 1861 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 1862 /*! FAULT3EN - Fault Input 3 Enable 1863 * 0b0..Fault input is disabled. 1864 * 0b1..Fault input is enabled. 1865 */ 1866 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 1867 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 1868 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 1869 /*! FFLTR0EN - Fault Input 0 Filter Enable 1870 * 0b0..Fault input filter is disabled. 1871 * 0b1..Fault input filter is enabled. 1872 */ 1873 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 1874 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 1875 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 1876 /*! FFLTR1EN - Fault Input 1 Filter Enable 1877 * 0b0..Fault input filter is disabled. 1878 * 0b1..Fault input filter is enabled. 1879 */ 1880 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 1881 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 1882 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 1883 /*! FFLTR2EN - Fault Input 2 Filter Enable 1884 * 0b0..Fault input filter is disabled. 1885 * 0b1..Fault input filter is enabled. 1886 */ 1887 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 1888 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 1889 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 1890 /*! FFLTR3EN - Fault Input 3 Filter Enable 1891 * 0b0..Fault input filter is disabled. 1892 * 0b1..Fault input filter is enabled. 1893 */ 1894 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 1895 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 1896 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 1897 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 1898 /*! @} */ 1899 1900 /*! @name CONF - Configuration */ 1901 /*! @{ */ 1902 #define FTM_CONF_NUMTOF_MASK (0x1FU) 1903 #define FTM_CONF_NUMTOF_SHIFT (0U) 1904 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) 1905 #define FTM_CONF_BDMMODE_MASK (0xC0U) 1906 #define FTM_CONF_BDMMODE_SHIFT (6U) 1907 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 1908 #define FTM_CONF_GTBEEN_MASK (0x200U) 1909 #define FTM_CONF_GTBEEN_SHIFT (9U) 1910 /*! GTBEEN - Global Time Base Enable 1911 * 0b0..Use of an external global time base is disabled. 1912 * 0b1..Use of an external global time base is enabled. 1913 */ 1914 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 1915 #define FTM_CONF_GTBEOUT_MASK (0x400U) 1916 #define FTM_CONF_GTBEOUT_SHIFT (10U) 1917 /*! GTBEOUT - Global Time Base Output 1918 * 0b0..A global time base signal generation is disabled. 1919 * 0b1..A global time base signal generation is enabled. 1920 */ 1921 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 1922 /*! @} */ 1923 1924 /*! @name FLTPOL - FTM Fault Input Polarity */ 1925 /*! @{ */ 1926 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 1927 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 1928 /*! FLT0POL - Fault Input 0 Polarity 1929 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1930 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1931 */ 1932 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 1933 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 1934 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 1935 /*! FLT1POL - Fault Input 1 Polarity 1936 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1937 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1938 */ 1939 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 1940 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 1941 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 1942 /*! FLT2POL - Fault Input 2 Polarity 1943 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1944 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1945 */ 1946 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 1947 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 1948 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 1949 /*! FLT3POL - Fault Input 3 Polarity 1950 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1951 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1952 */ 1953 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 1954 /*! @} */ 1955 1956 /*! @name SYNCONF - Synchronization Configuration */ 1957 /*! @{ */ 1958 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 1959 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 1960 /*! HWTRIGMODE - Hardware Trigger Mode 1961 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 1962 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 1963 */ 1964 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 1965 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 1966 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 1967 /*! CNTINC - CNTIN Register Synchronization 1968 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 1969 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. 1970 */ 1971 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 1972 #define FTM_SYNCONF_INVC_MASK (0x10U) 1973 #define FTM_SYNCONF_INVC_SHIFT (4U) 1974 /*! INVC - INVCTRL Register Synchronization 1975 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 1976 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. 1977 */ 1978 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 1979 #define FTM_SYNCONF_SWOC_MASK (0x20U) 1980 #define FTM_SYNCONF_SWOC_SHIFT (5U) 1981 /*! SWOC - SWOCTRL Register Synchronization 1982 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 1983 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. 1984 */ 1985 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 1986 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 1987 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 1988 /*! SYNCMODE - Synchronization Mode 1989 * 0b0..Legacy PWM synchronization is selected. 1990 * 0b1..Enhanced PWM synchronization is selected. 1991 */ 1992 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 1993 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 1994 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 1995 /*! SWRSTCNT 1996 * 0b0..The software trigger does not activate the FTM counter synchronization. 1997 * 0b1..The software trigger activates the FTM counter synchronization. 1998 */ 1999 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 2000 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 2001 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 2002 /*! SWWRBUF 2003 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 2004 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization. 2005 */ 2006 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 2007 #define FTM_SYNCONF_SWOM_MASK (0x400U) 2008 #define FTM_SYNCONF_SWOM_SHIFT (10U) 2009 /*! SWOM 2010 * 0b0..The software trigger does not activate the OUTMASK register synchronization. 2011 * 0b1..The software trigger activates the OUTMASK register synchronization. 2012 */ 2013 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 2014 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 2015 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 2016 /*! SWINVC 2017 * 0b0..The software trigger does not activate the INVCTRL register synchronization. 2018 * 0b1..The software trigger activates the INVCTRL register synchronization. 2019 */ 2020 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 2021 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 2022 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 2023 /*! SWSOC 2024 * 0b0..The software trigger does not activate the SWOCTRL register synchronization. 2025 * 0b1..The software trigger activates the SWOCTRL register synchronization. 2026 */ 2027 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 2028 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 2029 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 2030 /*! HWRSTCNT 2031 * 0b0..A hardware trigger does not activate the FTM counter synchronization. 2032 * 0b1..A hardware trigger activates the FTM counter synchronization. 2033 */ 2034 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 2035 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 2036 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 2037 /*! HWWRBUF 2038 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 2039 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization. 2040 */ 2041 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 2042 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 2043 #define FTM_SYNCONF_HWOM_SHIFT (18U) 2044 /*! HWOM 2045 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 2046 * 0b1..A hardware trigger activates the OUTMASK register synchronization. 2047 */ 2048 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 2049 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 2050 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 2051 /*! HWINVC 2052 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 2053 * 0b1..A hardware trigger activates the INVCTRL register synchronization. 2054 */ 2055 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 2056 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 2057 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 2058 /*! HWSOC 2059 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 2060 * 0b1..A hardware trigger activates the SWOCTRL register synchronization. 2061 */ 2062 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 2063 /*! @} */ 2064 2065 /*! @name INVCTRL - FTM Inverting Control */ 2066 /*! @{ */ 2067 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 2068 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 2069 /*! INV0EN - Pair Channels 0 Inverting Enable 2070 * 0b0..Inverting is disabled. 2071 * 0b1..Inverting is enabled. 2072 */ 2073 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 2074 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 2075 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 2076 /*! INV1EN - Pair Channels 1 Inverting Enable 2077 * 0b0..Inverting is disabled. 2078 * 0b1..Inverting is enabled. 2079 */ 2080 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 2081 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 2082 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 2083 /*! INV2EN - Pair Channels 2 Inverting Enable 2084 * 0b0..Inverting is disabled. 2085 * 0b1..Inverting is enabled. 2086 */ 2087 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 2088 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 2089 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 2090 /*! INV3EN - Pair Channels 3 Inverting Enable 2091 * 0b0..Inverting is disabled. 2092 * 0b1..Inverting is enabled. 2093 */ 2094 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 2095 /*! @} */ 2096 2097 /*! @name SWOCTRL - FTM Software Output Control */ 2098 /*! @{ */ 2099 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 2100 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 2101 /*! CH0OC - Channel 0 Software Output Control Enable 2102 * 0b0..The channel output is not affected by software output control. 2103 * 0b1..The channel output is affected by software output control. 2104 */ 2105 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 2106 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 2107 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 2108 /*! CH1OC - Channel 1 Software Output Control Enable 2109 * 0b0..The channel output is not affected by software output control. 2110 * 0b1..The channel output is affected by software output control. 2111 */ 2112 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 2113 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 2114 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 2115 /*! CH2OC - Channel 2 Software Output Control Enable 2116 * 0b0..The channel output is not affected by software output control. 2117 * 0b1..The channel output is affected by software output control. 2118 */ 2119 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 2120 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 2121 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 2122 /*! CH3OC - Channel 3 Software Output Control Enable 2123 * 0b0..The channel output is not affected by software output control. 2124 * 0b1..The channel output is affected by software output control. 2125 */ 2126 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 2127 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 2128 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 2129 /*! CH4OC - Channel 4 Software Output Control Enable 2130 * 0b0..The channel output is not affected by software output control. 2131 * 0b1..The channel output is affected by software output control. 2132 */ 2133 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 2134 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 2135 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 2136 /*! CH5OC - Channel 5 Software Output Control Enable 2137 * 0b0..The channel output is not affected by software output control. 2138 * 0b1..The channel output is affected by software output control. 2139 */ 2140 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 2141 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 2142 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 2143 /*! CH6OC - Channel 6 Software Output Control Enable 2144 * 0b0..The channel output is not affected by software output control. 2145 * 0b1..The channel output is affected by software output control. 2146 */ 2147 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 2148 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 2149 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 2150 /*! CH7OC - Channel 7 Software Output Control Enable 2151 * 0b0..The channel output is not affected by software output control. 2152 * 0b1..The channel output is affected by software output control. 2153 */ 2154 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 2155 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 2156 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 2157 /*! CH0OCV - Channel 0 Software Output Control Value 2158 * 0b0..The software output control forces 0 to the channel output. 2159 * 0b1..The software output control forces 1 to the channel output. 2160 */ 2161 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 2162 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 2163 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 2164 /*! CH1OCV - Channel 1 Software Output Control Value 2165 * 0b0..The software output control forces 0 to the channel output. 2166 * 0b1..The software output control forces 1 to the channel output. 2167 */ 2168 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 2169 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 2170 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 2171 /*! CH2OCV - Channel 2 Software Output Control Value 2172 * 0b0..The software output control forces 0 to the channel output. 2173 * 0b1..The software output control forces 1 to the channel output. 2174 */ 2175 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 2176 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 2177 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 2178 /*! CH3OCV - Channel 3 Software Output Control Value 2179 * 0b0..The software output control forces 0 to the channel output. 2180 * 0b1..The software output control forces 1 to the channel output. 2181 */ 2182 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 2183 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 2184 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 2185 /*! CH4OCV - Channel 4 Software Output Control Value 2186 * 0b0..The software output control forces 0 to the channel output. 2187 * 0b1..The software output control forces 1 to the channel output. 2188 */ 2189 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 2190 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 2191 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 2192 /*! CH5OCV - Channel 5 Software Output Control Value 2193 * 0b0..The software output control forces 0 to the channel output. 2194 * 0b1..The software output control forces 1 to the channel output. 2195 */ 2196 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 2197 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 2198 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 2199 /*! CH6OCV - Channel 6 Software Output Control Value 2200 * 0b0..The software output control forces 0 to the channel output. 2201 * 0b1..The software output control forces 1 to the channel output. 2202 */ 2203 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 2204 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 2205 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 2206 /*! CH7OCV - Channel 7 Software Output Control Value 2207 * 0b0..The software output control forces 0 to the channel output. 2208 * 0b1..The software output control forces 1 to the channel output. 2209 */ 2210 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 2211 /*! @} */ 2212 2213 /*! @name PWMLOAD - FTM PWM Load */ 2214 /*! @{ */ 2215 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 2216 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 2217 /*! CH0SEL - Channel 0 Select 2218 * 0b0..Do not include the channel in the matching process. 2219 * 0b1..Include the channel in the matching process. 2220 */ 2221 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 2222 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 2223 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 2224 /*! CH1SEL - Channel 1 Select 2225 * 0b0..Do not include the channel in the matching process. 2226 * 0b1..Include the channel in the matching process. 2227 */ 2228 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 2229 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 2230 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 2231 /*! CH2SEL - Channel 2 Select 2232 * 0b0..Do not include the channel in the matching process. 2233 * 0b1..Include the channel in the matching process. 2234 */ 2235 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 2236 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 2237 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 2238 /*! CH3SEL - Channel 3 Select 2239 * 0b0..Do not include the channel in the matching process. 2240 * 0b1..Include the channel in the matching process. 2241 */ 2242 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 2243 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 2244 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 2245 /*! CH4SEL - Channel 4 Select 2246 * 0b0..Do not include the channel in the matching process. 2247 * 0b1..Include the channel in the matching process. 2248 */ 2249 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 2250 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 2251 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 2252 /*! CH5SEL - Channel 5 Select 2253 * 0b0..Do not include the channel in the matching process. 2254 * 0b1..Include the channel in the matching process. 2255 */ 2256 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 2257 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 2258 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 2259 /*! CH6SEL - Channel 6 Select 2260 * 0b0..Do not include the channel in the matching process. 2261 * 0b1..Include the channel in the matching process. 2262 */ 2263 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 2264 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 2265 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 2266 /*! CH7SEL - Channel 7 Select 2267 * 0b0..Do not include the channel in the matching process. 2268 * 0b1..Include the channel in the matching process. 2269 */ 2270 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 2271 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 2272 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 2273 /*! LDOK - Load Enable 2274 * 0b0..Loading updated values is disabled. 2275 * 0b1..Loading updated values is enabled. 2276 */ 2277 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 2278 /*! @} */ 2279 2280 2281 /*! 2282 * @} 2283 */ /* end of group FTM_Register_Masks */ 2284 2285 2286 /* FTM - Peripheral instance base addresses */ 2287 /** Peripheral FTM0 base address */ 2288 #define FTM0_BASE (0x40038000u) 2289 /** Peripheral FTM0 base pointer */ 2290 #define FTM0 ((FTM_Type *)FTM0_BASE) 2291 /** Peripheral FTM1 base address */ 2292 #define FTM1_BASE (0x40039000u) 2293 /** Peripheral FTM1 base pointer */ 2294 #define FTM1 ((FTM_Type *)FTM1_BASE) 2295 /** Peripheral FTM2 base address */ 2296 #define FTM2_BASE (0x4003A000u) 2297 /** Peripheral FTM2 base pointer */ 2298 #define FTM2 ((FTM_Type *)FTM2_BASE) 2299 /** Array initializer of FTM peripheral base addresses */ 2300 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE } 2301 /** Array initializer of FTM peripheral base pointers */ 2302 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2 } 2303 /** Interrupt vectors for the FTM peripheral type */ 2304 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn } 2305 /* Backward compatibility */ 2306 /*! @name SC - Status And Control */ 2307 #define TPM_SC_PS_MASK FTM_SC_PS_MASK 2308 #define TPM_SC_PS_SHIFT FTM_SC_PS_SHIFT 2309 #define TPM_SC_PS(x) FTM_SC_PS(x) 2310 #define TPM_SC_CLKS_MASK FTM_SC_CLKS_MASK 2311 #define TPM_SC_CLKS_SHIFT FTM_SC_CLKS_SHIFT 2312 #define TPM_SC_CLKS(x) FTM_SC_CLKS(x) 2313 #define TPM_SC_CPWMS_MASK FTM_SC_CPWMS_MASK 2314 #define TPM_SC_CPWMS_SHIFT FTM_SC_CPWMS_SHIFT 2315 #define TPM_SC_CPWMS(x) FTM_SC_CPWMS(x) 2316 #define TPM_SC_TOIE_MASK FTM_SC_TOIE_MASK 2317 #define TPM_SC_TOIE_SHIFT FTM_SC_TOIE_SHIFT 2318 #define TPM_SC_TOIE(x) FTM_SC_TOIE(x) 2319 #define TPM_SC_TOF_MASK FTM_SC_TOF_MASK 2320 #define TPM_SC_TOF_SHIFT FTM_SC_TOF_SHIFT 2321 #define TPM_SC_TOF(x) FTM_SC_TOF(x) 2322 /*! @name CNT - Counter */ 2323 #define TPM_CNT_COUNT_MASK FTM_CNT_COUNT_MASK 2324 #define TPM_CNT_COUNT_SHIFT FTM_CNT_COUNT_SHIFT 2325 #define TPM_CNT_COUNT(x) FTM_CNT_COUNT(x) 2326 /*! @name MOD - Modulo */ 2327 #define TPM_MOD_MOD_MASK FTM_MOD_MOD_MASK 2328 #define TPM_MOD_MOD_SHIFT FTM_MOD_MOD_SHIFT 2329 #define TPM_MOD_MOD(x) FTM_MOD_MOD(x) 2330 /*! @name CnSC - Channel (n) Status And Control */ 2331 #define TPM_CnSC_ELSA_MASK FTM_CnSC_ELSA_MASK 2332 #define TPM_CnSC_ELSA_SHIFT FTM_CnSC_ELSA_SHIFT 2333 #define TPM_CnSC_ELSA(x) FTM_CnSC_ELSA(x) 2334 #define TPM_CnSC_ELSB_MASK FTM_CnSC_ELSB_MASK 2335 #define TPM_CnSC_ELSB_SHIFT FTM_CnSC_ELSB_SHIFT 2336 #define TPM_CnSC_ELSB(x) FTM_CnSC_ELSB(x) 2337 #define TPM_CnSC_MSA_MASK FTM_CnSC_MSA_MASK 2338 #define TPM_CnSC_MSA_SHIFT FTM_CnSC_MSA_SHIFT 2339 #define TPM_CnSC_MSA(x) FTM_CnSC_MSA(x) 2340 #define TPM_CnSC_MSB_MASK FTM_CnSC_MSB_MASK 2341 #define TPM_CnSC_MSB_SHIFT FTM_CnSC_MSB_SHIFT 2342 #define TPM_CnSC_MSB(x) FTM_CnSC_MSB(x) 2343 #define TPM_CnSC_CHIE_MASK FTM_CnSC_CHIE_MASK 2344 #define TPM_CnSC_CHIE_SHIFT FTM_CnSC_CHIE_SHIFT 2345 #define TPM_CnSC_CHIE(x) FTM_CnSC_CHIE(x) 2346 #define TPM_CnSC_CHF_MASK FTM_CnSC_CHF_MASK 2347 #define TPM_CnSC_CHF_SHIFT FTM_CnSC_CHF_SHIFT 2348 #define TPM_CnSC_CHF(x) FTM_CnSC_CHF(x) 2349 /* The count of FTM_CnSC */ 2350 #define TPM_CnSC_COUNT (2U) 2351 /*! @name CnV - Channel (n) Value */ 2352 #define TPM_CnV_VAL_MASK FTM_CnV_VAL_MASK 2353 #define TPM_CnV_VAL_SHIFT FTM_CnV_VAL_SHIFT 2354 #define TPM_CnV_VAL(x) FTM_CnV_VAL(x) 2355 /* The count of FTM_CnSC */ 2356 #define TPM_CnV_COUNT (2U) 2357 /** TPM - Register Layout Typedef */ 2358 typedef FTM_Type TPM_Type; 2359 #define TPM0_IRQn FTM0_IRQn 2360 #define TPM0_IRQHandler FTM0_IRQHandler 2361 #define TPM1_IRQn FTM1_IRQn 2362 #define TPM1_IRQHandler FTM1_IRQHandler 2363 #define TPM_CLOCKS FTM_CLOCKS 2364 /* TPM - Peripheral instance base addresses */ 2365 /** Peripheral TPM0 base address */ 2366 #define TPM0_BASE FTM0_BASE 2367 /** Peripheral TPM0 base pointer */ 2368 #define TPM0 ((TPM_Type *)TPM0_BASE) 2369 /** Peripheral TPM1 base address */ 2370 #define TPM1_BASE FTM1_BASE 2371 /** Peripheral TPM1 base pointer */ 2372 #define TPM1 ((TPM_Type *)TPM1_BASE) 2373 /** Array initializer of TPM peripheral base addresses */ 2374 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE } 2375 /** Array initializer of TPM peripheral base pointers */ 2376 #define TPM_BASE_PTRS { TPM0, TPM1 } 2377 /** Interrupt vectors for the TPM peripheral type */ 2378 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn } 2379 2380 2381 /*! 2382 * @} 2383 */ /* end of group FTM_Peripheral_Access_Layer */ 2384 2385 2386 /* ---------------------------------------------------------------------------- 2387 -- FTMRH Peripheral Access Layer 2388 ---------------------------------------------------------------------------- */ 2389 2390 /*! 2391 * @addtogroup FTMRH_Peripheral_Access_Layer FTMRH Peripheral Access Layer 2392 * @{ 2393 */ 2394 2395 /** FTMRH - Register Layout Typedef */ 2396 typedef struct { 2397 __IO uint8_t FCLKDIV; /**< Flash Clock Divider Register, offset: 0x0 */ 2398 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x1 */ 2399 __IO uint8_t FCCOBIX; /**< Flash CCOB Index Register, offset: 0x2 */ 2400 uint8_t RESERVED_0[1]; 2401 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ 2402 __IO uint8_t FERCNFG; /**< Flash Error Configuration Register, offset: 0x5 */ 2403 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x6 */ 2404 __IO uint8_t FERSTAT; /**< Flash Error Status Register, offset: 0x7 */ 2405 __IO uint8_t FPROT; /**< Flash Protection Register, offset: 0x8 */ 2406 __IO uint8_t EEPROT; /**< EEPROM Protection Register, offset: 0x9 */ 2407 __IO uint8_t FCCOBHI; /**< Flash Common Command Object Register:High, offset: 0xA */ 2408 __IO uint8_t FCCOBLO; /**< Flash Common Command Object Register: Low, offset: 0xB */ 2409 __I uint8_t FOPT; /**< Flash Option Register, offset: 0xC */ 2410 } FTMRH_Type; 2411 2412 /* ---------------------------------------------------------------------------- 2413 -- FTMRH Register Masks 2414 ---------------------------------------------------------------------------- */ 2415 2416 /*! 2417 * @addtogroup FTMRH_Register_Masks FTMRH Register Masks 2418 * @{ 2419 */ 2420 2421 /*! @name FCLKDIV - Flash Clock Divider Register */ 2422 /*! @{ */ 2423 #define FTMRH_FCLKDIV_FDIV_MASK (0x3FU) 2424 #define FTMRH_FCLKDIV_FDIV_SHIFT (0U) 2425 #define FTMRH_FCLKDIV_FDIV(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCLKDIV_FDIV_SHIFT)) & FTMRH_FCLKDIV_FDIV_MASK) 2426 #define FTMRH_FCLKDIV_FDIVLCK_MASK (0x40U) 2427 #define FTMRH_FCLKDIV_FDIVLCK_SHIFT (6U) 2428 /*! FDIVLCK - Clock Divider Locked 2429 * 0b0..FDIV field is open for writing. 2430 * 0b1..FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode. 2431 */ 2432 #define FTMRH_FCLKDIV_FDIVLCK(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCLKDIV_FDIVLCK_SHIFT)) & FTMRH_FCLKDIV_FDIVLCK_MASK) 2433 #define FTMRH_FCLKDIV_FDIVLD_MASK (0x80U) 2434 #define FTMRH_FCLKDIV_FDIVLD_SHIFT (7U) 2435 /*! FDIVLD - Clock Divider Loaded 2436 * 0b0..FCLKDIV register has not been written since the last reset. 2437 * 0b1..FCLKDIV register has been written since the last reset. 2438 */ 2439 #define FTMRH_FCLKDIV_FDIVLD(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCLKDIV_FDIVLD_SHIFT)) & FTMRH_FCLKDIV_FDIVLD_MASK) 2440 /*! @} */ 2441 2442 /*! @name FSEC - Flash Security Register */ 2443 /*! @{ */ 2444 #define FTMRH_FSEC_SEC_MASK (0x3U) 2445 #define FTMRH_FSEC_SEC_SHIFT (0U) 2446 /*! SEC - Flash Security Bits 2447 * 0b00..Secured 2448 * 0b01..Secured 2449 * 0b10..Unsecured 2450 * 0b11..Secured 2451 */ 2452 #define FTMRH_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSEC_SEC_SHIFT)) & FTMRH_FSEC_SEC_MASK) 2453 #define FTMRH_FSEC_KEYEN_MASK (0xC0U) 2454 #define FTMRH_FSEC_KEYEN_SHIFT (6U) 2455 /*! KEYEN - Backdoor Key Security Enable Bits 2456 * 0b00..Disabled 2457 * 0b01..Disabled 2458 * 0b10..Enabled 2459 * 0b11..Disabled 2460 */ 2461 #define FTMRH_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSEC_KEYEN_SHIFT)) & FTMRH_FSEC_KEYEN_MASK) 2462 /*! @} */ 2463 2464 /*! @name FCCOBIX - Flash CCOB Index Register */ 2465 /*! @{ */ 2466 #define FTMRH_FCCOBIX_CCOBIX_MASK (0x7U) 2467 #define FTMRH_FCCOBIX_CCOBIX_SHIFT (0U) 2468 #define FTMRH_FCCOBIX_CCOBIX(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCCOBIX_CCOBIX_SHIFT)) & FTMRH_FCCOBIX_CCOBIX_MASK) 2469 /*! @} */ 2470 2471 /*! @name FCNFG - Flash Configuration Register */ 2472 /*! @{ */ 2473 #define FTMRH_FCNFG_FSFD_MASK (0x1U) 2474 #define FTMRH_FCNFG_FSFD_SHIFT (0U) 2475 /*! FSFD - Force Single Bit Fault Detect 2476 * 0b0..Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected. 2477 * 0b1..Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt will be generated as long as FERCNFG[SFDIE] is set. 2478 */ 2479 #define FTMRH_FCNFG_FSFD(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCNFG_FSFD_SHIFT)) & FTMRH_FCNFG_FSFD_MASK) 2480 #define FTMRH_FCNFG_FDFD_MASK (0x2U) 2481 #define FTMRH_FCNFG_FDFD_SHIFT (1U) 2482 /*! FDFD - Force Double Bit Fault Detect 2483 * 0b0..Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected. 2484 * 0b1..Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as FERCNFG[DFDIE] is set. 2485 */ 2486 #define FTMRH_FCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCNFG_FDFD_SHIFT)) & FTMRH_FCNFG_FDFD_MASK) 2487 #define FTMRH_FCNFG_IGNSF_MASK (0x10U) 2488 #define FTMRH_FCNFG_IGNSF_SHIFT (4U) 2489 /*! IGNSF - Ignore Single Bit Fault 2490 * 0b0..All single-bit faults detected during array reads are reported. 2491 * 0b1..Single-bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated. 2492 */ 2493 #define FTMRH_FCNFG_IGNSF(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCNFG_IGNSF_SHIFT)) & FTMRH_FCNFG_IGNSF_MASK) 2494 #define FTMRH_FCNFG_CCIE_MASK (0x80U) 2495 #define FTMRH_FCNFG_CCIE_SHIFT (7U) 2496 /*! CCIE - Command Complete Interrupt Enable 2497 * 0b0..Command complete interrupt is disabled. 2498 * 0b1..An interrupt will be requested whenever the CCIF flag in the FSTAT register is set. 2499 */ 2500 #define FTMRH_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCNFG_CCIE_SHIFT)) & FTMRH_FCNFG_CCIE_MASK) 2501 /*! @} */ 2502 2503 /*! @name FERCNFG - Flash Error Configuration Register */ 2504 /*! @{ */ 2505 #define FTMRH_FERCNFG_SFDIE_MASK (0x1U) 2506 #define FTMRH_FERCNFG_SFDIE_SHIFT (0U) 2507 /*! SFDIE - Single Bit Fault Detect Interrupt Enable 2508 * 0b0..SFDIF interrupt is disabled whenever the SFDIF flag is set. 2509 * 0b1..An interrupt will be requested whenever the SFDIF flag is set. 2510 */ 2511 #define FTMRH_FERCNFG_SFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FERCNFG_SFDIE_SHIFT)) & FTMRH_FERCNFG_SFDIE_MASK) 2512 #define FTMRH_FERCNFG_DFDIE_MASK (0x2U) 2513 #define FTMRH_FERCNFG_DFDIE_SHIFT (1U) 2514 /*! DFDIE - Double Bit Fault Detect Interrupt Enable 2515 * 0b0..DFDIF interrupt is disabled. 2516 * 0b1..An interrupt will be requested whenever the DFDIF flag is set. 2517 */ 2518 #define FTMRH_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FERCNFG_DFDIE_SHIFT)) & FTMRH_FERCNFG_DFDIE_MASK) 2519 /*! @} */ 2520 2521 /*! @name FSTAT - Flash Status Register */ 2522 /*! @{ */ 2523 #define FTMRH_FSTAT_MGSTAT_MASK (0x3U) 2524 #define FTMRH_FSTAT_MGSTAT_SHIFT (0U) 2525 #define FTMRH_FSTAT_MGSTAT(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSTAT_MGSTAT_SHIFT)) & FTMRH_FSTAT_MGSTAT_MASK) 2526 #define FTMRH_FSTAT_MGBUSY_MASK (0x8U) 2527 #define FTMRH_FSTAT_MGBUSY_SHIFT (3U) 2528 /*! MGBUSY - Memory Controller Busy Flag 2529 * 0b0..Memory controller is idle. 2530 * 0b1..Memory controller is busy executing a flash command (CCIF = 0). 2531 */ 2532 #define FTMRH_FSTAT_MGBUSY(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSTAT_MGBUSY_SHIFT)) & FTMRH_FSTAT_MGBUSY_MASK) 2533 #define FTMRH_FSTAT_FPVIOL_MASK (0x10U) 2534 #define FTMRH_FSTAT_FPVIOL_SHIFT (4U) 2535 /*! FPVIOL - Flash Protection Violation Flag 2536 * 0b0..No protection violation is detected. 2537 * 0b1..Protection violation is detected. 2538 */ 2539 #define FTMRH_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSTAT_FPVIOL_SHIFT)) & FTMRH_FSTAT_FPVIOL_MASK) 2540 #define FTMRH_FSTAT_ACCERR_MASK (0x20U) 2541 #define FTMRH_FSTAT_ACCERR_SHIFT (5U) 2542 /*! ACCERR - Flash Access Error Flag 2543 * 0b0..No access error is detected. 2544 * 0b1..Access error is detected. 2545 */ 2546 #define FTMRH_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSTAT_ACCERR_SHIFT)) & FTMRH_FSTAT_ACCERR_MASK) 2547 #define FTMRH_FSTAT_CCIF_MASK (0x80U) 2548 #define FTMRH_FSTAT_CCIF_SHIFT (7U) 2549 /*! CCIF - Command Complete Interrupt Flag 2550 * 0b0..Flash command is in progress. 2551 * 0b1..Flash command has completed. 2552 */ 2553 #define FTMRH_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FSTAT_CCIF_SHIFT)) & FTMRH_FSTAT_CCIF_MASK) 2554 /*! @} */ 2555 2556 /*! @name FERSTAT - Flash Error Status Register */ 2557 /*! @{ */ 2558 #define FTMRH_FERSTAT_SFDIF_MASK (0x1U) 2559 #define FTMRH_FERSTAT_SFDIF_SHIFT (0U) 2560 /*! SFDIF - Single Bit Fault Detect Interrupt Flag 2561 * 0b0..No single bit fault detected. 2562 * 0b1..Single bit fault detected and corrected or a flash array read operation returning invalid data was attempted while command running. 2563 */ 2564 #define FTMRH_FERSTAT_SFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FERSTAT_SFDIF_SHIFT)) & FTMRH_FERSTAT_SFDIF_MASK) 2565 #define FTMRH_FERSTAT_DFDIF_MASK (0x2U) 2566 #define FTMRH_FERSTAT_DFDIF_SHIFT (1U) 2567 /*! DFDIF - Double Bit Fault Detect Interrupt Flag 2568 * 0b0..No double bit fault detected. 2569 * 0b1..Double bit fault detected or a flash array read operation returning invalid data was attempted while command running. 2570 */ 2571 #define FTMRH_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FERSTAT_DFDIF_SHIFT)) & FTMRH_FERSTAT_DFDIF_MASK) 2572 /*! @} */ 2573 2574 /*! @name FPROT - Flash Protection Register */ 2575 /*! @{ */ 2576 #define FTMRH_FPROT_FPLS_MASK (0x3U) 2577 #define FTMRH_FPROT_FPLS_SHIFT (0U) 2578 #define FTMRH_FPROT_FPLS(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FPROT_FPLS_SHIFT)) & FTMRH_FPROT_FPLS_MASK) 2579 #define FTMRH_FPROT_FPLDIS_MASK (0x4U) 2580 #define FTMRH_FPROT_FPLDIS_SHIFT (2U) 2581 /*! FPLDIS - Flash Protection Lower Address Range Disable 2582 * 0b0..Protection/Unprotection enabled. 2583 * 0b1..Protection/Unprotection disabled. 2584 */ 2585 #define FTMRH_FPROT_FPLDIS(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FPROT_FPLDIS_SHIFT)) & FTMRH_FPROT_FPLDIS_MASK) 2586 #define FTMRH_FPROT_FPHS_MASK (0x18U) 2587 #define FTMRH_FPROT_FPHS_SHIFT (3U) 2588 #define FTMRH_FPROT_FPHS(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FPROT_FPHS_SHIFT)) & FTMRH_FPROT_FPHS_MASK) 2589 #define FTMRH_FPROT_FPHDIS_MASK (0x20U) 2590 #define FTMRH_FPROT_FPHDIS_SHIFT (5U) 2591 /*! FPHDIS - Flash Protection Higher Address Range Disable 2592 * 0b0..Protection/Unprotection enabled. 2593 * 0b1..Protection/Unprotection disabled. 2594 */ 2595 #define FTMRH_FPROT_FPHDIS(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FPROT_FPHDIS_SHIFT)) & FTMRH_FPROT_FPHDIS_MASK) 2596 #define FTMRH_FPROT_RNV6_MASK (0x40U) 2597 #define FTMRH_FPROT_RNV6_SHIFT (6U) 2598 #define FTMRH_FPROT_RNV6(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FPROT_RNV6_SHIFT)) & FTMRH_FPROT_RNV6_MASK) 2599 #define FTMRH_FPROT_FPOPEN_MASK (0x80U) 2600 #define FTMRH_FPROT_FPOPEN_SHIFT (7U) 2601 /*! FPOPEN - Flash Protection Operation Enable 2602 * 0b0..When FPOPEN is clear, the FPHDIS and FPLDIS fields define unprotected address ranges as specified by the corresponding FPHS and FPLS fields. 2603 * 0b1..When FPOPEN is set, the FPHDIS and FPLDIS fields enable protection for the address range specified by the corresponding FPHS and FPLS fields. 2604 */ 2605 #define FTMRH_FPROT_FPOPEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FPROT_FPOPEN_SHIFT)) & FTMRH_FPROT_FPOPEN_MASK) 2606 /*! @} */ 2607 2608 /*! @name EEPROT - EEPROM Protection Register */ 2609 /*! @{ */ 2610 #define FTMRH_EEPROT_DPS_MASK (0x7U) 2611 #define FTMRH_EEPROT_DPS_SHIFT (0U) 2612 #define FTMRH_EEPROT_DPS(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_EEPROT_DPS_SHIFT)) & FTMRH_EEPROT_DPS_MASK) 2613 #define FTMRH_EEPROT_DPOPEN_MASK (0x80U) 2614 #define FTMRH_EEPROT_DPOPEN_SHIFT (7U) 2615 /*! DPOPEN - EEPROM Protection Control 2616 * 0b0..Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits. 2617 * 0b1..Disables EEPROM memory protection from program and erase. 2618 */ 2619 #define FTMRH_EEPROT_DPOPEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_EEPROT_DPOPEN_SHIFT)) & FTMRH_EEPROT_DPOPEN_MASK) 2620 /*! @} */ 2621 2622 /*! @name FCCOBHI - Flash Common Command Object Register:High */ 2623 /*! @{ */ 2624 #define FTMRH_FCCOBHI_CCOB_MASK (0xFFU) 2625 #define FTMRH_FCCOBHI_CCOB_SHIFT (0U) 2626 #define FTMRH_FCCOBHI_CCOB(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCCOBHI_CCOB_SHIFT)) & FTMRH_FCCOBHI_CCOB_MASK) 2627 /*! @} */ 2628 2629 /*! @name FCCOBLO - Flash Common Command Object Register: Low */ 2630 /*! @{ */ 2631 #define FTMRH_FCCOBLO_CCOB_MASK (0xFFU) 2632 #define FTMRH_FCCOBLO_CCOB_SHIFT (0U) 2633 #define FTMRH_FCCOBLO_CCOB(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FCCOBLO_CCOB_SHIFT)) & FTMRH_FCCOBLO_CCOB_MASK) 2634 /*! @} */ 2635 2636 /*! @name FOPT - Flash Option Register */ 2637 /*! @{ */ 2638 #define FTMRH_FOPT_NV_MASK (0xFFU) 2639 #define FTMRH_FOPT_NV_SHIFT (0U) 2640 #define FTMRH_FOPT_NV(x) (((uint8_t)(((uint8_t)(x)) << FTMRH_FOPT_NV_SHIFT)) & FTMRH_FOPT_NV_MASK) 2641 /*! @} */ 2642 2643 2644 /*! 2645 * @} 2646 */ /* end of group FTMRH_Register_Masks */ 2647 2648 2649 /* FTMRH - Peripheral instance base addresses */ 2650 /** Peripheral FTMRH base address */ 2651 #define FTMRH_BASE (0x40020000u) 2652 /** Peripheral FTMRH base pointer */ 2653 #define FTMRH ((FTMRH_Type *)FTMRH_BASE) 2654 /** Array initializer of FTMRH peripheral base addresses */ 2655 #define FTMRH_BASE_ADDRS { FTMRH_BASE } 2656 /** Array initializer of FTMRH peripheral base pointers */ 2657 #define FTMRH_BASE_PTRS { FTMRH } 2658 /** Interrupt vectors for the FTMRH peripheral type */ 2659 #define FTMRH_IRQS { FTMRH_IRQn } 2660 2661 /*! 2662 * @} 2663 */ /* end of group FTMRH_Peripheral_Access_Layer */ 2664 2665 2666 /* ---------------------------------------------------------------------------- 2667 -- GPIO Peripheral Access Layer 2668 ---------------------------------------------------------------------------- */ 2669 2670 /*! 2671 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2672 * @{ 2673 */ 2674 2675 /** GPIO - Register Layout Typedef */ 2676 typedef struct { 2677 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 2678 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 2679 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 2680 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 2681 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 2682 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 2683 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 2684 } GPIO_Type; 2685 2686 /* ---------------------------------------------------------------------------- 2687 -- GPIO Register Masks 2688 ---------------------------------------------------------------------------- */ 2689 2690 /*! 2691 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2692 * @{ 2693 */ 2694 2695 /*! @name PDOR - Port Data Output Register */ 2696 /*! @{ */ 2697 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 2698 #define GPIO_PDOR_PDO_SHIFT (0U) 2699 /*! PDO - Port Data Output 2700 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 2701 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 2702 */ 2703 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 2704 /*! @} */ 2705 2706 /*! @name PSOR - Port Set Output Register */ 2707 /*! @{ */ 2708 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 2709 #define GPIO_PSOR_PTSO_SHIFT (0U) 2710 /*! PTSO - Port Set Output 2711 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2712 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 2713 */ 2714 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 2715 /*! @} */ 2716 2717 /*! @name PCOR - Port Clear Output Register */ 2718 /*! @{ */ 2719 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 2720 #define GPIO_PCOR_PTCO_SHIFT (0U) 2721 /*! PTCO - Port Clear Output 2722 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2723 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 2724 */ 2725 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 2726 /*! @} */ 2727 2728 /*! @name PTOR - Port Toggle Output Register */ 2729 /*! @{ */ 2730 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 2731 #define GPIO_PTOR_PTTO_SHIFT (0U) 2732 /*! PTTO - Port Toggle Output 2733 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2734 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 2735 */ 2736 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 2737 /*! @} */ 2738 2739 /*! @name PDIR - Port Data Input Register */ 2740 /*! @{ */ 2741 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 2742 #define GPIO_PDIR_PDI_SHIFT (0U) 2743 /*! PDI - Port Data Input 2744 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 2745 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 2746 */ 2747 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 2748 /*! @} */ 2749 2750 /*! @name PDDR - Port Data Direction Register */ 2751 /*! @{ */ 2752 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 2753 #define GPIO_PDDR_PDD_SHIFT (0U) 2754 /*! PDD - Port Data Direction 2755 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register. 2756 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 2757 */ 2758 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 2759 /*! @} */ 2760 2761 /*! @name PIDR - Port Input Disable Register */ 2762 /*! @{ */ 2763 #define GPIO_PIDR_PID_MASK (0xFFFFFFFFU) 2764 #define GPIO_PIDR_PID_SHIFT (0U) 2765 /*! PID - Port Input Disable 2766 * 0b00000000000000000000000000000000..Pin is configured for General Purpose Input, provided the pin is configured for any digital function. 2767 * 0b00000000000000000000000000000001..Pin is not configured as General Purpose Input.Corresponding Port Data Input Register bit will read zero. 2768 */ 2769 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID_SHIFT)) & GPIO_PIDR_PID_MASK) 2770 /*! @} */ 2771 2772 2773 /*! 2774 * @} 2775 */ /* end of group GPIO_Register_Masks */ 2776 2777 2778 /* GPIO - Peripheral instance base addresses */ 2779 /** Peripheral GPIOA base address */ 2780 #define GPIOA_BASE (0x400FF000u) 2781 /** Peripheral GPIOA base pointer */ 2782 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 2783 /** Peripheral GPIOB base address */ 2784 #define GPIOB_BASE (0x400FF040u) 2785 /** Peripheral GPIOB base pointer */ 2786 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 2787 /** Array initializer of GPIO peripheral base addresses */ 2788 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE } 2789 /** Array initializer of GPIO peripheral base pointers */ 2790 #define GPIO_BASE_PTRS { GPIOA, GPIOB } 2791 2792 /*! 2793 * @} 2794 */ /* end of group GPIO_Peripheral_Access_Layer */ 2795 2796 2797 /* ---------------------------------------------------------------------------- 2798 -- I2C Peripheral Access Layer 2799 ---------------------------------------------------------------------------- */ 2800 2801 /*! 2802 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 2803 * @{ 2804 */ 2805 2806 /** I2C - Register Layout Typedef */ 2807 typedef struct { 2808 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 2809 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 2810 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 2811 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 2812 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 2813 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 2814 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ 2815 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 2816 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 2817 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 2818 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 2819 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 2820 } I2C_Type; 2821 2822 /* ---------------------------------------------------------------------------- 2823 -- I2C Register Masks 2824 ---------------------------------------------------------------------------- */ 2825 2826 /*! 2827 * @addtogroup I2C_Register_Masks I2C Register Masks 2828 * @{ 2829 */ 2830 2831 /*! @name A1 - I2C Address Register 1 */ 2832 /*! @{ */ 2833 #define I2C_A1_AD_MASK (0xFEU) 2834 #define I2C_A1_AD_SHIFT (1U) 2835 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 2836 /*! @} */ 2837 2838 /*! @name F - I2C Frequency Divider register */ 2839 /*! @{ */ 2840 #define I2C_F_ICR_MASK (0x3FU) 2841 #define I2C_F_ICR_SHIFT (0U) 2842 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 2843 #define I2C_F_MULT_MASK (0xC0U) 2844 #define I2C_F_MULT_SHIFT (6U) 2845 /*! MULT - Multiplier Factor 2846 * 0b00..mul = 1 2847 * 0b01..mul = 2 2848 * 0b10..mul = 4 2849 * 0b11..Reserved 2850 */ 2851 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 2852 /*! @} */ 2853 2854 /*! @name C1 - I2C Control Register 1 */ 2855 /*! @{ */ 2856 #define I2C_C1_WUEN_MASK (0x2U) 2857 #define I2C_C1_WUEN_SHIFT (1U) 2858 /*! WUEN - Wakeup Enable 2859 * 0b0..Normal operation. No interrupt generated when address matching in low power mode. 2860 * 0b1..Enables the wakeup function in low power mode. 2861 */ 2862 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 2863 #define I2C_C1_RSTA_MASK (0x4U) 2864 #define I2C_C1_RSTA_SHIFT (2U) 2865 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 2866 #define I2C_C1_TXAK_MASK (0x8U) 2867 #define I2C_C1_TXAK_SHIFT (3U) 2868 /*! TXAK - Transmit Acknowledge Enable 2869 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 2870 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). 2871 */ 2872 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 2873 #define I2C_C1_TX_MASK (0x10U) 2874 #define I2C_C1_TX_SHIFT (4U) 2875 /*! TX - Transmit Mode Select 2876 * 0b0..Receive 2877 * 0b1..Transmit 2878 */ 2879 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 2880 #define I2C_C1_MST_MASK (0x20U) 2881 #define I2C_C1_MST_SHIFT (5U) 2882 /*! MST - Master Mode Select 2883 * 0b0..Slave mode 2884 * 0b1..Master mode 2885 */ 2886 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 2887 #define I2C_C1_IICIE_MASK (0x40U) 2888 #define I2C_C1_IICIE_SHIFT (6U) 2889 /*! IICIE - I2C Interrupt Enable 2890 * 0b0..Disabled 2891 * 0b1..Enabled 2892 */ 2893 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 2894 #define I2C_C1_IICEN_MASK (0x80U) 2895 #define I2C_C1_IICEN_SHIFT (7U) 2896 /*! IICEN - I2C Enable 2897 * 0b0..Disabled 2898 * 0b1..Enabled 2899 */ 2900 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 2901 /*! @} */ 2902 2903 /*! @name S - I2C Status register */ 2904 /*! @{ */ 2905 #define I2C_S_RXAK_MASK (0x1U) 2906 #define I2C_S_RXAK_SHIFT (0U) 2907 /*! RXAK - Receive Acknowledge 2908 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 2909 * 0b1..No acknowledge signal detected 2910 */ 2911 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 2912 #define I2C_S_IICIF_MASK (0x2U) 2913 #define I2C_S_IICIF_SHIFT (1U) 2914 /*! IICIF - Interrupt Flag 2915 * 0b0..No interrupt pending 2916 * 0b1..Interrupt pending 2917 */ 2918 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 2919 #define I2C_S_SRW_MASK (0x4U) 2920 #define I2C_S_SRW_SHIFT (2U) 2921 /*! SRW - Slave Read/Write 2922 * 0b0..Slave receive, master writing to slave 2923 * 0b1..Slave transmit, master reading from slave 2924 */ 2925 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 2926 #define I2C_S_RAM_MASK (0x8U) 2927 #define I2C_S_RAM_SHIFT (3U) 2928 /*! RAM - Range Address Match 2929 * 0b0..Not addressed 2930 * 0b1..Addressed as a slave 2931 */ 2932 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 2933 #define I2C_S_ARBL_MASK (0x10U) 2934 #define I2C_S_ARBL_SHIFT (4U) 2935 /*! ARBL - Arbitration Lost 2936 * 0b0..Standard bus operation. 2937 * 0b1..Loss of arbitration. 2938 */ 2939 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 2940 #define I2C_S_BUSY_MASK (0x20U) 2941 #define I2C_S_BUSY_SHIFT (5U) 2942 /*! BUSY - Bus Busy 2943 * 0b0..Bus is idle 2944 * 0b1..Bus is busy 2945 */ 2946 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 2947 #define I2C_S_IAAS_MASK (0x40U) 2948 #define I2C_S_IAAS_SHIFT (6U) 2949 /*! IAAS - Addressed As A Slave 2950 * 0b0..Not addressed 2951 * 0b1..Addressed as a slave 2952 */ 2953 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 2954 #define I2C_S_TCF_MASK (0x80U) 2955 #define I2C_S_TCF_SHIFT (7U) 2956 /*! TCF - Transfer Complete Flag 2957 * 0b0..Transfer in progress 2958 * 0b1..Transfer complete 2959 */ 2960 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 2961 /*! @} */ 2962 2963 /*! @name D - I2C Data I/O register */ 2964 /*! @{ */ 2965 #define I2C_D_DATA_MASK (0xFFU) 2966 #define I2C_D_DATA_SHIFT (0U) 2967 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 2968 /*! @} */ 2969 2970 /*! @name C2 - I2C Control Register 2 */ 2971 /*! @{ */ 2972 #define I2C_C2_AD_MASK (0x7U) 2973 #define I2C_C2_AD_SHIFT (0U) 2974 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 2975 #define I2C_C2_RMEN_MASK (0x8U) 2976 #define I2C_C2_RMEN_SHIFT (3U) 2977 /*! RMEN - Range Address Matching Enable 2978 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 2979 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. 2980 */ 2981 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 2982 #define I2C_C2_SBRC_MASK (0x10U) 2983 #define I2C_C2_SBRC_SHIFT (4U) 2984 /*! SBRC - Slave Baud Rate Control 2985 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 2986 * 0b1..Slave baud rate is independent of the master baud rate 2987 */ 2988 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 2989 #define I2C_C2_ADEXT_MASK (0x40U) 2990 #define I2C_C2_ADEXT_SHIFT (6U) 2991 /*! ADEXT - Address Extension 2992 * 0b0..7-bit address scheme 2993 * 0b1..10-bit address scheme 2994 */ 2995 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 2996 #define I2C_C2_GCAEN_MASK (0x80U) 2997 #define I2C_C2_GCAEN_SHIFT (7U) 2998 /*! GCAEN - General Call Address Enable 2999 * 0b0..Disabled 3000 * 0b1..Enabled 3001 */ 3002 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 3003 /*! @} */ 3004 3005 /*! @name FLT - I2C Programmable Input Glitch Filter Register */ 3006 /*! @{ */ 3007 #define I2C_FLT_FLT_MASK (0xFU) 3008 #define I2C_FLT_FLT_SHIFT (0U) 3009 /*! FLT - I2C Programmable Filter Factor 3010 * 0b0000..No filter/bypass 3011 */ 3012 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 3013 #define I2C_FLT_STARTF_MASK (0x10U) 3014 #define I2C_FLT_STARTF_SHIFT (4U) 3015 /*! STARTF - I2C Bus Start Detect Flag 3016 * 0b0..No start happens on I2C bus 3017 * 0b1..Start detected on I2C bus 3018 */ 3019 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 3020 #define I2C_FLT_SSIE_MASK (0x20U) 3021 #define I2C_FLT_SSIE_SHIFT (5U) 3022 /*! SSIE - I2C Bus Stop or Start Interrupt Enable 3023 * 0b0..Stop or start detection interrupt is disabled 3024 * 0b1..Stop or start detection interrupt is enabled 3025 */ 3026 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 3027 #define I2C_FLT_STOPF_MASK (0x40U) 3028 #define I2C_FLT_STOPF_SHIFT (6U) 3029 /*! STOPF - I2C Bus Stop Detect Flag 3030 * 0b0..No stop happens on I2C bus 3031 * 0b1..Stop detected on I2C bus 3032 */ 3033 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 3034 #define I2C_FLT_SHEN_MASK (0x80U) 3035 #define I2C_FLT_SHEN_SHIFT (7U) 3036 /*! SHEN - Stop Hold Enable 3037 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 3038 * 0b1..Stop holdoff is enabled. 3039 */ 3040 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 3041 /*! @} */ 3042 3043 /*! @name RA - I2C Range Address register */ 3044 /*! @{ */ 3045 #define I2C_RA_RAD_MASK (0xFEU) 3046 #define I2C_RA_RAD_SHIFT (1U) 3047 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 3048 /*! @} */ 3049 3050 /*! @name SMB - I2C SMBus Control and Status register */ 3051 /*! @{ */ 3052 #define I2C_SMB_SHTF2IE_MASK (0x1U) 3053 #define I2C_SMB_SHTF2IE_SHIFT (0U) 3054 /*! SHTF2IE - SHTF2 Interrupt Enable 3055 * 0b0..SHTF2 interrupt is disabled 3056 * 0b1..SHTF2 interrupt is enabled 3057 */ 3058 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 3059 #define I2C_SMB_SHTF2_MASK (0x2U) 3060 #define I2C_SMB_SHTF2_SHIFT (1U) 3061 /*! SHTF2 - SCL High Timeout Flag 2 3062 * 0b0..No SCL high and SDA low timeout occurs 3063 * 0b1..SCL high and SDA low timeout occurs 3064 */ 3065 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 3066 #define I2C_SMB_SHTF1_MASK (0x4U) 3067 #define I2C_SMB_SHTF1_SHIFT (2U) 3068 /*! SHTF1 - SCL High Timeout Flag 1 3069 * 0b0..No SCL high and SDA high timeout occurs 3070 * 0b1..SCL high and SDA high timeout occurs 3071 */ 3072 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 3073 #define I2C_SMB_SLTF_MASK (0x8U) 3074 #define I2C_SMB_SLTF_SHIFT (3U) 3075 /*! SLTF - SCL Low Timeout Flag 3076 * 0b0..No low timeout occurs 3077 * 0b1..Low timeout occurs 3078 */ 3079 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 3080 #define I2C_SMB_TCKSEL_MASK (0x10U) 3081 #define I2C_SMB_TCKSEL_SHIFT (4U) 3082 /*! TCKSEL - Timeout Counter Clock Select 3083 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 3084 * 0b1..Timeout counter counts at the frequency of the I2C module clock 3085 */ 3086 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 3087 #define I2C_SMB_SIICAEN_MASK (0x20U) 3088 #define I2C_SMB_SIICAEN_SHIFT (5U) 3089 /*! SIICAEN - Second I2C Address Enable 3090 * 0b0..I2C address register 2 matching is disabled 3091 * 0b1..I2C address register 2 matching is enabled 3092 */ 3093 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 3094 #define I2C_SMB_ALERTEN_MASK (0x40U) 3095 #define I2C_SMB_ALERTEN_SHIFT (6U) 3096 /*! ALERTEN - SMBus Alert Response Address Enable 3097 * 0b0..SMBus alert response address matching is disabled 3098 * 0b1..SMBus alert response address matching is enabled 3099 */ 3100 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 3101 #define I2C_SMB_FACK_MASK (0x80U) 3102 #define I2C_SMB_FACK_SHIFT (7U) 3103 /*! FACK - Fast NACK/ACK Enable 3104 * 0b0..An ACK or NACK is sent on the following receiving data byte 3105 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. 3106 */ 3107 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 3108 /*! @} */ 3109 3110 /*! @name A2 - I2C Address Register 2 */ 3111 /*! @{ */ 3112 #define I2C_A2_SAD_MASK (0xFEU) 3113 #define I2C_A2_SAD_SHIFT (1U) 3114 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 3115 /*! @} */ 3116 3117 /*! @name SLTH - I2C SCL Low Timeout Register High */ 3118 /*! @{ */ 3119 #define I2C_SLTH_SSLT_MASK (0xFFU) 3120 #define I2C_SLTH_SSLT_SHIFT (0U) 3121 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 3122 /*! @} */ 3123 3124 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 3125 /*! @{ */ 3126 #define I2C_SLTL_SSLT_MASK (0xFFU) 3127 #define I2C_SLTL_SSLT_SHIFT (0U) 3128 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 3129 /*! @} */ 3130 3131 3132 /*! 3133 * @} 3134 */ /* end of group I2C_Register_Masks */ 3135 3136 3137 /* I2C - Peripheral instance base addresses */ 3138 /** Peripheral I2C0 base address */ 3139 #define I2C0_BASE (0x40066000u) 3140 /** Peripheral I2C0 base pointer */ 3141 #define I2C0 ((I2C_Type *)I2C0_BASE) 3142 /** Array initializer of I2C peripheral base addresses */ 3143 #define I2C_BASE_ADDRS { I2C0_BASE } 3144 /** Array initializer of I2C peripheral base pointers */ 3145 #define I2C_BASE_PTRS { I2C0 } 3146 /** Interrupt vectors for the I2C peripheral type */ 3147 #define I2C_IRQS { I2C0_IRQn } 3148 3149 /*! 3150 * @} 3151 */ /* end of group I2C_Peripheral_Access_Layer */ 3152 3153 3154 /* ---------------------------------------------------------------------------- 3155 -- ICS Peripheral Access Layer 3156 ---------------------------------------------------------------------------- */ 3157 3158 /*! 3159 * @addtogroup ICS_Peripheral_Access_Layer ICS Peripheral Access Layer 3160 * @{ 3161 */ 3162 3163 /** ICS - Register Layout Typedef */ 3164 typedef struct { 3165 __IO uint8_t C1; /**< ICS Control Register 1, offset: 0x0 */ 3166 __IO uint8_t C2; /**< ICS Control Register 2, offset: 0x1 */ 3167 __IO uint8_t C3; /**< ICS Control Register 3, offset: 0x2 */ 3168 __IO uint8_t C4; /**< ICS Control Register 4, offset: 0x3 */ 3169 __IO uint8_t S; /**< ICS Status Register, offset: 0x4 */ 3170 } ICS_Type; 3171 3172 /* ---------------------------------------------------------------------------- 3173 -- ICS Register Masks 3174 ---------------------------------------------------------------------------- */ 3175 3176 /*! 3177 * @addtogroup ICS_Register_Masks ICS Register Masks 3178 * @{ 3179 */ 3180 3181 /*! @name C1 - ICS Control Register 1 */ 3182 /*! @{ */ 3183 #define ICS_C1_IREFSTEN_MASK (0x1U) 3184 #define ICS_C1_IREFSTEN_SHIFT (0U) 3185 /*! IREFSTEN - Internal Reference Stop Enable 3186 * 0b0..Internal reference clock is disabled in Stop mode. 3187 * 0b1..Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop. 3188 */ 3189 #define ICS_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IREFSTEN_SHIFT)) & ICS_C1_IREFSTEN_MASK) 3190 #define ICS_C1_IRCLKEN_MASK (0x2U) 3191 #define ICS_C1_IRCLKEN_SHIFT (1U) 3192 /*! IRCLKEN - Internal Reference Clock Enable 3193 * 0b0..ICSIRCLK is inactive. 3194 * 0b1..ICSIRCLK is active. 3195 */ 3196 #define ICS_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IRCLKEN_SHIFT)) & ICS_C1_IRCLKEN_MASK) 3197 #define ICS_C1_IREFS_MASK (0x4U) 3198 #define ICS_C1_IREFS_SHIFT (2U) 3199 /*! IREFS - Internal Reference Select 3200 * 0b0..External reference clock is selected. 3201 * 0b1..Internal reference clock is selected. 3202 */ 3203 #define ICS_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IREFS_SHIFT)) & ICS_C1_IREFS_MASK) 3204 #define ICS_C1_RDIV_MASK (0x38U) 3205 #define ICS_C1_RDIV_SHIFT (3U) 3206 #define ICS_C1_RDIV(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_RDIV_SHIFT)) & ICS_C1_RDIV_MASK) 3207 #define ICS_C1_CLKS_MASK (0xC0U) 3208 #define ICS_C1_CLKS_SHIFT (6U) 3209 /*! CLKS - Clock Source Select 3210 * 0b00..Output of FLL is selected. 3211 * 0b01..Internal reference clock is selected. 3212 * 0b10..External reference clock is selected. 3213 * 0b11..Reserved, defaults to 00. 3214 */ 3215 #define ICS_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_CLKS_SHIFT)) & ICS_C1_CLKS_MASK) 3216 /*! @} */ 3217 3218 /*! @name C2 - ICS Control Register 2 */ 3219 /*! @{ */ 3220 #define ICS_C2_LP_MASK (0x10U) 3221 #define ICS_C2_LP_SHIFT (4U) 3222 /*! LP - Low Power Select 3223 * 0b0..FLL is not disabled in bypass mode. 3224 * 0b1..FLL is disabled in bypass modes unless debug is active. 3225 */ 3226 #define ICS_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << ICS_C2_LP_SHIFT)) & ICS_C2_LP_MASK) 3227 #define ICS_C2_BDIV_MASK (0xE0U) 3228 #define ICS_C2_BDIV_SHIFT (5U) 3229 /*! BDIV - Bus Frequency Divider 3230 * 0b000..Encoding 0-Divides the selected clock by 1. 3231 * 0b001..Encoding 1-Divides the selected clock by 2 (reset default). 3232 * 0b010..Encoding 2-Divides the selected clock by 4. 3233 * 0b011..Encoding 3-Divides the selected clock by 8. 3234 * 0b100..Encoding 4-Divides the selected clock by 16. 3235 * 0b101..Encoding 5-Divides the selected clock by 32. 3236 * 0b110..Encoding 6-Divides the selected clock by 64. 3237 * 0b111..Encoding 7-Divides the selected clock by 128. 3238 */ 3239 #define ICS_C2_BDIV(x) (((uint8_t)(((uint8_t)(x)) << ICS_C2_BDIV_SHIFT)) & ICS_C2_BDIV_MASK) 3240 /*! @} */ 3241 3242 /*! @name C3 - ICS Control Register 3 */ 3243 /*! @{ */ 3244 #define ICS_C3_SCTRIM_MASK (0xFFU) 3245 #define ICS_C3_SCTRIM_SHIFT (0U) 3246 #define ICS_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << ICS_C3_SCTRIM_SHIFT)) & ICS_C3_SCTRIM_MASK) 3247 /*! @} */ 3248 3249 /*! @name C4 - ICS Control Register 4 */ 3250 /*! @{ */ 3251 #define ICS_C4_SCFTRIM_MASK (0x1U) 3252 #define ICS_C4_SCFTRIM_SHIFT (0U) 3253 #define ICS_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_SCFTRIM_SHIFT)) & ICS_C4_SCFTRIM_MASK) 3254 #define ICS_C4_CME_MASK (0x20U) 3255 #define ICS_C4_CME_SHIFT (5U) 3256 /*! CME - Clock Monitor Enable 3257 * 0b0..Clock monitor is disabled. 3258 * 0b1..Generates a reset request on loss of external clock. 3259 */ 3260 #define ICS_C4_CME(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_CME_SHIFT)) & ICS_C4_CME_MASK) 3261 #define ICS_C4_LOLIE_MASK (0x80U) 3262 #define ICS_C4_LOLIE_SHIFT (7U) 3263 /*! LOLIE - Loss of Lock Interrupt 3264 * 0b0..No request on loss of lock. 3265 * 0b1..Generates an interrupt request on loss of lock. 3266 */ 3267 #define ICS_C4_LOLIE(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_LOLIE_SHIFT)) & ICS_C4_LOLIE_MASK) 3268 /*! @} */ 3269 3270 /*! @name S - ICS Status Register */ 3271 /*! @{ */ 3272 #define ICS_S_CLKST_MASK (0xCU) 3273 #define ICS_S_CLKST_SHIFT (2U) 3274 /*! CLKST - Clock Mode Status 3275 * 0b00..Output of FLL is selected. 3276 * 0b01..FLL Bypassed, internal reference clock is selected. 3277 * 0b10..FLL Bypassed, external reference clock is selected. 3278 * 0b11..Reserved. 3279 */ 3280 #define ICS_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_CLKST_SHIFT)) & ICS_S_CLKST_MASK) 3281 #define ICS_S_IREFST_MASK (0x10U) 3282 #define ICS_S_IREFST_SHIFT (4U) 3283 /*! IREFST - Internal Reference Status 3284 * 0b0..Source of reference clock is external clock. 3285 * 0b1..Source of reference clock is internal clock. 3286 */ 3287 #define ICS_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_IREFST_SHIFT)) & ICS_S_IREFST_MASK) 3288 #define ICS_S_LOCK_MASK (0x40U) 3289 #define ICS_S_LOCK_SHIFT (6U) 3290 /*! LOCK - Lock Status 3291 * 0b0..FLL is currently unlocked. 3292 * 0b1..FLL is currently locked. 3293 */ 3294 #define ICS_S_LOCK(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_LOCK_SHIFT)) & ICS_S_LOCK_MASK) 3295 #define ICS_S_LOLS_MASK (0x80U) 3296 #define ICS_S_LOLS_SHIFT (7U) 3297 /*! LOLS - Loss of Lock Status 3298 * 0b0..FLL has not lost lock since LOLS was last cleared. 3299 * 0b1..FLL has lost lock since LOLS was last cleared. 3300 */ 3301 #define ICS_S_LOLS(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_LOLS_SHIFT)) & ICS_S_LOLS_MASK) 3302 /*! @} */ 3303 3304 3305 /*! 3306 * @} 3307 */ /* end of group ICS_Register_Masks */ 3308 3309 3310 /* ICS - Peripheral instance base addresses */ 3311 /** Peripheral ICS base address */ 3312 #define ICS_BASE (0x40064000u) 3313 /** Peripheral ICS base pointer */ 3314 #define ICS ((ICS_Type *)ICS_BASE) 3315 /** Array initializer of ICS peripheral base addresses */ 3316 #define ICS_BASE_ADDRS { ICS_BASE } 3317 /** Array initializer of ICS peripheral base pointers */ 3318 #define ICS_BASE_PTRS { ICS } 3319 /** Interrupt vectors for the ICS peripheral type */ 3320 #define ICS_IRQS { ICS_IRQn } 3321 3322 /*! 3323 * @} 3324 */ /* end of group ICS_Peripheral_Access_Layer */ 3325 3326 3327 /* ---------------------------------------------------------------------------- 3328 -- IRQ Peripheral Access Layer 3329 ---------------------------------------------------------------------------- */ 3330 3331 /*! 3332 * @addtogroup IRQ_Peripheral_Access_Layer IRQ Peripheral Access Layer 3333 * @{ 3334 */ 3335 3336 /** IRQ - Register Layout Typedef */ 3337 typedef struct { 3338 __IO uint8_t SC; /**< Interrupt Pin Request Status and Control Register, offset: 0x0 */ 3339 } IRQ_Type; 3340 3341 /* ---------------------------------------------------------------------------- 3342 -- IRQ Register Masks 3343 ---------------------------------------------------------------------------- */ 3344 3345 /*! 3346 * @addtogroup IRQ_Register_Masks IRQ Register Masks 3347 * @{ 3348 */ 3349 3350 /*! @name SC - Interrupt Pin Request Status and Control Register */ 3351 /*! @{ */ 3352 #define IRQ_SC_IRQMOD_MASK (0x1U) 3353 #define IRQ_SC_IRQMOD_SHIFT (0U) 3354 /*! IRQMOD - IRQ Detection Mode 3355 * 0b0..IRQ event is detected only on falling/rising edges. 3356 * 0b1..IRQ event is detected on falling/rising edges and low/high levels. 3357 */ 3358 #define IRQ_SC_IRQMOD(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQMOD_SHIFT)) & IRQ_SC_IRQMOD_MASK) 3359 #define IRQ_SC_IRQIE_MASK (0x2U) 3360 #define IRQ_SC_IRQIE_SHIFT (1U) 3361 /*! IRQIE - IRQ Interrupt Enable 3362 * 0b0..Interrupt request when IRQF set is disabled (use polling). 3363 * 0b1..Interrupt requested whenever IRQF = 1. 3364 */ 3365 #define IRQ_SC_IRQIE(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQIE_SHIFT)) & IRQ_SC_IRQIE_MASK) 3366 #define IRQ_SC_IRQACK_MASK (0x4U) 3367 #define IRQ_SC_IRQACK_SHIFT (2U) 3368 #define IRQ_SC_IRQACK(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQACK_SHIFT)) & IRQ_SC_IRQACK_MASK) 3369 #define IRQ_SC_IRQF_MASK (0x8U) 3370 #define IRQ_SC_IRQF_SHIFT (3U) 3371 /*! IRQF - IRQ Flag 3372 * 0b0..No IRQ request 3373 * 0b1..IRQ event is detected. 3374 */ 3375 #define IRQ_SC_IRQF(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQF_SHIFT)) & IRQ_SC_IRQF_MASK) 3376 #define IRQ_SC_IRQPE_MASK (0x10U) 3377 #define IRQ_SC_IRQPE_SHIFT (4U) 3378 /*! IRQPE - IRQ Pin Enable 3379 * 0b0..IRQ pin function is disabled. 3380 * 0b1..IRQ pin function is enabled. 3381 */ 3382 #define IRQ_SC_IRQPE(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQPE_SHIFT)) & IRQ_SC_IRQPE_MASK) 3383 #define IRQ_SC_IRQEDG_MASK (0x20U) 3384 #define IRQ_SC_IRQEDG_SHIFT (5U) 3385 /*! IRQEDG - Interrupt Request (IRQ) Edge Select 3386 * 0b0..IRQ is falling-edge or falling-edge/low-level sensitive. 3387 * 0b1..IRQ is rising-edge or rising-edge/high-level sensitive. 3388 */ 3389 #define IRQ_SC_IRQEDG(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQEDG_SHIFT)) & IRQ_SC_IRQEDG_MASK) 3390 #define IRQ_SC_IRQPDD_MASK (0x40U) 3391 #define IRQ_SC_IRQPDD_SHIFT (6U) 3392 /*! IRQPDD - Interrupt Request (IRQ) Pull Device Disable 3393 * 0b0..IRQ pull device enabled if IRQPE = 1. 3394 * 0b1..IRQ pull device disabled if IRQPE = 1. 3395 */ 3396 #define IRQ_SC_IRQPDD(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQPDD_SHIFT)) & IRQ_SC_IRQPDD_MASK) 3397 /*! @} */ 3398 3399 3400 /*! 3401 * @} 3402 */ /* end of group IRQ_Register_Masks */ 3403 3404 3405 /* IRQ - Peripheral instance base addresses */ 3406 /** Peripheral IRQ base address */ 3407 #define IRQ_BASE (0x40031000u) 3408 /** Peripheral IRQ base pointer */ 3409 #define IRQ ((IRQ_Type *)IRQ_BASE) 3410 /** Array initializer of IRQ peripheral base addresses */ 3411 #define IRQ_BASE_ADDRS { IRQ_BASE } 3412 /** Array initializer of IRQ peripheral base pointers */ 3413 #define IRQ_BASE_PTRS { IRQ } 3414 3415 /*! 3416 * @} 3417 */ /* end of group IRQ_Peripheral_Access_Layer */ 3418 3419 3420 /* ---------------------------------------------------------------------------- 3421 -- KBI Peripheral Access Layer 3422 ---------------------------------------------------------------------------- */ 3423 3424 /*! 3425 * @addtogroup KBI_Peripheral_Access_Layer KBI Peripheral Access Layer 3426 * @{ 3427 */ 3428 3429 /** KBI - Register Layout Typedef */ 3430 typedef struct { 3431 __IO uint8_t SC; /**< KBI Status and Control Register, offset: 0x0 */ 3432 __IO uint8_t PE; /**< KBI Pin Enable Register, offset: 0x1 */ 3433 __IO uint8_t ES; /**< KBI Edge Select Register, offset: 0x2 */ 3434 } KBI_Type; 3435 3436 /* ---------------------------------------------------------------------------- 3437 -- KBI Register Masks 3438 ---------------------------------------------------------------------------- */ 3439 3440 /*! 3441 * @addtogroup KBI_Register_Masks KBI Register Masks 3442 * @{ 3443 */ 3444 3445 /*! @name SC - KBI Status and Control Register */ 3446 /*! @{ */ 3447 #define KBI_SC_KBMOD_MASK (0x1U) 3448 #define KBI_SC_KBMOD_SHIFT (0U) 3449 /*! KBMOD - KBI Detection Mode 3450 * 0b0..Keyboard detects edges only. 3451 * 0b1..Keyboard detects both edges and levels. 3452 */ 3453 #define KBI_SC_KBMOD(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBMOD_SHIFT)) & KBI_SC_KBMOD_MASK) 3454 #define KBI_SC_KBIE_MASK (0x2U) 3455 #define KBI_SC_KBIE_SHIFT (1U) 3456 /*! KBIE - KBI Interrupt Enable 3457 * 0b0..KBI interrupt not enabled. 3458 * 0b1..KBI interrupt enabled. 3459 */ 3460 #define KBI_SC_KBIE(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBIE_SHIFT)) & KBI_SC_KBIE_MASK) 3461 #define KBI_SC_KBACK_MASK (0x4U) 3462 #define KBI_SC_KBACK_SHIFT (2U) 3463 #define KBI_SC_KBACK(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBACK_SHIFT)) & KBI_SC_KBACK_MASK) 3464 #define KBI_SC_KBF_MASK (0x8U) 3465 #define KBI_SC_KBF_SHIFT (3U) 3466 /*! KBF - KBI Interrupt Flag 3467 * 0b0..KBI interrupt request not detected. 3468 * 0b1..KBI interrupt request detected. 3469 */ 3470 #define KBI_SC_KBF(x) (((uint8_t)(((uint8_t)(x)) << KBI_SC_KBF_SHIFT)) & KBI_SC_KBF_MASK) 3471 /*! @} */ 3472 3473 /*! @name PE - KBI Pin Enable Register */ 3474 /*! @{ */ 3475 #define KBI_PE_KBIPE_MASK (0xFFU) 3476 #define KBI_PE_KBIPE_SHIFT (0U) 3477 /*! KBIPE - KBI Pin Enables 3478 * 0b00000000..Pin is not enabled as KBI interrupt. 3479 * 0b00000001..Pin is enabled as KBI interrupt. 3480 */ 3481 #define KBI_PE_KBIPE(x) (((uint8_t)(((uint8_t)(x)) << KBI_PE_KBIPE_SHIFT)) & KBI_PE_KBIPE_MASK) 3482 /*! @} */ 3483 3484 /*! @name ES - KBI Edge Select Register */ 3485 /*! @{ */ 3486 #define KBI_ES_KBEDG_MASK (0xFFU) 3487 #define KBI_ES_KBEDG_SHIFT (0U) 3488 /*! KBEDG - KBI Edge Selects 3489 * 0b00000000..Falling edge/low level. 3490 * 0b00000001..Rising edge/high level. 3491 */ 3492 #define KBI_ES_KBEDG(x) (((uint8_t)(((uint8_t)(x)) << KBI_ES_KBEDG_SHIFT)) & KBI_ES_KBEDG_MASK) 3493 /*! @} */ 3494 3495 3496 /*! 3497 * @} 3498 */ /* end of group KBI_Register_Masks */ 3499 3500 3501 /* KBI - Peripheral instance base addresses */ 3502 /** Peripheral KBI0 base address */ 3503 #define KBI0_BASE (0x40079000u) 3504 /** Peripheral KBI0 base pointer */ 3505 #define KBI0 ((KBI_Type *)KBI0_BASE) 3506 /** Peripheral KBI1 base address */ 3507 #define KBI1_BASE (0x4007A000u) 3508 /** Peripheral KBI1 base pointer */ 3509 #define KBI1 ((KBI_Type *)KBI1_BASE) 3510 /** Array initializer of KBI peripheral base addresses */ 3511 #define KBI_BASE_ADDRS { KBI0_BASE, KBI1_BASE } 3512 /** Array initializer of KBI peripheral base pointers */ 3513 #define KBI_BASE_PTRS { KBI0, KBI1 } 3514 /** Interrupt vectors for the KBI peripheral type */ 3515 #define KBI_IRQS { KBI0_IRQn, KBI1_IRQn } 3516 3517 /*! 3518 * @} 3519 */ /* end of group KBI_Peripheral_Access_Layer */ 3520 3521 3522 /* ---------------------------------------------------------------------------- 3523 -- MCM Peripheral Access Layer 3524 ---------------------------------------------------------------------------- */ 3525 3526 /*! 3527 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 3528 * @{ 3529 */ 3530 3531 /** MCM - Register Layout Typedef */ 3532 typedef struct { 3533 uint8_t RESERVED_0[8]; 3534 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 3535 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 3536 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 3537 } MCM_Type; 3538 3539 /* ---------------------------------------------------------------------------- 3540 -- MCM Register Masks 3541 ---------------------------------------------------------------------------- */ 3542 3543 /*! 3544 * @addtogroup MCM_Register_Masks MCM Register Masks 3545 * @{ 3546 */ 3547 3548 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 3549 /*! @{ */ 3550 #define MCM_PLASC_ASC_MASK (0xFFU) 3551 #define MCM_PLASC_ASC_SHIFT (0U) 3552 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 3553 * 0b00000000..A bus slave connection to AXBS input port n is absent. 3554 * 0b00000001..A bus slave connection to AXBS input port n is present. 3555 */ 3556 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 3557 /*! @} */ 3558 3559 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 3560 /*! @{ */ 3561 #define MCM_PLAMC_AMC_MASK (0xFFU) 3562 #define MCM_PLAMC_AMC_SHIFT (0U) 3563 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 3564 * 0b00000000..A bus master connection to AXBS input port n is absent 3565 * 0b00000001..A bus master connection to AXBS input port n is present 3566 */ 3567 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 3568 /*! @} */ 3569 3570 /*! @name PLACR - Platform Control Register */ 3571 /*! @{ */ 3572 #define MCM_PLACR_CFCC_MASK (0x400U) 3573 #define MCM_PLACR_CFCC_SHIFT (10U) 3574 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 3575 #define MCM_PLACR_DFCDA_MASK (0x800U) 3576 #define MCM_PLACR_DFCDA_SHIFT (11U) 3577 /*! DFCDA - Disable Flash Controller Data Caching 3578 * 0b0..Enable flash controller data caching 3579 * 0b1..Disable flash controller data caching. 3580 */ 3581 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 3582 #define MCM_PLACR_DFCIC_MASK (0x1000U) 3583 #define MCM_PLACR_DFCIC_SHIFT (12U) 3584 /*! DFCIC - Disable Flash Controller Instruction Caching 3585 * 0b0..Enable flash controller instruction caching. 3586 * 0b1..Disable flash controller instruction caching. 3587 */ 3588 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 3589 #define MCM_PLACR_DFCC_MASK (0x2000U) 3590 #define MCM_PLACR_DFCC_SHIFT (13U) 3591 /*! DFCC - Disable Flash Controller Cache 3592 * 0b0..Enable flash controller cache. 3593 * 0b1..Disable flash controller cache. 3594 */ 3595 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 3596 #define MCM_PLACR_EFDS_MASK (0x4000U) 3597 #define MCM_PLACR_EFDS_SHIFT (14U) 3598 /*! EFDS - Enable Flash Data Speculation 3599 * 0b0..Disable flash data speculation. 3600 * 0b1..Enable flash data speculation. 3601 */ 3602 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 3603 #define MCM_PLACR_DFCS_MASK (0x8000U) 3604 #define MCM_PLACR_DFCS_SHIFT (15U) 3605 /*! DFCS - Disable Flash Controller Speculation 3606 * 0b0..Enable flash controller speculation. 3607 * 0b1..Disable flash controller speculation. 3608 */ 3609 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 3610 #define MCM_PLACR_ESFC_MASK (0x10000U) 3611 #define MCM_PLACR_ESFC_SHIFT (16U) 3612 /*! ESFC - Enable Stalling Flash Controller 3613 * 0b0..Disable stalling flash controller when flash is busy. 3614 * 0b1..Enable stalling flash controller when flash is busy. 3615 */ 3616 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 3617 /*! @} */ 3618 3619 3620 /*! 3621 * @} 3622 */ /* end of group MCM_Register_Masks */ 3623 3624 3625 /* MCM - Peripheral instance base addresses */ 3626 /** Peripheral MCM base address */ 3627 #define MCM_BASE (0xF0003000u) 3628 /** Peripheral MCM base pointer */ 3629 #define MCM ((MCM_Type *)MCM_BASE) 3630 /** Array initializer of MCM peripheral base addresses */ 3631 #define MCM_BASE_ADDRS { MCM_BASE } 3632 /** Array initializer of MCM peripheral base pointers */ 3633 #define MCM_BASE_PTRS { MCM } 3634 3635 /*! 3636 * @} 3637 */ /* end of group MCM_Peripheral_Access_Layer */ 3638 3639 3640 /* ---------------------------------------------------------------------------- 3641 -- OSC Peripheral Access Layer 3642 ---------------------------------------------------------------------------- */ 3643 3644 /*! 3645 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 3646 * @{ 3647 */ 3648 3649 /** OSC - Register Layout Typedef */ 3650 typedef struct { 3651 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 3652 } OSC_Type; 3653 3654 /* ---------------------------------------------------------------------------- 3655 -- OSC Register Masks 3656 ---------------------------------------------------------------------------- */ 3657 3658 /*! 3659 * @addtogroup OSC_Register_Masks OSC Register Masks 3660 * @{ 3661 */ 3662 3663 /*! @name CR - OSC Control Register */ 3664 /*! @{ */ 3665 #define OSC_CR_OSCINIT_MASK (0x1U) 3666 #define OSC_CR_OSCINIT_SHIFT (0U) 3667 /*! OSCINIT - OSC Initialization 3668 * 0b0..Oscillator initialization is not complete. 3669 * 0b1..Oscillator initialization is completed. 3670 */ 3671 #define OSC_CR_OSCINIT(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCINIT_SHIFT)) & OSC_CR_OSCINIT_MASK) 3672 #define OSC_CR_HGO_MASK (0x2U) 3673 #define OSC_CR_HGO_SHIFT (1U) 3674 /*! HGO - High Gain Oscillator Select 3675 * 0b0..Low-power mode 3676 * 0b1..High-gain mode 3677 */ 3678 #define OSC_CR_HGO(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_HGO_SHIFT)) & OSC_CR_HGO_MASK) 3679 #define OSC_CR_RANGE_MASK (0x4U) 3680 #define OSC_CR_RANGE_SHIFT (2U) 3681 /*! RANGE - Frequency Range Select 3682 * 0b0..Low frequency range of 32 kHz. 3683 * 0b1..High frequency range of 4-20 MHz. 3684 */ 3685 #define OSC_CR_RANGE(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_RANGE_SHIFT)) & OSC_CR_RANGE_MASK) 3686 #define OSC_CR_OSCOS_MASK (0x10U) 3687 #define OSC_CR_OSCOS_SHIFT (4U) 3688 /*! OSCOS - OSC Output Select 3689 * 0b0..External clock source from EXTAL pin is selected. 3690 * 0b1..Oscillator clock source is selected. 3691 */ 3692 #define OSC_CR_OSCOS(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCOS_SHIFT)) & OSC_CR_OSCOS_MASK) 3693 #define OSC_CR_OSCSTEN_MASK (0x20U) 3694 #define OSC_CR_OSCSTEN_SHIFT (5U) 3695 /*! OSCSTEN - OSC Enable in Stop mode 3696 * 0b0..OSC clock is disabled in Stop mode. 3697 * 0b1..OSC clock stays enabled in Stop mode. 3698 */ 3699 #define OSC_CR_OSCSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCSTEN_SHIFT)) & OSC_CR_OSCSTEN_MASK) 3700 #define OSC_CR_OSCEN_MASK (0x80U) 3701 #define OSC_CR_OSCEN_SHIFT (7U) 3702 /*! OSCEN - OSC Enable 3703 * 0b0..OSC module is disabled. 3704 * 0b1..OSC module is enabled. 3705 */ 3706 #define OSC_CR_OSCEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCEN_SHIFT)) & OSC_CR_OSCEN_MASK) 3707 /*! @} */ 3708 3709 3710 /*! 3711 * @} 3712 */ /* end of group OSC_Register_Masks */ 3713 3714 3715 /* OSC - Peripheral instance base addresses */ 3716 /** Peripheral OSC base address */ 3717 #define OSC_BASE (0x40065000u) 3718 /** Peripheral OSC base pointer */ 3719 #define OSC ((OSC_Type *)OSC_BASE) 3720 /** Array initializer of OSC peripheral base addresses */ 3721 #define OSC_BASE_ADDRS { OSC_BASE } 3722 /** Array initializer of OSC peripheral base pointers */ 3723 #define OSC_BASE_PTRS { OSC } 3724 3725 /*! 3726 * @} 3727 */ /* end of group OSC_Peripheral_Access_Layer */ 3728 3729 3730 /* ---------------------------------------------------------------------------- 3731 -- PIT Peripheral Access Layer 3732 ---------------------------------------------------------------------------- */ 3733 3734 /*! 3735 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 3736 * @{ 3737 */ 3738 3739 /** PIT - Register Layout Typedef */ 3740 typedef struct { 3741 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 3742 uint8_t RESERVED_0[252]; 3743 struct { /* offset: 0x100, array step: 0x10 */ 3744 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 3745 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 3746 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 3747 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 3748 } CHANNEL[2]; 3749 } PIT_Type; 3750 3751 /* ---------------------------------------------------------------------------- 3752 -- PIT Register Masks 3753 ---------------------------------------------------------------------------- */ 3754 3755 /*! 3756 * @addtogroup PIT_Register_Masks PIT Register Masks 3757 * @{ 3758 */ 3759 3760 /*! @name MCR - PIT Module Control Register */ 3761 /*! @{ */ 3762 #define PIT_MCR_FRZ_MASK (0x1U) 3763 #define PIT_MCR_FRZ_SHIFT (0U) 3764 /*! FRZ - Freeze 3765 * 0b0..Timers continue to run in Debug mode. 3766 * 0b1..Timers are stopped in Debug mode. 3767 */ 3768 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 3769 #define PIT_MCR_MDIS_MASK (0x2U) 3770 #define PIT_MCR_MDIS_SHIFT (1U) 3771 /*! MDIS - Module Disable - (PIT section) 3772 * 0b0..Clock for standard PIT timers is enabled. 3773 * 0b1..Clock for standard PIT timers is disabled. 3774 */ 3775 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 3776 /*! @} */ 3777 3778 /*! @name LDVAL - Timer Load Value Register */ 3779 /*! @{ */ 3780 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 3781 #define PIT_LDVAL_TSV_SHIFT (0U) 3782 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 3783 /*! @} */ 3784 3785 /* The count of PIT_LDVAL */ 3786 #define PIT_LDVAL_COUNT (2U) 3787 3788 /*! @name CVAL - Current Timer Value Register */ 3789 /*! @{ */ 3790 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 3791 #define PIT_CVAL_TVL_SHIFT (0U) 3792 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 3793 /*! @} */ 3794 3795 /* The count of PIT_CVAL */ 3796 #define PIT_CVAL_COUNT (2U) 3797 3798 /*! @name TCTRL - Timer Control Register */ 3799 /*! @{ */ 3800 #define PIT_TCTRL_TEN_MASK (0x1U) 3801 #define PIT_TCTRL_TEN_SHIFT (0U) 3802 /*! TEN - Timer Enable 3803 * 0b0..Timer n is disabled. 3804 * 0b1..Timer n is enabled. 3805 */ 3806 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 3807 #define PIT_TCTRL_TIE_MASK (0x2U) 3808 #define PIT_TCTRL_TIE_SHIFT (1U) 3809 /*! TIE - Timer Interrupt Enable 3810 * 0b0..Interrupt requests from Timer n are disabled. 3811 * 0b1..Interrupt will be requested whenever TIF is set. 3812 */ 3813 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 3814 #define PIT_TCTRL_CHN_MASK (0x4U) 3815 #define PIT_TCTRL_CHN_SHIFT (2U) 3816 /*! CHN - Chain Mode 3817 * 0b0..Timer is not chained. 3818 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. 3819 */ 3820 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 3821 /*! @} */ 3822 3823 /* The count of PIT_TCTRL */ 3824 #define PIT_TCTRL_COUNT (2U) 3825 3826 /*! @name TFLG - Timer Flag Register */ 3827 /*! @{ */ 3828 #define PIT_TFLG_TIF_MASK (0x1U) 3829 #define PIT_TFLG_TIF_SHIFT (0U) 3830 /*! TIF - Timer Interrupt Flag 3831 * 0b0..Timeout has not yet occurred. 3832 * 0b1..Timeout has occurred. 3833 */ 3834 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 3835 /*! @} */ 3836 3837 /* The count of PIT_TFLG */ 3838 #define PIT_TFLG_COUNT (2U) 3839 3840 3841 /*! 3842 * @} 3843 */ /* end of group PIT_Register_Masks */ 3844 3845 3846 /* PIT - Peripheral instance base addresses */ 3847 /** Peripheral PIT base address */ 3848 #define PIT_BASE (0x40037000u) 3849 /** Peripheral PIT base pointer */ 3850 #define PIT ((PIT_Type *)PIT_BASE) 3851 /** Array initializer of PIT peripheral base addresses */ 3852 #define PIT_BASE_ADDRS { PIT_BASE } 3853 /** Array initializer of PIT peripheral base pointers */ 3854 #define PIT_BASE_PTRS { PIT } 3855 /** Interrupt vectors for the PIT peripheral type */ 3856 #define PIT_IRQS { { PIT_CH0_IRQn, PIT_CH1_IRQn } } 3857 3858 /*! 3859 * @} 3860 */ /* end of group PIT_Peripheral_Access_Layer */ 3861 3862 3863 /* ---------------------------------------------------------------------------- 3864 -- PMC Peripheral Access Layer 3865 ---------------------------------------------------------------------------- */ 3866 3867 /*! 3868 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 3869 * @{ 3870 */ 3871 3872 /** PMC - Register Layout Typedef */ 3873 typedef struct { 3874 __IO uint8_t SPMSC1; /**< System Power Management Status and Control 1 Register, offset: 0x0 */ 3875 __IO uint8_t SPMSC2; /**< System Power Management Status and Control 2 Register, offset: 0x1 */ 3876 } PMC_Type; 3877 3878 /* ---------------------------------------------------------------------------- 3879 -- PMC Register Masks 3880 ---------------------------------------------------------------------------- */ 3881 3882 /*! 3883 * @addtogroup PMC_Register_Masks PMC Register Masks 3884 * @{ 3885 */ 3886 3887 /*! @name SPMSC1 - System Power Management Status and Control 1 Register */ 3888 /*! @{ */ 3889 #define PMC_SPMSC1_BGBE_MASK (0x1U) 3890 #define PMC_SPMSC1_BGBE_SHIFT (0U) 3891 /*! BGBE - Bandgap Buffer Enable 3892 * 0b0..Bandgap buffer is disabled. 3893 * 0b1..Bandgap buffer is enabled. 3894 */ 3895 #define PMC_SPMSC1_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_BGBE_SHIFT)) & PMC_SPMSC1_BGBE_MASK) 3896 #define PMC_SPMSC1_LVDE_MASK (0x4U) 3897 #define PMC_SPMSC1_LVDE_SHIFT (2U) 3898 /*! LVDE - Low-Voltage Detect Enable 3899 * 0b0..LVD logic is disabled. 3900 * 0b1..LVD logic is enabled. 3901 */ 3902 #define PMC_SPMSC1_LVDE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDE_SHIFT)) & PMC_SPMSC1_LVDE_MASK) 3903 #define PMC_SPMSC1_LVDSE_MASK (0x8U) 3904 #define PMC_SPMSC1_LVDSE_SHIFT (3U) 3905 /*! LVDSE - Low-Voltage Detect Stop Enable 3906 * 0b0..Low-voltage detect is disabled during Stop mode. 3907 * 0b1..Low-voltage detect is enabled during Stop mode. 3908 */ 3909 #define PMC_SPMSC1_LVDSE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDSE_SHIFT)) & PMC_SPMSC1_LVDSE_MASK) 3910 #define PMC_SPMSC1_LVDRE_MASK (0x10U) 3911 #define PMC_SPMSC1_LVDRE_SHIFT (4U) 3912 /*! LVDRE - Low-Voltage Detect Reset Enable 3913 * 0b0..LVD events do not generate hardware resets. 3914 * 0b1..Forces an MCU reset when an enabled low-voltage detect event occurs. 3915 */ 3916 #define PMC_SPMSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDRE_SHIFT)) & PMC_SPMSC1_LVDRE_MASK) 3917 #define PMC_SPMSC1_LVWIE_MASK (0x20U) 3918 #define PMC_SPMSC1_LVWIE_SHIFT (5U) 3919 /*! LVWIE - Low-Voltage Warning Interrupt Enable 3920 * 0b0..Hardware interrupt is disabled (use polling). 3921 * 0b1..Requests a hardware interrupt when LVWF = 1. 3922 */ 3923 #define PMC_SPMSC1_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWIE_SHIFT)) & PMC_SPMSC1_LVWIE_MASK) 3924 #define PMC_SPMSC1_LVWACK_MASK (0x40U) 3925 #define PMC_SPMSC1_LVWACK_SHIFT (6U) 3926 #define PMC_SPMSC1_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWACK_SHIFT)) & PMC_SPMSC1_LVWACK_MASK) 3927 #define PMC_SPMSC1_LVWF_MASK (0x80U) 3928 #define PMC_SPMSC1_LVWF_SHIFT (7U) 3929 /*! LVWF - Low-Voltage Warning Flag 3930 * 0b0..Low-voltage warning is not present. 3931 * 0b1..Low-voltage warning is present or was present. 3932 */ 3933 #define PMC_SPMSC1_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWF_SHIFT)) & PMC_SPMSC1_LVWF_MASK) 3934 /*! @} */ 3935 3936 /*! @name SPMSC2 - System Power Management Status and Control 2 Register */ 3937 /*! @{ */ 3938 #define PMC_SPMSC2_LVWV_MASK (0x30U) 3939 #define PMC_SPMSC2_LVWV_SHIFT (4U) 3940 /*! LVWV - Low-Voltage Warning Voltage Select 3941 * 0b00..Low trip point is selected (VLVW = VLVW1). 3942 * 0b01..Middle 1 trip point is selected (VLVW = VLVW2). 3943 * 0b10..Middle 2 trip point is selected (VLVW = VLVW3). 3944 * 0b11..High trip point is selected (VLVW = VLVW4). 3945 */ 3946 #define PMC_SPMSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC2_LVWV_SHIFT)) & PMC_SPMSC2_LVWV_MASK) 3947 #define PMC_SPMSC2_LVDV_MASK (0x40U) 3948 #define PMC_SPMSC2_LVDV_SHIFT (6U) 3949 /*! LVDV - Low-Voltage Detect Voltage Select 3950 * 0b0..Low trip point is selected (VLVD = VLVDL). 3951 * 0b1..High trip point is selected (VLVD = VLVDH). 3952 */ 3953 #define PMC_SPMSC2_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC2_LVDV_SHIFT)) & PMC_SPMSC2_LVDV_MASK) 3954 /*! @} */ 3955 3956 3957 /*! 3958 * @} 3959 */ /* end of group PMC_Register_Masks */ 3960 3961 3962 /* PMC - Peripheral instance base addresses */ 3963 /** Peripheral PMC base address */ 3964 #define PMC_BASE (0x4007D000u) 3965 /** Peripheral PMC base pointer */ 3966 #define PMC ((PMC_Type *)PMC_BASE) 3967 /** Array initializer of PMC peripheral base addresses */ 3968 #define PMC_BASE_ADDRS { PMC_BASE } 3969 /** Array initializer of PMC peripheral base pointers */ 3970 #define PMC_BASE_PTRS { PMC } 3971 /** Interrupt vectors for the PMC peripheral type */ 3972 #define PMC_IRQS { PMC_IRQn } 3973 3974 /*! 3975 * @} 3976 */ /* end of group PMC_Peripheral_Access_Layer */ 3977 3978 3979 /* ---------------------------------------------------------------------------- 3980 -- PORT Peripheral Access Layer 3981 ---------------------------------------------------------------------------- */ 3982 3983 /*! 3984 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 3985 * @{ 3986 */ 3987 3988 /** PORT - Register Layout Typedef */ 3989 typedef struct { 3990 __IO uint32_t IOFLT; /**< Port Filter Register, offset: 0x0 */ 3991 __IO uint32_t PUEL; /**< Port Pullup Enable Low Register, offset: 0x4 */ 3992 __IO uint32_t PUEH; /**< Port Pullup Enable High Register, offset: 0x8 */ 3993 __IO uint32_t HDRVE; /**< Port High Drive Enable Register, offset: 0xC */ 3994 } PORT_Type; 3995 3996 /* ---------------------------------------------------------------------------- 3997 -- PORT Register Masks 3998 ---------------------------------------------------------------------------- */ 3999 4000 /*! 4001 * @addtogroup PORT_Register_Masks PORT Register Masks 4002 * @{ 4003 */ 4004 4005 /*! @name IOFLT - Port Filter Register */ 4006 /*! @{ */ 4007 #define PORT_IOFLT_FLTA_MASK (0x3U) 4008 #define PORT_IOFLT_FLTA_SHIFT (0U) 4009 /*! FLTA - Filter Selection for Input from PTA 4010 * 0b00..BUSCLK 4011 * 0b01..FLTDIV1 4012 * 0b10..FLTDIV2 4013 * 0b11..FLTDIV3 4014 */ 4015 #define PORT_IOFLT_FLTA(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTA_SHIFT)) & PORT_IOFLT_FLTA_MASK) 4016 #define PORT_IOFLT_FLTB_MASK (0xCU) 4017 #define PORT_IOFLT_FLTB_SHIFT (2U) 4018 /*! FLTB - Filter Selection for Input from PTB 4019 * 0b00..BUSCLK 4020 * 0b01..FLTDIV1 4021 * 0b10..FLTDIV2 4022 * 0b11..FLTDIV3 4023 */ 4024 #define PORT_IOFLT_FLTB(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTB_SHIFT)) & PORT_IOFLT_FLTB_MASK) 4025 #define PORT_IOFLT_FLTC_MASK (0x30U) 4026 #define PORT_IOFLT_FLTC_SHIFT (4U) 4027 /*! FLTC - Filter Selection for Input from PTC 4028 * 0b00..BUSCLK 4029 * 0b01..FLTDIV1 4030 * 0b10..FLTDIV2 4031 * 0b11..FLTDIV3 4032 */ 4033 #define PORT_IOFLT_FLTC(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTC_SHIFT)) & PORT_IOFLT_FLTC_MASK) 4034 #define PORT_IOFLT_FLTD_MASK (0xC0U) 4035 #define PORT_IOFLT_FLTD_SHIFT (6U) 4036 /*! FLTD - Filter Selection for Input from PTD 4037 * 0b00..BUSCLK 4038 * 0b01..FLTDIV1 4039 * 0b10..FLTDIV2 4040 * 0b11..FLTDIV3 4041 */ 4042 #define PORT_IOFLT_FLTD(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTD_SHIFT)) & PORT_IOFLT_FLTD_MASK) 4043 #define PORT_IOFLT_FLTE_MASK (0x300U) 4044 #define PORT_IOFLT_FLTE_SHIFT (8U) 4045 /*! FLTE - Filter Selection for Input from PTD 4046 * 0b00..BUSCLK 4047 * 0b01..FLTDIV1 4048 * 0b10..FLTDIV2 4049 * 0b11..FLTDIV3 4050 */ 4051 #define PORT_IOFLT_FLTE(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTE_SHIFT)) & PORT_IOFLT_FLTE_MASK) 4052 #define PORT_IOFLT_FLTF_MASK (0xC00U) 4053 #define PORT_IOFLT_FLTF_SHIFT (10U) 4054 /*! FLTF - Filter Selection for Input from PTF 4055 * 0b00..BUSCLK 4056 * 0b01..FLTDIV1 4057 * 0b10..FLTDIV2 4058 * 0b11..FLTDIV3 4059 */ 4060 #define PORT_IOFLT_FLTF(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTF_SHIFT)) & PORT_IOFLT_FLTF_MASK) 4061 #define PORT_IOFLT_FLTG_MASK (0x3000U) 4062 #define PORT_IOFLT_FLTG_SHIFT (12U) 4063 /*! FLTG - Filter Selection for Input from PTG 4064 * 0b00..BUSCLK 4065 * 0b01..FLTDIV1 4066 * 0b10..FLTDIV2 4067 * 0b11..FLTDIV3 4068 */ 4069 #define PORT_IOFLT_FLTG(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTG_SHIFT)) & PORT_IOFLT_FLTG_MASK) 4070 #define PORT_IOFLT_FLTH_MASK (0xC000U) 4071 #define PORT_IOFLT_FLTH_SHIFT (14U) 4072 /*! FLTH - Filter Selection for Input from PTH 4073 * 0b00..BUSCLK 4074 * 0b01..FLTDIV1 4075 * 0b10..FLTDIV2 4076 * 0b11..FLTDIV3 4077 */ 4078 #define PORT_IOFLT_FLTH(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTH_SHIFT)) & PORT_IOFLT_FLTH_MASK) 4079 #define PORT_IOFLT_FLTRST_MASK (0x30000U) 4080 #define PORT_IOFLT_FLTRST_SHIFT (16U) 4081 /*! FLTRST - Filter Selection for Input from RESET/IRQ 4082 * 0b00..No filter. 4083 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4084 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4085 * 0b11..FLTDIV3 4086 */ 4087 #define PORT_IOFLT_FLTRST(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTRST_SHIFT)) & PORT_IOFLT_FLTRST_MASK) 4088 #define PORT_IOFLT_FLTKBI0_MASK (0xC0000U) 4089 #define PORT_IOFLT_FLTKBI0_SHIFT (18U) 4090 /*! FLTKBI0 - Filter selection for Input from KBI0 4091 * 0b00..No filter. 4092 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4093 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4094 * 0b11..FLTDIV3 4095 */ 4096 #define PORT_IOFLT_FLTKBI0(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTKBI0_SHIFT)) & PORT_IOFLT_FLTKBI0_MASK) 4097 #define PORT_IOFLT_FLTKBI1_MASK (0x300000U) 4098 #define PORT_IOFLT_FLTKBI1_SHIFT (20U) 4099 /*! FLTKBI1 - Filter Selection for Input from KBI1 4100 * 0b00..No filter 4101 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4102 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4103 * 0b11..FLTDIV3 4104 */ 4105 #define PORT_IOFLT_FLTKBI1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTKBI1_SHIFT)) & PORT_IOFLT_FLTKBI1_MASK) 4106 #define PORT_IOFLT_FLTNMI_MASK (0xC00000U) 4107 #define PORT_IOFLT_FLTNMI_SHIFT (22U) 4108 /*! FLTNMI - Filter Selection for Input from NMI 4109 * 0b00..No filter. 4110 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4111 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4112 * 0b11..FLTDIV3 4113 */ 4114 #define PORT_IOFLT_FLTNMI(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTNMI_SHIFT)) & PORT_IOFLT_FLTNMI_MASK) 4115 #define PORT_IOFLT_FLTDIV1_MASK (0x3000000U) 4116 #define PORT_IOFLT_FLTDIV1_SHIFT (24U) 4117 /*! FLTDIV1 - Filter Division Set 1 4118 * 0b00..BUSCLK/2 4119 * 0b01..BUSCLK/4 4120 * 0b10..BUSCLK/8 4121 * 0b11..BUSCLK/16 4122 */ 4123 #define PORT_IOFLT_FLTDIV1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTDIV1_SHIFT)) & PORT_IOFLT_FLTDIV1_MASK) 4124 #define PORT_IOFLT_FLTDIV2_MASK (0x1C000000U) 4125 #define PORT_IOFLT_FLTDIV2_SHIFT (26U) 4126 /*! FLTDIV2 - Filter Division Set 2 4127 * 0b000..BUSCLK/32 4128 * 0b001..BUSCLK/64 4129 * 0b010..BUSCLK/128 4130 * 0b011..BUSCLK/256 4131 * 0b100..BUSCLK/512 4132 * 0b101..BUSCLK/1024 4133 * 0b110..BUSCLK/2048 4134 * 0b111..BUSCLK/4096 4135 */ 4136 #define PORT_IOFLT_FLTDIV2(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTDIV2_SHIFT)) & PORT_IOFLT_FLTDIV2_MASK) 4137 #define PORT_IOFLT_FLTDIV3_MASK (0xE0000000U) 4138 #define PORT_IOFLT_FLTDIV3_SHIFT (29U) 4139 /*! FLTDIV3 - Filter Division Set 3 4140 * 0b000..LPOCLK 4141 * 0b001..LPOCLK/2 4142 * 0b010..LPOCLK/4 4143 * 0b011..LPOCLK/8 4144 * 0b100..LPOCLK/16 4145 * 0b101..LPOCLK/32 4146 * 0b110..LPOCLK/64 4147 * 0b111..LPOCLK/128 4148 */ 4149 #define PORT_IOFLT_FLTDIV3(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT_FLTDIV3_SHIFT)) & PORT_IOFLT_FLTDIV3_MASK) 4150 /*! @} */ 4151 4152 /*! @name PUEL - Port Pullup Enable Low Register */ 4153 /*! @{ */ 4154 #define PORT_PUEL_PTAPE0_MASK (0x1U) 4155 #define PORT_PUEL_PTAPE0_SHIFT (0U) 4156 /*! PTAPE0 - Pull Enable for Port A Bit 0 4157 * 0b0..Pullup is disabled for port A bit 0. 4158 * 0b1..Pullup is enabled for port A bit 0. 4159 */ 4160 #define PORT_PUEL_PTAPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE0_SHIFT)) & PORT_PUEL_PTAPE0_MASK) 4161 #define PORT_PUEL_PTAPE1_MASK (0x2U) 4162 #define PORT_PUEL_PTAPE1_SHIFT (1U) 4163 /*! PTAPE1 - Pull Enable for Port A Bit 1 4164 * 0b0..Pullup is disabled for port A bit 1. 4165 * 0b1..Pullup is enabled for port A bit 1. 4166 */ 4167 #define PORT_PUEL_PTAPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE1_SHIFT)) & PORT_PUEL_PTAPE1_MASK) 4168 #define PORT_PUEL_PTAPE2_MASK (0x4U) 4169 #define PORT_PUEL_PTAPE2_SHIFT (2U) 4170 /*! PTAPE2 - Pull Enable for Port A Bit 2 4171 * 0b0..Pullup is disabled for port A bit 2. 4172 * 0b1..Pullup is enabled for port A bit 2. 4173 */ 4174 #define PORT_PUEL_PTAPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE2_SHIFT)) & PORT_PUEL_PTAPE2_MASK) 4175 #define PORT_PUEL_PTAPE3_MASK (0x8U) 4176 #define PORT_PUEL_PTAPE3_SHIFT (3U) 4177 /*! PTAPE3 - Pull Enable for Port A Bit 3 4178 * 0b0..Pullup is disabled for port A bit 3. 4179 * 0b1..Pullup is enabled for port A bit 3. 4180 */ 4181 #define PORT_PUEL_PTAPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE3_SHIFT)) & PORT_PUEL_PTAPE3_MASK) 4182 #define PORT_PUEL_PTAPE4_MASK (0x10U) 4183 #define PORT_PUEL_PTAPE4_SHIFT (4U) 4184 /*! PTAPE4 - Pull Enable for Port A Bit 4 4185 * 0b0..Pullup is disabled for port A bit 4. 4186 * 0b1..Pullup is enabled for port A bit 4. 4187 */ 4188 #define PORT_PUEL_PTAPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE4_SHIFT)) & PORT_PUEL_PTAPE4_MASK) 4189 #define PORT_PUEL_PTAPE5_MASK (0x20U) 4190 #define PORT_PUEL_PTAPE5_SHIFT (5U) 4191 /*! PTAPE5 - Pull Enable for Port A Bit 5 4192 * 0b0..Pullup is disabled for port A bit 5. 4193 * 0b1..Pullup is enabled for port A bit 5. 4194 */ 4195 #define PORT_PUEL_PTAPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE5_SHIFT)) & PORT_PUEL_PTAPE5_MASK) 4196 #define PORT_PUEL_PTAPE6_MASK (0x40U) 4197 #define PORT_PUEL_PTAPE6_SHIFT (6U) 4198 /*! PTAPE6 - Pull Enable for Port A Bit 6 4199 * 0b0..Pullup is disabled for port A bit 6. 4200 * 0b1..Pullup is enabled for port A bit 6. 4201 */ 4202 #define PORT_PUEL_PTAPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE6_SHIFT)) & PORT_PUEL_PTAPE6_MASK) 4203 #define PORT_PUEL_PTAPE7_MASK (0x80U) 4204 #define PORT_PUEL_PTAPE7_SHIFT (7U) 4205 /*! PTAPE7 - Pull Enable for Port A Bit 7 4206 * 0b0..Pullup is disabled for port A bit 7. 4207 * 0b1..Pullup is enabled for port A bit 7. 4208 */ 4209 #define PORT_PUEL_PTAPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTAPE7_SHIFT)) & PORT_PUEL_PTAPE7_MASK) 4210 #define PORT_PUEL_PTBPE0_MASK (0x100U) 4211 #define PORT_PUEL_PTBPE0_SHIFT (8U) 4212 /*! PTBPE0 - Pull Enable for Port B Bit 0 4213 * 0b0..Pullup is disabled for port B bit 0. 4214 * 0b1..Pullup is enabled for port B bit 0. 4215 */ 4216 #define PORT_PUEL_PTBPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE0_SHIFT)) & PORT_PUEL_PTBPE0_MASK) 4217 #define PORT_PUEL_PTBPE1_MASK (0x200U) 4218 #define PORT_PUEL_PTBPE1_SHIFT (9U) 4219 /*! PTBPE1 - Pull Enable for Port B Bit 1 4220 * 0b0..Pullup is disabled for port B bit 1. 4221 * 0b1..Pullup is enabled for port B bit 1. 4222 */ 4223 #define PORT_PUEL_PTBPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE1_SHIFT)) & PORT_PUEL_PTBPE1_MASK) 4224 #define PORT_PUEL_PTBPE2_MASK (0x400U) 4225 #define PORT_PUEL_PTBPE2_SHIFT (10U) 4226 /*! PTBPE2 - Pull Enable for Port B Bit 2 4227 * 0b0..Pullup is disabled for port B bit 2. 4228 * 0b1..Pullup is enabled for port B bit 2. 4229 */ 4230 #define PORT_PUEL_PTBPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE2_SHIFT)) & PORT_PUEL_PTBPE2_MASK) 4231 #define PORT_PUEL_PTBPE3_MASK (0x800U) 4232 #define PORT_PUEL_PTBPE3_SHIFT (11U) 4233 /*! PTBPE3 - Pull Enable for Port B Bit 3 4234 * 0b0..Pullup is disabled for port B bit 3. 4235 * 0b1..Pullup is enabled for port B bit 3. 4236 */ 4237 #define PORT_PUEL_PTBPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE3_SHIFT)) & PORT_PUEL_PTBPE3_MASK) 4238 #define PORT_PUEL_PTBPE4_MASK (0x1000U) 4239 #define PORT_PUEL_PTBPE4_SHIFT (12U) 4240 /*! PTBPE4 - Pull Enable for Port B Bit 4 4241 * 0b0..Pullup is disabled for port B bit 4. 4242 * 0b1..Pullup is enabled for port B bit 4. 4243 */ 4244 #define PORT_PUEL_PTBPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE4_SHIFT)) & PORT_PUEL_PTBPE4_MASK) 4245 #define PORT_PUEL_PTBPE5_MASK (0x2000U) 4246 #define PORT_PUEL_PTBPE5_SHIFT (13U) 4247 /*! PTBPE5 - Pull Enable for Port B Bit 5 4248 * 0b0..Pullup is disabled for port B bit 5. 4249 * 0b1..Pullup is enabled for port B bit 5. 4250 */ 4251 #define PORT_PUEL_PTBPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE5_SHIFT)) & PORT_PUEL_PTBPE5_MASK) 4252 #define PORT_PUEL_PTBPE6_MASK (0x4000U) 4253 #define PORT_PUEL_PTBPE6_SHIFT (14U) 4254 /*! PTBPE6 - Pull Enable for Port B Bit 6 4255 * 0b0..Pullup is disabled for port B bit 6. 4256 * 0b1..Pullup is enabled for port B bit 6. 4257 */ 4258 #define PORT_PUEL_PTBPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE6_SHIFT)) & PORT_PUEL_PTBPE6_MASK) 4259 #define PORT_PUEL_PTBPE7_MASK (0x8000U) 4260 #define PORT_PUEL_PTBPE7_SHIFT (15U) 4261 /*! PTBPE7 - Pull Enable for Port B Bit 7 4262 * 0b0..Pullup is disabled for port B bit 7. 4263 * 0b1..Pullup is enabled for port B bit 7. 4264 */ 4265 #define PORT_PUEL_PTBPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTBPE7_SHIFT)) & PORT_PUEL_PTBPE7_MASK) 4266 #define PORT_PUEL_PTCPE0_MASK (0x10000U) 4267 #define PORT_PUEL_PTCPE0_SHIFT (16U) 4268 /*! PTCPE0 - Pull Enable for Port C Bit 0 4269 * 0b0..Pullup is disabled for port C bit 0. 4270 * 0b1..Pullup is enabled for port C bit 0. 4271 */ 4272 #define PORT_PUEL_PTCPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE0_SHIFT)) & PORT_PUEL_PTCPE0_MASK) 4273 #define PORT_PUEL_PTCPE1_MASK (0x20000U) 4274 #define PORT_PUEL_PTCPE1_SHIFT (17U) 4275 /*! PTCPE1 - Pull Enable for Port C Bit 1 4276 * 0b0..Pullup is disabled for port C bit 1. 4277 * 0b1..Pullup is enabled for port C bit 1. 4278 */ 4279 #define PORT_PUEL_PTCPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE1_SHIFT)) & PORT_PUEL_PTCPE1_MASK) 4280 #define PORT_PUEL_PTCPE2_MASK (0x40000U) 4281 #define PORT_PUEL_PTCPE2_SHIFT (18U) 4282 /*! PTCPE2 - Pull Enable for Port C Bit 2 4283 * 0b0..Pullup is disabled for port C bit 2. 4284 * 0b1..Pullup is enabled for port C bit 2. 4285 */ 4286 #define PORT_PUEL_PTCPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE2_SHIFT)) & PORT_PUEL_PTCPE2_MASK) 4287 #define PORT_PUEL_PTCPE3_MASK (0x80000U) 4288 #define PORT_PUEL_PTCPE3_SHIFT (19U) 4289 /*! PTCPE3 - Pull Enable for Port C Bit 3 4290 * 0b0..Pullup is disabled for port C bit 3. 4291 * 0b1..Pullup is enabled for port C bit 3. 4292 */ 4293 #define PORT_PUEL_PTCPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE3_SHIFT)) & PORT_PUEL_PTCPE3_MASK) 4294 #define PORT_PUEL_PTCPE4_MASK (0x100000U) 4295 #define PORT_PUEL_PTCPE4_SHIFT (20U) 4296 /*! PTCPE4 - Pull Enable for Port C Bit 4 4297 * 0b0..Pullup is disabled for port C bit 4. 4298 * 0b1..Pullup is enabled for port C bit 4. 4299 */ 4300 #define PORT_PUEL_PTCPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE4_SHIFT)) & PORT_PUEL_PTCPE4_MASK) 4301 #define PORT_PUEL_PTCPE5_MASK (0x200000U) 4302 #define PORT_PUEL_PTCPE5_SHIFT (21U) 4303 /*! PTCPE5 - Pull Enable for Port C Bit 5 4304 * 0b0..Pullup is disabled for port C bit 5. 4305 * 0b1..Pullup is enabled for port C bit 5. 4306 */ 4307 #define PORT_PUEL_PTCPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE5_SHIFT)) & PORT_PUEL_PTCPE5_MASK) 4308 #define PORT_PUEL_PTCPE6_MASK (0x400000U) 4309 #define PORT_PUEL_PTCPE6_SHIFT (22U) 4310 /*! PTCPE6 - Pull Enable for Port C Bit 6 4311 * 0b0..Pullup is disabled for port C bit 6. 4312 * 0b1..Pullup is enabled for port C bit 6. 4313 */ 4314 #define PORT_PUEL_PTCPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE6_SHIFT)) & PORT_PUEL_PTCPE6_MASK) 4315 #define PORT_PUEL_PTCPE7_MASK (0x800000U) 4316 #define PORT_PUEL_PTCPE7_SHIFT (23U) 4317 /*! PTCPE7 - Pull Enable for Port C Bit 7 4318 * 0b0..Pullup is disabled for port C bit 7. 4319 * 0b1..Pullup is enabled for port C bit 7. 4320 */ 4321 #define PORT_PUEL_PTCPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTCPE7_SHIFT)) & PORT_PUEL_PTCPE7_MASK) 4322 #define PORT_PUEL_PTDPE0_MASK (0x1000000U) 4323 #define PORT_PUEL_PTDPE0_SHIFT (24U) 4324 /*! PTDPE0 - Pull Enable for Port D Bit 0 4325 * 0b0..Pullup is disabled for port D bit 0. 4326 * 0b1..Pullup is enabled for port D bit 0. 4327 */ 4328 #define PORT_PUEL_PTDPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE0_SHIFT)) & PORT_PUEL_PTDPE0_MASK) 4329 #define PORT_PUEL_PTDPE1_MASK (0x2000000U) 4330 #define PORT_PUEL_PTDPE1_SHIFT (25U) 4331 /*! PTDPE1 - Pull Enable for Port D Bit 1 4332 * 0b0..Pullup is disabled for port D bit 1. 4333 * 0b1..Pullup is enabled for port D bit 1. 4334 */ 4335 #define PORT_PUEL_PTDPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE1_SHIFT)) & PORT_PUEL_PTDPE1_MASK) 4336 #define PORT_PUEL_PTDPE2_MASK (0x4000000U) 4337 #define PORT_PUEL_PTDPE2_SHIFT (26U) 4338 /*! PTDPE2 - Pull Enable for Port D Bit 2 4339 * 0b0..Pullup is disabled for port D bit 2. 4340 * 0b1..Pullup is enabled for port D bit 2. 4341 */ 4342 #define PORT_PUEL_PTDPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE2_SHIFT)) & PORT_PUEL_PTDPE2_MASK) 4343 #define PORT_PUEL_PTDPE3_MASK (0x8000000U) 4344 #define PORT_PUEL_PTDPE3_SHIFT (27U) 4345 /*! PTDPE3 - Pull Enable for Port D Bit 3 4346 * 0b0..Pullup is disabled for port D bit 3. 4347 * 0b1..Pullup is enabled for port D bit 3. 4348 */ 4349 #define PORT_PUEL_PTDPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE3_SHIFT)) & PORT_PUEL_PTDPE3_MASK) 4350 #define PORT_PUEL_PTDPE4_MASK (0x10000000U) 4351 #define PORT_PUEL_PTDPE4_SHIFT (28U) 4352 /*! PTDPE4 - Pull Enable for Port D Bit 4 4353 * 0b0..Pullup is disabled for port D bit 4. 4354 * 0b1..Pullup is enabled for port D bit 4. 4355 */ 4356 #define PORT_PUEL_PTDPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE4_SHIFT)) & PORT_PUEL_PTDPE4_MASK) 4357 #define PORT_PUEL_PTDPE5_MASK (0x20000000U) 4358 #define PORT_PUEL_PTDPE5_SHIFT (29U) 4359 /*! PTDPE5 - Pull Enable for Port D Bit 5 4360 * 0b0..Pullup is disabled for port D bit 5. 4361 * 0b1..Pullup is enabled for port D bit 5. 4362 */ 4363 #define PORT_PUEL_PTDPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE5_SHIFT)) & PORT_PUEL_PTDPE5_MASK) 4364 #define PORT_PUEL_PTDPE6_MASK (0x40000000U) 4365 #define PORT_PUEL_PTDPE6_SHIFT (30U) 4366 /*! PTDPE6 - Pull Enable for Port D Bit 6 4367 * 0b0..Pullup is disabled for port D bit 6. 4368 * 0b1..Pullup is enabled for port D bit 6. 4369 */ 4370 #define PORT_PUEL_PTDPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE6_SHIFT)) & PORT_PUEL_PTDPE6_MASK) 4371 #define PORT_PUEL_PTDPE7_MASK (0x80000000U) 4372 #define PORT_PUEL_PTDPE7_SHIFT (31U) 4373 /*! PTDPE7 - Pull Enable for Port D Bit 7 4374 * 0b0..Pullup is disabled for port D bit 7. 4375 * 0b1..Pullup is enabled for port D bit 7. 4376 */ 4377 #define PORT_PUEL_PTDPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEL_PTDPE7_SHIFT)) & PORT_PUEL_PTDPE7_MASK) 4378 /*! @} */ 4379 4380 /*! @name PUEH - Port Pullup Enable High Register */ 4381 /*! @{ */ 4382 #define PORT_PUEH_PTEPE0_MASK (0x1U) 4383 #define PORT_PUEH_PTEPE0_SHIFT (0U) 4384 /*! PTEPE0 - Pull Enable for Port E Bit 0 4385 * 0b0..Pullup is disabled for port E bit 0. 4386 * 0b1..Pullup is enabled for port E bit 0. 4387 */ 4388 #define PORT_PUEH_PTEPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE0_SHIFT)) & PORT_PUEH_PTEPE0_MASK) 4389 #define PORT_PUEH_PTEPE1_MASK (0x2U) 4390 #define PORT_PUEH_PTEPE1_SHIFT (1U) 4391 /*! PTEPE1 - Pull Enable for Port E Bit 1 4392 * 0b0..Pullup is disabled for port E bit 1. 4393 * 0b1..Pullup is enabled for port E bit 1. 4394 */ 4395 #define PORT_PUEH_PTEPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE1_SHIFT)) & PORT_PUEH_PTEPE1_MASK) 4396 #define PORT_PUEH_PTEPE2_MASK (0x4U) 4397 #define PORT_PUEH_PTEPE2_SHIFT (2U) 4398 /*! PTEPE2 - Pull Enable for Port E Bit 2 4399 * 0b0..Pullup is disabled for port E bit 2. 4400 * 0b1..Pullup is enabled for port E bit 2. 4401 */ 4402 #define PORT_PUEH_PTEPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE2_SHIFT)) & PORT_PUEH_PTEPE2_MASK) 4403 #define PORT_PUEH_PTEPE3_MASK (0x8U) 4404 #define PORT_PUEH_PTEPE3_SHIFT (3U) 4405 /*! PTEPE3 - Pull Enable for Port E Bit 3 4406 * 0b0..Pullup is disabled for port E bit 3. 4407 * 0b1..Pullup is enabled for port E bit 3. 4408 */ 4409 #define PORT_PUEH_PTEPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE3_SHIFT)) & PORT_PUEH_PTEPE3_MASK) 4410 #define PORT_PUEH_PTEPE4_MASK (0x10U) 4411 #define PORT_PUEH_PTEPE4_SHIFT (4U) 4412 /*! PTEPE4 - Pull Enable for Port E Bit 4 4413 * 0b0..Pullup is disabled for port E bit 4. 4414 * 0b1..Pullup is enabled for port E bit 4. 4415 */ 4416 #define PORT_PUEH_PTEPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE4_SHIFT)) & PORT_PUEH_PTEPE4_MASK) 4417 #define PORT_PUEH_PTEPE5_MASK (0x20U) 4418 #define PORT_PUEH_PTEPE5_SHIFT (5U) 4419 /*! PTEPE5 - Pull Enable for Port E Bit 5 4420 * 0b0..Pullup is disabled for port E bit 5. 4421 * 0b1..Pullup is enabled for port E bit 5. 4422 */ 4423 #define PORT_PUEH_PTEPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE5_SHIFT)) & PORT_PUEH_PTEPE5_MASK) 4424 #define PORT_PUEH_PTEPE6_MASK (0x40U) 4425 #define PORT_PUEH_PTEPE6_SHIFT (6U) 4426 /*! PTEPE6 - Pull Enable for Port E Bit 6 4427 * 0b0..Pullup is disabled for port E bit 6. 4428 * 0b1..Pullup is enabled for port E bit 6. 4429 */ 4430 #define PORT_PUEH_PTEPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE6_SHIFT)) & PORT_PUEH_PTEPE6_MASK) 4431 #define PORT_PUEH_PTEPE7_MASK (0x80U) 4432 #define PORT_PUEH_PTEPE7_SHIFT (7U) 4433 /*! PTEPE7 - Pull Enable for Port E Bit 7 4434 * 0b0..Pullup is disabled for port E bit 7. 4435 * 0b1..Pullup is enabled for port E bit 7. 4436 */ 4437 #define PORT_PUEH_PTEPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTEPE7_SHIFT)) & PORT_PUEH_PTEPE7_MASK) 4438 #define PORT_PUEH_PTFPE0_MASK (0x100U) 4439 #define PORT_PUEH_PTFPE0_SHIFT (8U) 4440 /*! PTFPE0 - Pull Enable for Port F Bit 0 4441 * 0b0..Pullup is disabled for port F bit 0. 4442 * 0b1..Pullup is enabled for port F bit 0. 4443 */ 4444 #define PORT_PUEH_PTFPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE0_SHIFT)) & PORT_PUEH_PTFPE0_MASK) 4445 #define PORT_PUEH_PTFPE1_MASK (0x200U) 4446 #define PORT_PUEH_PTFPE1_SHIFT (9U) 4447 /*! PTFPE1 - Pull Enable for Port F Bit 1 4448 * 0b0..Pullup is disabled for port F bit 1. 4449 * 0b1..Pullup is enabled for port F bit 1. 4450 */ 4451 #define PORT_PUEH_PTFPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE1_SHIFT)) & PORT_PUEH_PTFPE1_MASK) 4452 #define PORT_PUEH_PTFPE2_MASK (0x400U) 4453 #define PORT_PUEH_PTFPE2_SHIFT (10U) 4454 /*! PTFPE2 - Pull Enable for Port F Bit 2 4455 * 0b0..Pullup is disabled for port F bit 2. 4456 * 0b1..Pullup is enabled for port F bit 2. 4457 */ 4458 #define PORT_PUEH_PTFPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE2_SHIFT)) & PORT_PUEH_PTFPE2_MASK) 4459 #define PORT_PUEH_PTFPE3_MASK (0x800U) 4460 #define PORT_PUEH_PTFPE3_SHIFT (11U) 4461 /*! PTFPE3 - Pull Enable for Port F Bit 3 4462 * 0b0..Pullup is disabled for port F bit 3. 4463 * 0b1..Pullup is enabled for port F bit 3. 4464 */ 4465 #define PORT_PUEH_PTFPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE3_SHIFT)) & PORT_PUEH_PTFPE3_MASK) 4466 #define PORT_PUEH_PTFPE4_MASK (0x1000U) 4467 #define PORT_PUEH_PTFPE4_SHIFT (12U) 4468 /*! PTFPE4 - Pull Enable for Port F Bit 4 4469 * 0b0..Pullup is disabled for port F bit 4. 4470 * 0b1..Pullup is enabled for port F bit 4. 4471 */ 4472 #define PORT_PUEH_PTFPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE4_SHIFT)) & PORT_PUEH_PTFPE4_MASK) 4473 #define PORT_PUEH_PTFPE5_MASK (0x2000U) 4474 #define PORT_PUEH_PTFPE5_SHIFT (13U) 4475 /*! PTFPE5 - Pull Enable for Port F Bit 5 4476 * 0b0..Pullup is disabled for port F bit 5. 4477 * 0b1..Pullup is enabled for port F bit 5. 4478 */ 4479 #define PORT_PUEH_PTFPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE5_SHIFT)) & PORT_PUEH_PTFPE5_MASK) 4480 #define PORT_PUEH_PTFPE6_MASK (0x4000U) 4481 #define PORT_PUEH_PTFPE6_SHIFT (14U) 4482 /*! PTFPE6 - Pull Enable for Port F Bit 6 4483 * 0b0..Pullup is disabled for port F bit 6. 4484 * 0b1..Pullup is enabled for port F bit 6. 4485 */ 4486 #define PORT_PUEH_PTFPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE6_SHIFT)) & PORT_PUEH_PTFPE6_MASK) 4487 #define PORT_PUEH_PTFPE7_MASK (0x8000U) 4488 #define PORT_PUEH_PTFPE7_SHIFT (15U) 4489 /*! PTFPE7 - Pull Enable for Port F Bit 7 4490 * 0b0..Pullup is disabled for port F bit 7. 4491 * 0b1..Pullup is enabled for port F bit 7. 4492 */ 4493 #define PORT_PUEH_PTFPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTFPE7_SHIFT)) & PORT_PUEH_PTFPE7_MASK) 4494 #define PORT_PUEH_PTGPE0_MASK (0x10000U) 4495 #define PORT_PUEH_PTGPE0_SHIFT (16U) 4496 /*! PTGPE0 - Pull Enable for Port G Bit 0 4497 * 0b0..Pullup is disabled for port G bit 0. 4498 * 0b1..Pullup is enabled for port G bit 0. 4499 */ 4500 #define PORT_PUEH_PTGPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTGPE0_SHIFT)) & PORT_PUEH_PTGPE0_MASK) 4501 #define PORT_PUEH_PTGPE1_MASK (0x20000U) 4502 #define PORT_PUEH_PTGPE1_SHIFT (17U) 4503 /*! PTGPE1 - Pull Enable for Port G Bit 1 4504 * 0b0..Pullup is disabled for port G bit 1. 4505 * 0b1..Pullup is enabled for port G bit 1. 4506 */ 4507 #define PORT_PUEH_PTGPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTGPE1_SHIFT)) & PORT_PUEH_PTGPE1_MASK) 4508 #define PORT_PUEH_PTGPE2_MASK (0x40000U) 4509 #define PORT_PUEH_PTGPE2_SHIFT (18U) 4510 /*! PTGPE2 - Pull Enable for Port G Bit 2 4511 * 0b0..Pullup is disabled for port G bit 2. 4512 * 0b1..Pullup is enabled for port G bit 2. 4513 */ 4514 #define PORT_PUEH_PTGPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTGPE2_SHIFT)) & PORT_PUEH_PTGPE2_MASK) 4515 #define PORT_PUEH_PTGPE3_MASK (0x80000U) 4516 #define PORT_PUEH_PTGPE3_SHIFT (19U) 4517 /*! PTGPE3 - Pull Enable for Port G Bit 3 4518 * 0b0..Pullup is disabled for port G bit 3. 4519 * 0b1..Pullup is enabled for port G bit 3. 4520 */ 4521 #define PORT_PUEH_PTGPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTGPE3_SHIFT)) & PORT_PUEH_PTGPE3_MASK) 4522 #define PORT_PUEH_PTHPE0_MASK (0x1000000U) 4523 #define PORT_PUEH_PTHPE0_SHIFT (24U) 4524 /*! PTHPE0 - Pull Enable for Port H Bit 0 4525 * 0b0..Pullup is disabled for port H bit 0. 4526 * 0b1..Pullup is enabled for port H bit 0. 4527 */ 4528 #define PORT_PUEH_PTHPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTHPE0_SHIFT)) & PORT_PUEH_PTHPE0_MASK) 4529 #define PORT_PUEH_PTHPE1_MASK (0x2000000U) 4530 #define PORT_PUEH_PTHPE1_SHIFT (25U) 4531 /*! PTHPE1 - Pull Enable for Port H Bit 1 4532 * 0b0..Pullup is disabled for port H bit 1. 4533 * 0b1..Pullup is enabled for port H bit 1. 4534 */ 4535 #define PORT_PUEH_PTHPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTHPE1_SHIFT)) & PORT_PUEH_PTHPE1_MASK) 4536 #define PORT_PUEH_PTHPE2_MASK (0x4000000U) 4537 #define PORT_PUEH_PTHPE2_SHIFT (26U) 4538 /*! PTHPE2 - Pull Enable for Port H Bit 2 4539 * 0b0..Pullup is disabled for port H bit 2. 4540 * 0b1..Pullup is enabled for port H bit 2. 4541 */ 4542 #define PORT_PUEH_PTHPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTHPE2_SHIFT)) & PORT_PUEH_PTHPE2_MASK) 4543 #define PORT_PUEH_PTHPE6_MASK (0x40000000U) 4544 #define PORT_PUEH_PTHPE6_SHIFT (30U) 4545 /*! PTHPE6 - Pull Enable for Port H Bit 6 4546 * 0b0..Pullup is disabled for port H bit 6. 4547 * 0b1..Pullup is enabled for port H bit 6. 4548 */ 4549 #define PORT_PUEH_PTHPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTHPE6_SHIFT)) & PORT_PUEH_PTHPE6_MASK) 4550 #define PORT_PUEH_PTHPE7_MASK (0x80000000U) 4551 #define PORT_PUEH_PTHPE7_SHIFT (31U) 4552 /*! PTHPE7 - Pull Enable for Port H Bit 7 4553 * 0b0..Pullup is disabled for port H bit 7. 4554 * 0b1..Pullup is enabled for port H bit 7. 4555 */ 4556 #define PORT_PUEH_PTHPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUEH_PTHPE7_SHIFT)) & PORT_PUEH_PTHPE7_MASK) 4557 /*! @} */ 4558 4559 /*! @name HDRVE - Port High Drive Enable Register */ 4560 /*! @{ */ 4561 #define PORT_HDRVE_PTB4_MASK (0x1U) 4562 #define PORT_HDRVE_PTB4_SHIFT (0U) 4563 /*! PTB4 - High Current Drive Capability of PTB4 4564 * 0b0..PTB4 is disabled to offer high current drive capability. 4565 * 0b1..PTB4 is enabled to offer high current drive capability. 4566 */ 4567 #define PORT_HDRVE_PTB4(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTB4_SHIFT)) & PORT_HDRVE_PTB4_MASK) 4568 #define PORT_HDRVE_PTB5_MASK (0x2U) 4569 #define PORT_HDRVE_PTB5_SHIFT (1U) 4570 /*! PTB5 - High Current Drive Capability of PTB5 4571 * 0b0..PTB5 is disabled to offer high current drive capability. 4572 * 0b1..PTB5 is enabled to offer high current drive capability. 4573 */ 4574 #define PORT_HDRVE_PTB5(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTB5_SHIFT)) & PORT_HDRVE_PTB5_MASK) 4575 #define PORT_HDRVE_PTD0_MASK (0x4U) 4576 #define PORT_HDRVE_PTD0_SHIFT (2U) 4577 /*! PTD0 - High Current Drive Capability of PTD0 4578 * 0b0..PTD0 is disabled to offer high current drive capability. 4579 * 0b1..PTD0 is enabled to offer high current drive capability. 4580 */ 4581 #define PORT_HDRVE_PTD0(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTD0_SHIFT)) & PORT_HDRVE_PTD0_MASK) 4582 #define PORT_HDRVE_PTD1_MASK (0x8U) 4583 #define PORT_HDRVE_PTD1_SHIFT (3U) 4584 /*! PTD1 - High Current Drive Capability of PTD1 4585 * 0b0..PTD1 is disabled to offer high current drive capability. 4586 * 0b1..PTD1 is enable to offer high current drive capability. 4587 */ 4588 #define PORT_HDRVE_PTD1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTD1_SHIFT)) & PORT_HDRVE_PTD1_MASK) 4589 #define PORT_HDRVE_PTE0_MASK (0x10U) 4590 #define PORT_HDRVE_PTE0_SHIFT (4U) 4591 /*! PTE0 - High Current Drive Capability of PTE0 4592 * 0b0..PTE0 is disabled to offer high current drive capability. 4593 * 0b1..PTE0 is enable to offer high current drive capability. 4594 */ 4595 #define PORT_HDRVE_PTE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTE0_SHIFT)) & PORT_HDRVE_PTE0_MASK) 4596 #define PORT_HDRVE_PTE1_MASK (0x20U) 4597 #define PORT_HDRVE_PTE1_SHIFT (5U) 4598 /*! PTE1 - High Current Drive Capability of PTE1 4599 * 0b0..PTE1 is disabled to offer high current drive capability. 4600 * 0b1..PTE1 is enabled to offer high current drive capability. 4601 */ 4602 #define PORT_HDRVE_PTE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTE1_SHIFT)) & PORT_HDRVE_PTE1_MASK) 4603 #define PORT_HDRVE_PTH0_MASK (0x40U) 4604 #define PORT_HDRVE_PTH0_SHIFT (6U) 4605 /*! PTH0 - High Current Drive Capability of PTH0 4606 * 0b0..PTH0 is disabled to offer high current drive capability. 4607 * 0b1..PTH0 is enabled to offer high current drive capability. 4608 */ 4609 #define PORT_HDRVE_PTH0(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTH0_SHIFT)) & PORT_HDRVE_PTH0_MASK) 4610 #define PORT_HDRVE_PTH1_MASK (0x80U) 4611 #define PORT_HDRVE_PTH1_SHIFT (7U) 4612 /*! PTH1 - High Current Drive Capability of PTH1 4613 * 0b0..PTH1 is disabled to offer high current drive capability. 4614 * 0b1..PTH1 is enabled to offer high current drive capability. 4615 */ 4616 #define PORT_HDRVE_PTH1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTH1_SHIFT)) & PORT_HDRVE_PTH1_MASK) 4617 /*! @} */ 4618 4619 4620 /*! 4621 * @} 4622 */ /* end of group PORT_Register_Masks */ 4623 4624 4625 /* PORT - Peripheral instance base addresses */ 4626 /** Peripheral PORT base address */ 4627 #define PORT_BASE (0x40049000u) 4628 /** Peripheral PORT base pointer */ 4629 #define PORT ((PORT_Type *)PORT_BASE) 4630 /** Array initializer of PORT peripheral base addresses */ 4631 #define PORT_BASE_ADDRS { PORT_BASE } 4632 /** Array initializer of PORT peripheral base pointers */ 4633 #define PORT_BASE_PTRS { PORT } 4634 4635 /*! 4636 * @} 4637 */ /* end of group PORT_Peripheral_Access_Layer */ 4638 4639 4640 /* ---------------------------------------------------------------------------- 4641 -- ROM Peripheral Access Layer 4642 ---------------------------------------------------------------------------- */ 4643 4644 /*! 4645 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 4646 * @{ 4647 */ 4648 4649 /** ROM - Register Layout Typedef */ 4650 typedef struct { 4651 __I uint32_t ENTRY[1]; /**< Entry, array offset: 0x0, array step: 0x4 */ 4652 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0x4 */ 4653 uint8_t RESERVED_0[4036]; 4654 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 4655 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 4656 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 4657 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 4658 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 4659 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 4660 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 4661 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 4662 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 4663 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 4664 } ROM_Type; 4665 4666 /* ---------------------------------------------------------------------------- 4667 -- ROM Register Masks 4668 ---------------------------------------------------------------------------- */ 4669 4670 /*! 4671 * @addtogroup ROM_Register_Masks ROM Register Masks 4672 * @{ 4673 */ 4674 4675 /*! @name ENTRY - Entry */ 4676 /*! @{ */ 4677 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 4678 #define ROM_ENTRY_ENTRY_SHIFT (0U) 4679 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 4680 /*! @} */ 4681 4682 /* The count of ROM_ENTRY */ 4683 #define ROM_ENTRY_COUNT (1U) 4684 4685 /*! @name TABLEMARK - End of Table Marker Register */ 4686 /*! @{ */ 4687 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 4688 #define ROM_TABLEMARK_MARK_SHIFT (0U) 4689 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 4690 /*! @} */ 4691 4692 /*! @name SYSACCESS - System Access Register */ 4693 /*! @{ */ 4694 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 4695 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 4696 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 4697 /*! @} */ 4698 4699 /*! @name PERIPHID4 - Peripheral ID Register */ 4700 /*! @{ */ 4701 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 4702 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 4703 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 4704 /*! @} */ 4705 4706 /*! @name PERIPHID5 - Peripheral ID Register */ 4707 /*! @{ */ 4708 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 4709 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 4710 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 4711 /*! @} */ 4712 4713 /*! @name PERIPHID6 - Peripheral ID Register */ 4714 /*! @{ */ 4715 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 4716 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 4717 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 4718 /*! @} */ 4719 4720 /*! @name PERIPHID7 - Peripheral ID Register */ 4721 /*! @{ */ 4722 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 4723 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 4724 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 4725 /*! @} */ 4726 4727 /*! @name PERIPHID0 - Peripheral ID Register */ 4728 /*! @{ */ 4729 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 4730 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 4731 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 4732 /*! @} */ 4733 4734 /*! @name PERIPHID1 - Peripheral ID Register */ 4735 /*! @{ */ 4736 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 4737 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 4738 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 4739 /*! @} */ 4740 4741 /*! @name PERIPHID2 - Peripheral ID Register */ 4742 /*! @{ */ 4743 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 4744 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 4745 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 4746 /*! @} */ 4747 4748 /*! @name PERIPHID3 - Peripheral ID Register */ 4749 /*! @{ */ 4750 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 4751 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 4752 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 4753 /*! @} */ 4754 4755 /*! @name COMPID - Component ID Register */ 4756 /*! @{ */ 4757 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 4758 #define ROM_COMPID_COMPID_SHIFT (0U) 4759 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 4760 /*! @} */ 4761 4762 /* The count of ROM_COMPID */ 4763 #define ROM_COMPID_COUNT (4U) 4764 4765 4766 /*! 4767 * @} 4768 */ /* end of group ROM_Register_Masks */ 4769 4770 4771 /* ROM - Peripheral instance base addresses */ 4772 /** Peripheral ROM base address */ 4773 #define ROM_BASE (0xF0002000u) 4774 /** Peripheral ROM base pointer */ 4775 #define ROM ((ROM_Type *)ROM_BASE) 4776 /** Array initializer of ROM peripheral base addresses */ 4777 #define ROM_BASE_ADDRS { ROM_BASE } 4778 /** Array initializer of ROM peripheral base pointers */ 4779 #define ROM_BASE_PTRS { ROM } 4780 4781 /*! 4782 * @} 4783 */ /* end of group ROM_Peripheral_Access_Layer */ 4784 4785 4786 /* ---------------------------------------------------------------------------- 4787 -- RTC Peripheral Access Layer 4788 ---------------------------------------------------------------------------- */ 4789 4790 /*! 4791 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 4792 * @{ 4793 */ 4794 4795 /** RTC - Register Layout Typedef */ 4796 typedef struct { 4797 __IO uint32_t SC; /**< RTC Status and Control Register, offset: 0x0 */ 4798 __IO uint32_t MOD; /**< RTC Modulo Register, offset: 0x4 */ 4799 __I uint32_t CNT; /**< RTC Counter Register, offset: 0x8 */ 4800 } RTC_Type; 4801 4802 /* ---------------------------------------------------------------------------- 4803 -- RTC Register Masks 4804 ---------------------------------------------------------------------------- */ 4805 4806 /*! 4807 * @addtogroup RTC_Register_Masks RTC Register Masks 4808 * @{ 4809 */ 4810 4811 /*! @name SC - RTC Status and Control Register */ 4812 /*! @{ */ 4813 #define RTC_SC_RTCO_MASK (0x10U) 4814 #define RTC_SC_RTCO_SHIFT (4U) 4815 /*! RTCO - Real-Time Counter Output 4816 * 0b0..Real-time counter output disabled. 4817 * 0b1..Real-time counter output enabled. 4818 */ 4819 #define RTC_SC_RTCO(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCO_SHIFT)) & RTC_SC_RTCO_MASK) 4820 #define RTC_SC_RTIE_MASK (0x40U) 4821 #define RTC_SC_RTIE_SHIFT (6U) 4822 /*! RTIE - Real-Time Interrupt Enable 4823 * 0b0..Real-time interrupt requests are disabled. Use software polling. 4824 * 0b1..Real-time interrupt requests are enabled. 4825 */ 4826 #define RTC_SC_RTIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTIE_SHIFT)) & RTC_SC_RTIE_MASK) 4827 #define RTC_SC_RTIF_MASK (0x80U) 4828 #define RTC_SC_RTIF_SHIFT (7U) 4829 /*! RTIF - Real-Time Interrupt Flag 4830 * 0b0..RTC counter has not reached the value in the RTC modulo register. 4831 * 0b1..RTC counter has reached the value in the RTC modulo register. 4832 */ 4833 #define RTC_SC_RTIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTIF_SHIFT)) & RTC_SC_RTIF_MASK) 4834 #define RTC_SC_RTCPS_MASK (0x700U) 4835 #define RTC_SC_RTCPS_SHIFT (8U) 4836 /*! RTCPS - Real-Time Clock Prescaler Select 4837 * 0b000..Off 4838 * 0b001..If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128. 4839 * 0b010..If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256. 4840 * 0b011..If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512. 4841 * 0b100..If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024. 4842 * 0b101..If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048. 4843 * 0b110..If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100. 4844 * 0b111..If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000. 4845 */ 4846 #define RTC_SC_RTCPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCPS_SHIFT)) & RTC_SC_RTCPS_MASK) 4847 #define RTC_SC_RTCLKS_MASK (0xC000U) 4848 #define RTC_SC_RTCLKS_SHIFT (14U) 4849 /*! RTCLKS - Real-Time Clock Source Select 4850 * 0b00..External clock source. 4851 * 0b01..Real-time clock source is 1 kHz (LPOCLK). 4852 * 0b10..Internal reference clock (ICSIRCLK). 4853 * 0b11..Bus clock. 4854 */ 4855 #define RTC_SC_RTCLKS(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCLKS_SHIFT)) & RTC_SC_RTCLKS_MASK) 4856 /*! @} */ 4857 4858 /*! @name MOD - RTC Modulo Register */ 4859 /*! @{ */ 4860 #define RTC_MOD_MOD_MASK (0xFFFFU) 4861 #define RTC_MOD_MOD_SHIFT (0U) 4862 #define RTC_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << RTC_MOD_MOD_SHIFT)) & RTC_MOD_MOD_MASK) 4863 /*! @} */ 4864 4865 /*! @name CNT - RTC Counter Register */ 4866 /*! @{ */ 4867 #define RTC_CNT_CNT_MASK (0xFFFFU) 4868 #define RTC_CNT_CNT_SHIFT (0U) 4869 #define RTC_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_CNT_SHIFT)) & RTC_CNT_CNT_MASK) 4870 /*! @} */ 4871 4872 4873 /*! 4874 * @} 4875 */ /* end of group RTC_Register_Masks */ 4876 4877 4878 /* RTC - Peripheral instance base addresses */ 4879 /** Peripheral RTC base address */ 4880 #define RTC_BASE (0x4003D000u) 4881 /** Peripheral RTC base pointer */ 4882 #define RTC ((RTC_Type *)RTC_BASE) 4883 /** Array initializer of RTC peripheral base addresses */ 4884 #define RTC_BASE_ADDRS { RTC_BASE } 4885 /** Array initializer of RTC peripheral base pointers */ 4886 #define RTC_BASE_PTRS { RTC } 4887 /** Interrupt vectors for the RTC peripheral type */ 4888 #define RTC_IRQS { RTC_IRQn } 4889 4890 /*! 4891 * @} 4892 */ /* end of group RTC_Peripheral_Access_Layer */ 4893 4894 4895 /* ---------------------------------------------------------------------------- 4896 -- SIM Peripheral Access Layer 4897 ---------------------------------------------------------------------------- */ 4898 4899 /*! 4900 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 4901 * @{ 4902 */ 4903 4904 /** SIM - Register Layout Typedef */ 4905 typedef struct { 4906 __I uint32_t SRSID; /**< System Reset Status and ID Register, offset: 0x0 */ 4907 __IO uint32_t SOPT; /**< System Options Register, offset: 0x4 */ 4908 __IO uint32_t PINSEL; /**< Pin Selection Register, offset: 0x8 */ 4909 __IO uint32_t SCGC; /**< System Clock Gating Control Register, offset: 0xC */ 4910 __I uint32_t UUIDL; /**< Universally Unique Identifier Low Register, offset: 0x10 */ 4911 __I uint32_t UUIDH; /**< Universally Unique Identifier High Register, offset: 0x14 */ 4912 __IO uint32_t BUSDIV; /**< BUS Clock Divider Register, offset: 0x18 */ 4913 } SIM_Type; 4914 4915 /* ---------------------------------------------------------------------------- 4916 -- SIM Register Masks 4917 ---------------------------------------------------------------------------- */ 4918 4919 /*! 4920 * @addtogroup SIM_Register_Masks SIM Register Masks 4921 * @{ 4922 */ 4923 4924 /*! @name SRSID - System Reset Status and ID Register */ 4925 /*! @{ */ 4926 #define SIM_SRSID_LVD_MASK (0x2U) 4927 #define SIM_SRSID_LVD_SHIFT (1U) 4928 /*! LVD - Low Voltage Detect 4929 * 0b0..Reset is not caused by LVD trip or POR. 4930 * 0b1..Reset is caused by LVD trip or POR. 4931 */ 4932 #define SIM_SRSID_LVD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LVD_SHIFT)) & SIM_SRSID_LVD_MASK) 4933 #define SIM_SRSID_LOC_MASK (0x4U) 4934 #define SIM_SRSID_LOC_SHIFT (2U) 4935 /*! LOC - Internal Clock Source Module Reset 4936 * 0b0..Reset is not caused by the ICS module. 4937 * 0b1..Reset is caused by the ICS module. 4938 */ 4939 #define SIM_SRSID_LOC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LOC_SHIFT)) & SIM_SRSID_LOC_MASK) 4940 #define SIM_SRSID_WDOG_MASK (0x20U) 4941 #define SIM_SRSID_WDOG_SHIFT (5U) 4942 /*! WDOG - Watchdog (WDOG) 4943 * 0b0..Reset is not caused by WDOG timeout. 4944 * 0b1..Reset is caused by WDOG timeout. 4945 */ 4946 #define SIM_SRSID_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_WDOG_SHIFT)) & SIM_SRSID_WDOG_MASK) 4947 #define SIM_SRSID_PIN_MASK (0x40U) 4948 #define SIM_SRSID_PIN_SHIFT (6U) 4949 /*! PIN - External Reset Pin 4950 * 0b0..Reset is not caused by external reset pin. 4951 * 0b1..Reset came from external reset pin. 4952 */ 4953 #define SIM_SRSID_PIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_PIN_SHIFT)) & SIM_SRSID_PIN_MASK) 4954 #define SIM_SRSID_POR_MASK (0x80U) 4955 #define SIM_SRSID_POR_SHIFT (7U) 4956 /*! POR - Power-On Reset 4957 * 0b0..Reset not caused by POR. 4958 * 0b1..POR caused reset. 4959 */ 4960 #define SIM_SRSID_POR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_POR_SHIFT)) & SIM_SRSID_POR_MASK) 4961 #define SIM_SRSID_LOCKUP_MASK (0x200U) 4962 #define SIM_SRSID_LOCKUP_SHIFT (9U) 4963 /*! LOCKUP - Core Lockup 4964 * 0b0..Reset is not caused by core LOCKUP event. 4965 * 0b1..Reset is caused by core LOCKUP event. 4966 */ 4967 #define SIM_SRSID_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LOCKUP_SHIFT)) & SIM_SRSID_LOCKUP_MASK) 4968 #define SIM_SRSID_SW_MASK (0x400U) 4969 #define SIM_SRSID_SW_SHIFT (10U) 4970 /*! SW - Software 4971 * 0b0..Reset is not caused by software setting of SYSRESETREQ bit. 4972 * 0b1..Reset caused by software setting of SYSRESETREQ bit 4973 */ 4974 #define SIM_SRSID_SW(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SW_SHIFT)) & SIM_SRSID_SW_MASK) 4975 #define SIM_SRSID_MDMAP_MASK (0x800U) 4976 #define SIM_SRSID_MDMAP_SHIFT (11U) 4977 /*! MDMAP - MDM-AP System Reset Request 4978 * 0b0..Reset is not caused by host debugger system setting of the System Reset Request bit. 4979 * 0b1..Reset is caused by host debugger system setting of the System Reset Request bit. 4980 */ 4981 #define SIM_SRSID_MDMAP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_MDMAP_SHIFT)) & SIM_SRSID_MDMAP_MASK) 4982 #define SIM_SRSID_SACKERR_MASK (0x2000U) 4983 #define SIM_SRSID_SACKERR_SHIFT (13U) 4984 /*! SACKERR - Stop Mode Acknowledge Error Reset 4985 * 0b0..Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode. 4986 * 0b1..Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode. 4987 */ 4988 #define SIM_SRSID_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SACKERR_SHIFT)) & SIM_SRSID_SACKERR_MASK) 4989 #define SIM_SRSID_PINID_MASK (0xF0000U) 4990 #define SIM_SRSID_PINID_SHIFT (16U) 4991 /*! PINID - Device Pin ID 4992 * 0b0000..8-pin 4993 * 0b0001..16-pin 4994 * 0b0010..20-pin 4995 * 0b0011..24-pin 4996 * 0b0100..32-pin 4997 * 0b0101..44-pin 4998 * 0b0110..48-pin 4999 * 0b0111..64-pin 5000 * 0b1000..80-pin 5001 * 0b1010..100-pin 5002 */ 5003 #define SIM_SRSID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_PINID_SHIFT)) & SIM_SRSID_PINID_MASK) 5004 #define SIM_SRSID_RevID_MASK (0xF00000U) 5005 #define SIM_SRSID_RevID_SHIFT (20U) 5006 #define SIM_SRSID_RevID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_RevID_SHIFT)) & SIM_SRSID_RevID_MASK) 5007 #define SIM_SRSID_SUBFAMID_MASK (0xF000000U) 5008 #define SIM_SRSID_SUBFAMID_SHIFT (24U) 5009 /*! SUBFAMID - Kinetis sub-family ID 5010 * 0b0010..KEx2 sub-family 5011 */ 5012 #define SIM_SRSID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SUBFAMID_SHIFT)) & SIM_SRSID_SUBFAMID_MASK) 5013 #define SIM_SRSID_FAMID_MASK (0xF0000000U) 5014 #define SIM_SRSID_FAMID_SHIFT (28U) 5015 /*! FAMID - Kinetis family ID 5016 * 0b0000..KE0x family. 5017 */ 5018 #define SIM_SRSID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_FAMID_SHIFT)) & SIM_SRSID_FAMID_MASK) 5019 /*! @} */ 5020 5021 /*! @name SOPT - System Options Register */ 5022 /*! @{ */ 5023 #define SIM_SOPT_NMIE_MASK (0x2U) 5024 #define SIM_SOPT_NMIE_SHIFT (1U) 5025 /*! NMIE - NMI Pin Enable 5026 * 0b0..PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as PTB4, FTM2_CH4, SPI0_MISO, or ACMP1_IN2. 5027 * 0b1..PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as NMI. 5028 */ 5029 #define SIM_SOPT_NMIE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_NMIE_SHIFT)) & SIM_SOPT_NMIE_MASK) 5030 #define SIM_SOPT_RSTPE_MASK (0x4U) 5031 #define SIM_SOPT_RSTPE_SHIFT (2U) 5032 /*! RSTPE - RESET Pin Enable 5033 * 0b0..PTA5/IRQ/FTM0_CLK/RESET pin functions as PTA5, IRQ, or FTM0_CLK. 5034 * 0b1..PTA5/IRQ/FTM0_CLK/RESET pin functions as RESET. 5035 */ 5036 #define SIM_SOPT_RSTPE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RSTPE_SHIFT)) & SIM_SOPT_RSTPE_MASK) 5037 #define SIM_SOPT_SWDE_MASK (0x8U) 5038 #define SIM_SOPT_SWDE_SHIFT (3U) 5039 /*! SWDE - Single Wire Debug Port Pin Enable 5040 * 0b0..PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/RTCO/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, RTCO, FTM1_CH0, or ACMP0_IN2 function. 5041 * 0b1..PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/RTCO/FTM1CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function. 5042 */ 5043 #define SIM_SOPT_SWDE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_SWDE_SHIFT)) & SIM_SOPT_SWDE_MASK) 5044 #define SIM_SOPT_ADHWT_MASK (0x300U) 5045 #define SIM_SOPT_ADHWT_SHIFT (8U) 5046 /*! ADHWT - ADC Hardware Trigger Source 5047 * 0b00..RTC overflow as the ADC hardware trigger 5048 * 0b01..PIT overflow as the ADC hardware trigger 5049 * 0b10..FTM2 init trigger with 8-bit programmable delay 5050 * 0b11..FTM2 match trigger with 8-bit programmable delay 5051 */ 5052 #define SIM_SOPT_ADHWT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_ADHWT_SHIFT)) & SIM_SOPT_ADHWT_MASK) 5053 #define SIM_SOPT_RTCC_MASK (0x400U) 5054 #define SIM_SOPT_RTCC_SHIFT (10U) 5055 /*! RTCC - Real-Time Counter Capture 5056 * 0b0..RTC overflow is not connected to FTM1 input channel 1. 5057 * 0b1..RTC overflow is connected to FTM1 input channel 1. 5058 */ 5059 #define SIM_SOPT_RTCC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RTCC_SHIFT)) & SIM_SOPT_RTCC_MASK) 5060 #define SIM_SOPT_ACIC_MASK (0x800U) 5061 #define SIM_SOPT_ACIC_SHIFT (11U) 5062 /*! ACIC - Analog Comparator to Input Capture Enable 5063 * 0b0..ACMP0 output is not connected to FTM1 input channel 0. 5064 * 0b1..ACMP0 output is connected to FTM1 input channel 0. 5065 */ 5066 #define SIM_SOPT_ACIC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_ACIC_SHIFT)) & SIM_SOPT_ACIC_MASK) 5067 #define SIM_SOPT_RXDCE_MASK (0x1000U) 5068 #define SIM_SOPT_RXDCE_SHIFT (12U) 5069 /*! RXDCE - UART0_RX Capture Select 5070 * 0b0..UART0_RX input signal is connected to the UART0 module only. 5071 * 0b1..UART0_RX input signal is connected to the UART0 module and FTM0 channel 1. 5072 */ 5073 #define SIM_SOPT_RXDCE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RXDCE_SHIFT)) & SIM_SOPT_RXDCE_MASK) 5074 #define SIM_SOPT_RXDFE_MASK (0x2000U) 5075 #define SIM_SOPT_RXDFE_SHIFT (13U) 5076 /*! RXDFE - UART0_RX Filter Select 5077 * 0b0..UART0_RX input signal is connected to UART0 module directly. 5078 * 0b1..UART0_RX input signal is filtered by ACMP, then injected to UART0. 5079 */ 5080 #define SIM_SOPT_RXDFE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_RXDFE_SHIFT)) & SIM_SOPT_RXDFE_MASK) 5081 #define SIM_SOPT_FTMSYNC_MASK (0x4000U) 5082 #define SIM_SOPT_FTMSYNC_SHIFT (14U) 5083 /*! FTMSYNC - FTM2 Synchronization Select 5084 * 0b0..No synchronization triggered. 5085 * 0b1..Generates a PWM synchronization trigger to the FTM2 modules. 5086 */ 5087 #define SIM_SOPT_FTMSYNC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_FTMSYNC_SHIFT)) & SIM_SOPT_FTMSYNC_MASK) 5088 #define SIM_SOPT_TXDME_MASK (0x8000U) 5089 #define SIM_SOPT_TXDME_SHIFT (15U) 5090 /*! TXDME - UART0_TX Modulation Select 5091 * 0b0..UART0_TX output is connected to pinout directly. 5092 * 0b1..UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout. 5093 */ 5094 #define SIM_SOPT_TXDME(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_TXDME_SHIFT)) & SIM_SOPT_TXDME_MASK) 5095 #define SIM_SOPT_BUSREF_MASK (0x70000U) 5096 #define SIM_SOPT_BUSREF_SHIFT (16U) 5097 /*! BUSREF - BUS Clock Output select 5098 * 0b000..Bus 5099 * 0b001..Bus divided by 2 5100 * 0b010..Bus divided by 4 5101 * 0b011..Bus divided by 8 5102 * 0b100..Bus divided by 16 5103 * 0b101..Bus divided by 32 5104 * 0b110..Bus divided by 64 5105 * 0b111..Bus divided by 128 5106 */ 5107 #define SIM_SOPT_BUSREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_BUSREF_SHIFT)) & SIM_SOPT_BUSREF_MASK) 5108 #define SIM_SOPT_CLKOE_MASK (0x80000U) 5109 #define SIM_SOPT_CLKOE_SHIFT (19U) 5110 /*! CLKOE - Bus Clock Output Enable 5111 * 0b0..Bus clock output is disabled on PTH2. 5112 * 0b1..Bus clock output is enabled on PTH2. 5113 */ 5114 #define SIM_SOPT_CLKOE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_CLKOE_SHIFT)) & SIM_SOPT_CLKOE_MASK) 5115 #define SIM_SOPT_DLYACT_MASK (0x800000U) 5116 #define SIM_SOPT_DLYACT_SHIFT (23U) 5117 /*! DLYACT - FTM2 Trigger Delay Active 5118 * 0b0..The delay is inactive. 5119 * 0b1..The delay is active. 5120 */ 5121 #define SIM_SOPT_DLYACT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_DLYACT_SHIFT)) & SIM_SOPT_DLYACT_MASK) 5122 #define SIM_SOPT_DELAY_MASK (0xFF000000U) 5123 #define SIM_SOPT_DELAY_SHIFT (24U) 5124 #define SIM_SOPT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT_DELAY_SHIFT)) & SIM_SOPT_DELAY_MASK) 5125 /*! @} */ 5126 5127 /*! @name PINSEL - Pin Selection Register */ 5128 /*! @{ */ 5129 #define SIM_PINSEL_RTCPS_MASK (0x10U) 5130 #define SIM_PINSEL_RTCPS_SHIFT (4U) 5131 /*! RTCPS - RTCO Pin Select 5132 * 0b0..RTCO is mapped on PTC4. 5133 * 0b1..RTCO is mapped on PTC5. 5134 */ 5135 #define SIM_PINSEL_RTCPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_RTCPS_SHIFT)) & SIM_PINSEL_RTCPS_MASK) 5136 #define SIM_PINSEL_I2C0PS_MASK (0x20U) 5137 #define SIM_PINSEL_I2C0PS_SHIFT (5U) 5138 /*! I2C0PS - I2C0 Port Pin Select 5139 * 0b0..I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. 5140 * 0b1..I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. 5141 */ 5142 #define SIM_PINSEL_I2C0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_I2C0PS_SHIFT)) & SIM_PINSEL_I2C0PS_MASK) 5143 #define SIM_PINSEL_SPI0PS_MASK (0x40U) 5144 #define SIM_PINSEL_SPI0PS_SHIFT (6U) 5145 /*! SPI0PS - SPI0 Pin Select 5146 * 0b0..SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTB2, PTB3, PTB4, and PTB5. 5147 * 0b1..SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTE0, PTE1, PTE2, and PTE3. 5148 */ 5149 #define SIM_PINSEL_SPI0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_SPI0PS_SHIFT)) & SIM_PINSEL_SPI0PS_MASK) 5150 #define SIM_PINSEL_UART0PS_MASK (0x80U) 5151 #define SIM_PINSEL_UART0PS_SHIFT (7U) 5152 /*! UART0PS - UART0 Pin Select 5153 * 0b0..UART0_RX and UART0_TX are mapped on PTB0 and PTB1. 5154 * 0b1..UART0_RX and UART0_TX are mapped on PTA2 and PTA3. 5155 */ 5156 #define SIM_PINSEL_UART0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_UART0PS_SHIFT)) & SIM_PINSEL_UART0PS_MASK) 5157 #define SIM_PINSEL_FTM0PS0_MASK (0x100U) 5158 #define SIM_PINSEL_FTM0PS0_SHIFT (8U) 5159 /*! FTM0PS0 - FTM0_CH0 Port Pin Select 5160 * 0b0..FTM0_CH0 channels are mapped on PTA0. 5161 * 0b1..FTM0_CH0 channels are mapped on PTB2. 5162 */ 5163 #define SIM_PINSEL_FTM0PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM0PS0_SHIFT)) & SIM_PINSEL_FTM0PS0_MASK) 5164 #define SIM_PINSEL_FTM0PS1_MASK (0x200U) 5165 #define SIM_PINSEL_FTM0PS1_SHIFT (9U) 5166 /*! FTM0PS1 - FTM0_CH1 Port Pin Select 5167 * 0b0..FTM0_CH1 channels are mapped on PTA1. 5168 * 0b1..FTM0_CH1 channels are mapped on PTB3. 5169 */ 5170 #define SIM_PINSEL_FTM0PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM0PS1_SHIFT)) & SIM_PINSEL_FTM0PS1_MASK) 5171 #define SIM_PINSEL_FTM1PS0_MASK (0x400U) 5172 #define SIM_PINSEL_FTM1PS0_SHIFT (10U) 5173 /*! FTM1PS0 - FTM1_CH0 Port Pin Select 5174 * 0b0..FTM1_CH0 channels are mapped on PTC4. 5175 * 0b1..FTM1_CH0 channels are mapped on PTH2. 5176 */ 5177 #define SIM_PINSEL_FTM1PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM1PS0_SHIFT)) & SIM_PINSEL_FTM1PS0_MASK) 5178 #define SIM_PINSEL_FTM1PS1_MASK (0x800U) 5179 #define SIM_PINSEL_FTM1PS1_SHIFT (11U) 5180 /*! FTM1PS1 - FTM1_CH1 Port Pin Select 5181 * 0b0..FTM1_CH1 channels are mapped on PTC5. 5182 * 0b1..FTM1_CH1 channels are mapped on PTE7. 5183 */ 5184 #define SIM_PINSEL_FTM1PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM1PS1_SHIFT)) & SIM_PINSEL_FTM1PS1_MASK) 5185 #define SIM_PINSEL_FTM2PS0_MASK (0x1000U) 5186 #define SIM_PINSEL_FTM2PS0_SHIFT (12U) 5187 /*! FTM2PS0 - FTM2_CH0 Port Pin Select 5188 * 0b0..FTM2_CH0 channels are mapped on PTC0. 5189 * 0b1..FTM2_CH0 channels are mapped on PTH0. 5190 */ 5191 #define SIM_PINSEL_FTM2PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2PS0_SHIFT)) & SIM_PINSEL_FTM2PS0_MASK) 5192 #define SIM_PINSEL_FTM2PS1_MASK (0x2000U) 5193 #define SIM_PINSEL_FTM2PS1_SHIFT (13U) 5194 /*! FTM2PS1 - FTM2_CH1 Port Pin Select 5195 * 0b0..FTM2_CH1 channels are mapped on PTC1. 5196 * 0b1..FTM2_CH1 channels are mapped on PTH1. 5197 */ 5198 #define SIM_PINSEL_FTM2PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2PS1_SHIFT)) & SIM_PINSEL_FTM2PS1_MASK) 5199 #define SIM_PINSEL_FTM2PS2_MASK (0x4000U) 5200 #define SIM_PINSEL_FTM2PS2_SHIFT (14U) 5201 /*! FTM2PS2 - FTM2_CH2 Port Pin Select 5202 * 0b0..FTM2_CH2 channels are mapped on PTC2. 5203 * 0b1..FTM2_CH2 channels are mapped on PTD0. 5204 */ 5205 #define SIM_PINSEL_FTM2PS2(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2PS2_SHIFT)) & SIM_PINSEL_FTM2PS2_MASK) 5206 #define SIM_PINSEL_FTM2PS3_MASK (0x8000U) 5207 #define SIM_PINSEL_FTM2PS3_SHIFT (15U) 5208 /*! FTM2PS3 - FTM2_CH3 Port Pin Select 5209 * 0b0..FTM2_CH3 channels are mapped on PTC3. 5210 * 0b1..FTM2_CH3 channels are mapped on PTD1. 5211 */ 5212 #define SIM_PINSEL_FTM2PS3(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL_FTM2PS3_SHIFT)) & SIM_PINSEL_FTM2PS3_MASK) 5213 /*! @} */ 5214 5215 /*! @name SCGC - System Clock Gating Control Register */ 5216 /*! @{ */ 5217 #define SIM_SCGC_RTC_MASK (0x1U) 5218 #define SIM_SCGC_RTC_SHIFT (0U) 5219 /*! RTC - RTC Clock Gate Control 5220 * 0b0..Bus clock to the RTC module is disabled. 5221 * 0b1..Bus clock to the RTC module is enabled. 5222 */ 5223 #define SIM_SCGC_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_RTC_SHIFT)) & SIM_SCGC_RTC_MASK) 5224 #define SIM_SCGC_PIT_MASK (0x2U) 5225 #define SIM_SCGC_PIT_SHIFT (1U) 5226 /*! PIT - PIT Clock Gate Control 5227 * 0b0..Bus clock to the PIT module is disabled. 5228 * 0b1..Bus clock to the PIT module is enabled. 5229 */ 5230 #define SIM_SCGC_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_PIT_SHIFT)) & SIM_SCGC_PIT_MASK) 5231 #define SIM_SCGC_FTM0_MASK (0x20U) 5232 #define SIM_SCGC_FTM0_SHIFT (5U) 5233 /*! FTM0 - FTM0 Clock Gate Control 5234 * 0b0..Bus clock to the FTM0 module is disabled. 5235 * 0b1..Bus clock to the FTM0 module is enabled. 5236 */ 5237 #define SIM_SCGC_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM0_SHIFT)) & SIM_SCGC_FTM0_MASK) 5238 #define SIM_SCGC_FTM1_MASK (0x40U) 5239 #define SIM_SCGC_FTM1_SHIFT (6U) 5240 /*! FTM1 - FTM1 Clock Gate Control 5241 * 0b0..Bus clock to the FTM1 module is disabled. 5242 * 0b1..Bus clock to the FTM1 module is enabled. 5243 */ 5244 #define SIM_SCGC_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM1_SHIFT)) & SIM_SCGC_FTM1_MASK) 5245 #define SIM_SCGC_FTM2_MASK (0x80U) 5246 #define SIM_SCGC_FTM2_SHIFT (7U) 5247 /*! FTM2 - FTM2 Clock Gate Control 5248 * 0b0..Bus clock to the FTM2 module is disabled. 5249 * 0b1..Bus clock to the FTM2 module is enabled. 5250 */ 5251 #define SIM_SCGC_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM2_SHIFT)) & SIM_SCGC_FTM2_MASK) 5252 #define SIM_SCGC_CRC_MASK (0x400U) 5253 #define SIM_SCGC_CRC_SHIFT (10U) 5254 /*! CRC - CRC Clock Gate Control 5255 * 0b0..Bus clock to the CRC module is disabled. 5256 * 0b1..Bus clock to the CRC module is enabled. 5257 */ 5258 #define SIM_SCGC_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_CRC_SHIFT)) & SIM_SCGC_CRC_MASK) 5259 #define SIM_SCGC_FLASH_MASK (0x1000U) 5260 #define SIM_SCGC_FLASH_SHIFT (12U) 5261 /*! FLASH - Flash Clock Gate Control 5262 * 0b0..Bus clock to the flash module is disabled. 5263 * 0b1..Bus clock to the flash module is enabled. 5264 */ 5265 #define SIM_SCGC_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FLASH_SHIFT)) & SIM_SCGC_FLASH_MASK) 5266 #define SIM_SCGC_SWD_MASK (0x2000U) 5267 #define SIM_SCGC_SWD_SHIFT (13U) 5268 /*! SWD - SWD (single wire debugger) Clock Gate Control 5269 * 0b0..Bus clock to the SWD module is disabled. 5270 * 0b1..Bus clock to the SWD module is enabled. 5271 */ 5272 #define SIM_SCGC_SWD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SWD_SHIFT)) & SIM_SCGC_SWD_MASK) 5273 #define SIM_SCGC_I2C_MASK (0x20000U) 5274 #define SIM_SCGC_I2C_SHIFT (17U) 5275 /*! I2C - I2C Clock Gate Control 5276 * 0b0..Bus clock to the IIC module is disabled. 5277 * 0b1..Bus clock to the IIC module is enabled. 5278 */ 5279 #define SIM_SCGC_I2C(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_I2C_SHIFT)) & SIM_SCGC_I2C_MASK) 5280 #define SIM_SCGC_SPI0_MASK (0x40000U) 5281 #define SIM_SCGC_SPI0_SHIFT (18U) 5282 /*! SPI0 - SPI0 Clock Gate Control 5283 * 0b0..Bus clock to the SPI0 module is disabled. 5284 * 0b1..Bus clock to the SPI0 module is enabled. 5285 */ 5286 #define SIM_SCGC_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SPI0_SHIFT)) & SIM_SCGC_SPI0_MASK) 5287 #define SIM_SCGC_SPI1_MASK (0x80000U) 5288 #define SIM_SCGC_SPI1_SHIFT (19U) 5289 /*! SPI1 - SPI1 Clock Gate Control 5290 * 0b0..Bus clock to the SPI1 module is disabled. 5291 * 0b1..Bus clock to the SPI1 module is enabled. 5292 */ 5293 #define SIM_SCGC_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SPI1_SHIFT)) & SIM_SCGC_SPI1_MASK) 5294 #define SIM_SCGC_UART0_MASK (0x100000U) 5295 #define SIM_SCGC_UART0_SHIFT (20U) 5296 /*! UART0 - UART0 Clock Gate Control 5297 * 0b0..Bus clock to the UART0 module is disabled. 5298 * 0b1..Bus clock to the UART0 module is enabled. 5299 */ 5300 #define SIM_SCGC_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART0_SHIFT)) & SIM_SCGC_UART0_MASK) 5301 #define SIM_SCGC_UART1_MASK (0x200000U) 5302 #define SIM_SCGC_UART1_SHIFT (21U) 5303 /*! UART1 - UART1 Clock Gate Control 5304 * 0b0..Bus clock to the UART1 module is disabled. 5305 * 0b1..Bus clock to the UART1 module is enabled. 5306 */ 5307 #define SIM_SCGC_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART1_SHIFT)) & SIM_SCGC_UART1_MASK) 5308 #define SIM_SCGC_UART2_MASK (0x400000U) 5309 #define SIM_SCGC_UART2_SHIFT (22U) 5310 /*! UART2 - UART2 Clock Gate Control 5311 * 0b0..Bus clock to the UART2 module is disabled. 5312 * 0b1..Bus clock to the UART2 module is enabled. 5313 */ 5314 #define SIM_SCGC_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART2_SHIFT)) & SIM_SCGC_UART2_MASK) 5315 #define SIM_SCGC_KBI0_MASK (0x1000000U) 5316 #define SIM_SCGC_KBI0_SHIFT (24U) 5317 /*! KBI0 - KBI0 Clock Gate Control 5318 * 0b0..Bus clock to the KBI0 module is disabled. 5319 * 0b1..Bus clock to the KBI0 module is enabled. 5320 */ 5321 #define SIM_SCGC_KBI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_KBI0_SHIFT)) & SIM_SCGC_KBI0_MASK) 5322 #define SIM_SCGC_KBI1_MASK (0x2000000U) 5323 #define SIM_SCGC_KBI1_SHIFT (25U) 5324 /*! KBI1 - KBI1 Clock Gate Control 5325 * 0b0..Bus clock to the KBI1 module is disabled. 5326 * 0b1..Bus clock to the KBI1 module is enabled. 5327 */ 5328 #define SIM_SCGC_KBI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_KBI1_SHIFT)) & SIM_SCGC_KBI1_MASK) 5329 #define SIM_SCGC_IRQ_MASK (0x8000000U) 5330 #define SIM_SCGC_IRQ_SHIFT (27U) 5331 /*! IRQ - IRQ Clock Gate Control 5332 * 0b0..Bus clock to the IRQ module is disabled. 5333 * 0b1..Bus clock to the IRQ module is enabled. 5334 */ 5335 #define SIM_SCGC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_IRQ_SHIFT)) & SIM_SCGC_IRQ_MASK) 5336 #define SIM_SCGC_ADC_MASK (0x20000000U) 5337 #define SIM_SCGC_ADC_SHIFT (29U) 5338 /*! ADC - ADC Clock Gate Control 5339 * 0b0..Bus clock to the ADC module is disabled. 5340 * 0b1..Bus clock to the ADC module is enabled. 5341 */ 5342 #define SIM_SCGC_ADC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ADC_SHIFT)) & SIM_SCGC_ADC_MASK) 5343 #define SIM_SCGC_ACMP0_MASK (0x40000000U) 5344 #define SIM_SCGC_ACMP0_SHIFT (30U) 5345 /*! ACMP0 - ACMP0 Clock Gate Control 5346 * 0b0..Bus clock to the ACMP0 module is disabled. 5347 * 0b1..Bus clock to the ACMP0 module is enabled. 5348 */ 5349 #define SIM_SCGC_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ACMP0_SHIFT)) & SIM_SCGC_ACMP0_MASK) 5350 #define SIM_SCGC_ACMP1_MASK (0x80000000U) 5351 #define SIM_SCGC_ACMP1_SHIFT (31U) 5352 /*! ACMP1 - ACMP1 Clock Gate Control 5353 * 0b0..Bus clock to the ACMP1 module is disabled. 5354 * 0b1..Bus clock to the ACMP1 module is enabled. 5355 */ 5356 #define SIM_SCGC_ACMP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ACMP1_SHIFT)) & SIM_SCGC_ACMP1_MASK) 5357 /*! @} */ 5358 5359 /*! @name UUIDL - Universally Unique Identifier Low Register */ 5360 /*! @{ */ 5361 #define SIM_UUIDL_ID_MASK (0xFFFFFFFFU) 5362 #define SIM_UUIDL_ID_SHIFT (0U) 5363 #define SIM_UUIDL_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDL_ID_SHIFT)) & SIM_UUIDL_ID_MASK) 5364 /*! @} */ 5365 5366 /*! @name UUIDH - Universally Unique Identifier High Register */ 5367 /*! @{ */ 5368 #define SIM_UUIDH_ID_MASK (0xFFFFFFFFU) 5369 #define SIM_UUIDH_ID_SHIFT (0U) 5370 #define SIM_UUIDH_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDH_ID_SHIFT)) & SIM_UUIDH_ID_MASK) 5371 /*! @} */ 5372 5373 /*! @name BUSDIV - BUS Clock Divider Register */ 5374 /*! @{ */ 5375 #define SIM_BUSDIV_BUSDIV_MASK (0x1U) 5376 #define SIM_BUSDIV_BUSDIV_SHIFT (0U) 5377 /*! BUSDIV - BUS Clock Divider 5378 * 0b0..Bus clock is same as ICSOUTCLK. 5379 * 0b1..Bus clock is ICSOUTCLK divided by 2. 5380 */ 5381 #define SIM_BUSDIV_BUSDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_BUSDIV_BUSDIV_SHIFT)) & SIM_BUSDIV_BUSDIV_MASK) 5382 /*! @} */ 5383 5384 5385 /*! 5386 * @} 5387 */ /* end of group SIM_Register_Masks */ 5388 5389 5390 /* SIM - Peripheral instance base addresses */ 5391 /** Peripheral SIM base address */ 5392 #define SIM_BASE (0x40048000u) 5393 /** Peripheral SIM base pointer */ 5394 #define SIM ((SIM_Type *)SIM_BASE) 5395 /** Array initializer of SIM peripheral base addresses */ 5396 #define SIM_BASE_ADDRS { SIM_BASE } 5397 /** Array initializer of SIM peripheral base pointers */ 5398 #define SIM_BASE_PTRS { SIM } 5399 5400 /*! 5401 * @} 5402 */ /* end of group SIM_Peripheral_Access_Layer */ 5403 5404 5405 /* ---------------------------------------------------------------------------- 5406 -- SPI Peripheral Access Layer 5407 ---------------------------------------------------------------------------- */ 5408 5409 /*! 5410 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 5411 * @{ 5412 */ 5413 5414 /** SPI - Register Layout Typedef */ 5415 typedef struct { 5416 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x0 */ 5417 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x1 */ 5418 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x2 */ 5419 __IO uint8_t S; /**< SPI Status Register, offset: 0x3 */ 5420 uint8_t RESERVED_0[1]; 5421 __IO uint8_t D; /**< SPI Data Register, offset: 0x5 */ 5422 uint8_t RESERVED_1[1]; 5423 __IO uint8_t M; /**< SPI Match Register, offset: 0x7 */ 5424 } SPI_Type; 5425 5426 /* ---------------------------------------------------------------------------- 5427 -- SPI Register Masks 5428 ---------------------------------------------------------------------------- */ 5429 5430 /*! 5431 * @addtogroup SPI_Register_Masks SPI Register Masks 5432 * @{ 5433 */ 5434 5435 /*! @name C1 - SPI Control Register 1 */ 5436 /*! @{ */ 5437 #define SPI_C1_LSBFE_MASK (0x1U) 5438 #define SPI_C1_LSBFE_SHIFT (0U) 5439 /*! LSBFE - LSB First (shifter direction) 5440 * 0b0..SPI serial data transfers start with the most significant bit. 5441 * 0b1..SPI serial data transfers start with the least significant bit. 5442 */ 5443 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 5444 #define SPI_C1_SSOE_MASK (0x2U) 5445 #define SPI_C1_SSOE_SHIFT (1U) 5446 /*! SSOE - Slave Select Output Enable 5447 * 0b0..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. 5448 * 0b1..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. 5449 */ 5450 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 5451 #define SPI_C1_CPHA_MASK (0x4U) 5452 #define SPI_C1_CPHA_SHIFT (2U) 5453 /*! CPHA - Clock Phase 5454 * 0b0..First edge on SPSCK occurs at the middle of the first cycle of a data transfer. 5455 * 0b1..First edge on SPSCK occurs at the start of the first cycle of a data transfer. 5456 */ 5457 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 5458 #define SPI_C1_CPOL_MASK (0x8U) 5459 #define SPI_C1_CPOL_SHIFT (3U) 5460 /*! CPOL - Clock Polarity 5461 * 0b0..Active-high SPI clock (idles low) 5462 * 0b1..Active-low SPI clock (idles high) 5463 */ 5464 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 5465 #define SPI_C1_MSTR_MASK (0x10U) 5466 #define SPI_C1_MSTR_SHIFT (4U) 5467 /*! MSTR - Master/Slave Mode Select 5468 * 0b0..SPI module configured as a slave SPI device 5469 * 0b1..SPI module configured as a master SPI device 5470 */ 5471 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 5472 #define SPI_C1_SPTIE_MASK (0x20U) 5473 #define SPI_C1_SPTIE_SHIFT (5U) 5474 /*! SPTIE - SPI Transmit Interrupt Enable 5475 * 0b0..Interrupts from SPTEF inhibited (use polling) 5476 * 0b1..When SPTEF is 1, hardware interrupt requested 5477 */ 5478 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 5479 #define SPI_C1_SPE_MASK (0x40U) 5480 #define SPI_C1_SPE_SHIFT (6U) 5481 /*! SPE - SPI System Enable 5482 * 0b0..SPI system inactive 5483 * 0b1..SPI system enabled 5484 */ 5485 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 5486 #define SPI_C1_SPIE_MASK (0x80U) 5487 #define SPI_C1_SPIE_SHIFT (7U) 5488 /*! SPIE - SPI Interrupt Enable: for SPRF and MODF 5489 * 0b0..Interrupts from SPRF and MODF are inhibited-use polling 5490 * 0b1..Request a hardware interrupt when SPRF or MODF is 1 5491 */ 5492 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 5493 /*! @} */ 5494 5495 /*! @name C2 - SPI Control Register 2 */ 5496 /*! @{ */ 5497 #define SPI_C2_SPC0_MASK (0x1U) 5498 #define SPI_C2_SPC0_SHIFT (0U) 5499 /*! SPC0 - SPI Pin Control 0 5500 * 0b0..SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. 5501 * 0b1..SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. 5502 */ 5503 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 5504 #define SPI_C2_SPISWAI_MASK (0x2U) 5505 #define SPI_C2_SPISWAI_SHIFT (1U) 5506 /*! SPISWAI - SPI Stop in Wait Mode 5507 * 0b0..SPI clocks continue to operate in Wait mode. 5508 * 0b1..SPI clocks stop when the MCU enters Wait mode. 5509 */ 5510 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 5511 #define SPI_C2_BIDIROE_MASK (0x8U) 5512 #define SPI_C2_BIDIROE_SHIFT (3U) 5513 /*! BIDIROE - Bidirectional Mode Output Enable 5514 * 0b0..Output driver disabled so SPI data I/O pin acts as an input 5515 * 0b1..SPI I/O pin enabled as an output 5516 */ 5517 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 5518 #define SPI_C2_MODFEN_MASK (0x10U) 5519 #define SPI_C2_MODFEN_SHIFT (4U) 5520 /*! MODFEN - Master Mode-Fault Function Enable 5521 * 0b0..Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 5522 * 0b1..Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output 5523 */ 5524 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 5525 #define SPI_C2_SPMIE_MASK (0x80U) 5526 #define SPI_C2_SPMIE_SHIFT (7U) 5527 /*! SPMIE - SPI Match Interrupt Enable 5528 * 0b0..Interrupts from SPMF inhibited (use polling) 5529 * 0b1..When SPMF is 1, requests a hardware interrupt 5530 */ 5531 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 5532 /*! @} */ 5533 5534 /*! @name BR - SPI Baud Rate Register */ 5535 /*! @{ */ 5536 #define SPI_BR_SPR_MASK (0xFU) 5537 #define SPI_BR_SPR_SHIFT (0U) 5538 /*! SPR - SPI Baud Rate Divisor 5539 * 0b0000..Baud rate divisor is 2. 5540 * 0b0001..Baud rate divisor is 4. 5541 * 0b0010..Baud rate divisor is 8. 5542 * 0b0011..Baud rate divisor is 16. 5543 * 0b0100..Baud rate divisor is 32. 5544 * 0b0101..Baud rate divisor is 64. 5545 * 0b0110..Baud rate divisor is 128. 5546 * 0b0111..Baud rate divisor is 256. 5547 * 0b1000..Baud rate divisor is 512. 5548 */ 5549 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 5550 #define SPI_BR_SPPR_MASK (0x70U) 5551 #define SPI_BR_SPPR_SHIFT (4U) 5552 /*! SPPR - SPI Baud Rate Prescale Divisor 5553 * 0b000..Baud rate prescaler divisor is 1. 5554 * 0b001..Baud rate prescaler divisor is 2. 5555 * 0b010..Baud rate prescaler divisor is 3. 5556 * 0b011..Baud rate prescaler divisor is 4. 5557 * 0b100..Baud rate prescaler divisor is 5. 5558 * 0b101..Baud rate prescaler divisor is 6. 5559 * 0b110..Baud rate prescaler divisor is 7. 5560 * 0b111..Baud rate prescaler divisor is 8. 5561 */ 5562 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 5563 /*! @} */ 5564 5565 /*! @name S - SPI Status Register */ 5566 /*! @{ */ 5567 #define SPI_S_MODF_MASK (0x10U) 5568 #define SPI_S_MODF_SHIFT (4U) 5569 /*! MODF - Master Mode Fault Flag 5570 * 0b0..No mode fault error 5571 * 0b1..Mode fault error detected 5572 */ 5573 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 5574 #define SPI_S_SPTEF_MASK (0x20U) 5575 #define SPI_S_SPTEF_SHIFT (5U) 5576 /*! SPTEF - SPI Transmit Buffer Empty Flag 5577 * 0b0..SPI transmit buffer not empty 5578 * 0b1..SPI transmit buffer empty 5579 */ 5580 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 5581 #define SPI_S_SPMF_MASK (0x40U) 5582 #define SPI_S_SPMF_SHIFT (6U) 5583 /*! SPMF - SPI Match Flag 5584 * 0b0..Value in the receive data buffer does not match the value in the M register 5585 * 0b1..Value in the receive data buffer matches the value in the M register 5586 */ 5587 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 5588 #define SPI_S_SPRF_MASK (0x80U) 5589 #define SPI_S_SPRF_SHIFT (7U) 5590 /*! SPRF - SPI Read Buffer Full Flag 5591 * 0b0..No data available in the receive data buffer 5592 * 0b1..Data available in the receive data buffer 5593 */ 5594 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 5595 /*! @} */ 5596 5597 /*! @name D - SPI Data Register */ 5598 /*! @{ */ 5599 #define SPI_D_Bits_MASK (0xFFU) 5600 #define SPI_D_Bits_SHIFT (0U) 5601 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_D_Bits_SHIFT)) & SPI_D_Bits_MASK) 5602 /*! @} */ 5603 5604 /*! @name M - SPI Match Register */ 5605 /*! @{ */ 5606 #define SPI_M_Bits_MASK (0xFFU) 5607 #define SPI_M_Bits_SHIFT (0U) 5608 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_M_Bits_SHIFT)) & SPI_M_Bits_MASK) 5609 /*! @} */ 5610 5611 5612 /*! 5613 * @} 5614 */ /* end of group SPI_Register_Masks */ 5615 5616 5617 /* SPI - Peripheral instance base addresses */ 5618 /** Peripheral SPI0 base address */ 5619 #define SPI0_BASE (0x40076000u) 5620 /** Peripheral SPI0 base pointer */ 5621 #define SPI0 ((SPI_Type *)SPI0_BASE) 5622 /** Peripheral SPI1 base address */ 5623 #define SPI1_BASE (0x40077000u) 5624 /** Peripheral SPI1 base pointer */ 5625 #define SPI1 ((SPI_Type *)SPI1_BASE) 5626 /** Array initializer of SPI peripheral base addresses */ 5627 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } 5628 /** Array initializer of SPI peripheral base pointers */ 5629 #define SPI_BASE_PTRS { SPI0, SPI1 } 5630 /** Interrupt vectors for the SPI peripheral type */ 5631 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } 5632 5633 /*! 5634 * @} 5635 */ /* end of group SPI_Peripheral_Access_Layer */ 5636 5637 5638 /* ---------------------------------------------------------------------------- 5639 -- UART Peripheral Access Layer 5640 ---------------------------------------------------------------------------- */ 5641 5642 /*! 5643 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 5644 * @{ 5645 */ 5646 5647 /** UART - Register Layout Typedef */ 5648 typedef struct { 5649 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 5650 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 5651 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 5652 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 5653 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 5654 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 5655 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 5656 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 5657 } UART_Type; 5658 5659 /* ---------------------------------------------------------------------------- 5660 -- UART Register Masks 5661 ---------------------------------------------------------------------------- */ 5662 5663 /*! 5664 * @addtogroup UART_Register_Masks UART Register Masks 5665 * @{ 5666 */ 5667 5668 /*! @name BDH - UART Baud Rate Register: High */ 5669 /*! @{ */ 5670 #define UART_BDH_SBR_MASK (0x1FU) 5671 #define UART_BDH_SBR_SHIFT (0U) 5672 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 5673 #define UART_BDH_SBNS_MASK (0x20U) 5674 #define UART_BDH_SBNS_SHIFT (5U) 5675 /*! SBNS - Stop Bit Number Select 5676 * 0b0..One stop bit. 5677 * 0b1..Two stop bit. 5678 */ 5679 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) 5680 #define UART_BDH_RXEDGIE_MASK (0x40U) 5681 #define UART_BDH_RXEDGIE_SHIFT (6U) 5682 /*! RXEDGIE - RxD Input Active Edge Interrupt Enable (for RXEDGIF) 5683 * 0b0..Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). 5684 * 0b1..Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. 5685 */ 5686 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 5687 #define UART_BDH_LBKDIE_MASK (0x80U) 5688 #define UART_BDH_LBKDIE_SHIFT (7U) 5689 /*! LBKDIE - LIN Break Detect Interrupt Enable (for LBKDIF) 5690 * 0b0..Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). 5691 * 0b1..Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. 5692 */ 5693 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 5694 /*! @} */ 5695 5696 /*! @name BDL - UART Baud Rate Register: Low */ 5697 /*! @{ */ 5698 #define UART_BDL_SBR_MASK (0xFFU) 5699 #define UART_BDL_SBR_SHIFT (0U) 5700 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 5701 /*! @} */ 5702 5703 /*! @name C1 - UART Control Register 1 */ 5704 /*! @{ */ 5705 #define UART_C1_PT_MASK (0x1U) 5706 #define UART_C1_PT_SHIFT (0U) 5707 /*! PT - Parity Type 5708 * 0b0..Even parity. 5709 * 0b1..Odd parity. 5710 */ 5711 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 5712 #define UART_C1_PE_MASK (0x2U) 5713 #define UART_C1_PE_SHIFT (1U) 5714 /*! PE - Parity Enable 5715 * 0b0..No hardware parity generation or checking. 5716 * 0b1..Parity enabled. 5717 */ 5718 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 5719 #define UART_C1_ILT_MASK (0x4U) 5720 #define UART_C1_ILT_SHIFT (2U) 5721 /*! ILT - Idle Line Type Select 5722 * 0b0..Idle character bit count starts after start bit. 5723 * 0b1..Idle character bit count starts after stop bit. 5724 */ 5725 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 5726 #define UART_C1_WAKE_MASK (0x8U) 5727 #define UART_C1_WAKE_SHIFT (3U) 5728 /*! WAKE - Receiver Wakeup Method Select 5729 * 0b0..Idle-line wake-up. 5730 * 0b1..Address-mark wake-up. 5731 */ 5732 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 5733 #define UART_C1_M_MASK (0x10U) 5734 #define UART_C1_M_SHIFT (4U) 5735 /*! M - 9-Bit or 8-Bit Mode Select 5736 * 0b0..Normal - start + 8 data bits (lsb first) + stop. 5737 * 0b1..Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. 5738 */ 5739 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 5740 #define UART_C1_RSRC_MASK (0x20U) 5741 #define UART_C1_RSRC_SHIFT (5U) 5742 /*! RSRC - Receiver Source Select 5743 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. 5744 * 0b1..Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. 5745 */ 5746 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 5747 #define UART_C1_UARTSWAI_MASK (0x40U) 5748 #define UART_C1_UARTSWAI_SHIFT (6U) 5749 /*! UARTSWAI - UART Stops in Wait Mode 5750 * 0b0..UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU. 5751 * 0b1..UART clocks freeze while CPU is in Wait mode. 5752 */ 5753 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 5754 #define UART_C1_LOOPS_MASK (0x80U) 5755 #define UART_C1_LOOPS_SHIFT (7U) 5756 /*! LOOPS - Loop Mode Select 5757 * 0b0..Normal operation - RxD and TxD use separate pins. 5758 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. 5759 */ 5760 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 5761 /*! @} */ 5762 5763 /*! @name C2 - UART Control Register 2 */ 5764 /*! @{ */ 5765 #define UART_C2_SBK_MASK (0x1U) 5766 #define UART_C2_SBK_SHIFT (0U) 5767 /*! SBK - Send Break 5768 * 0b0..Normal transmitter operation. 5769 * 0b1..Queue break character(s) to be sent. 5770 */ 5771 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 5772 #define UART_C2_RWU_MASK (0x2U) 5773 #define UART_C2_RWU_SHIFT (1U) 5774 /*! RWU - Receiver Wakeup Control 5775 * 0b0..Normal UART receiver operation. 5776 * 0b1..UART receiver in standby waiting for wake-up condition. 5777 */ 5778 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 5779 #define UART_C2_RE_MASK (0x4U) 5780 #define UART_C2_RE_SHIFT (2U) 5781 /*! RE - Receiver Enable 5782 * 0b0..Receiver off. 5783 * 0b1..Receiver on. 5784 */ 5785 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 5786 #define UART_C2_TE_MASK (0x8U) 5787 #define UART_C2_TE_SHIFT (3U) 5788 /*! TE - Transmitter Enable 5789 * 0b0..Transmitter off. 5790 * 0b1..Transmitter on. 5791 */ 5792 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 5793 #define UART_C2_ILIE_MASK (0x10U) 5794 #define UART_C2_ILIE_SHIFT (4U) 5795 /*! ILIE - Idle Line Interrupt Enable for IDLE 5796 * 0b0..Hardware interrupts from S1[IDLE] disabled; use polling. 5797 * 0b1..Hardware interrupt requested when S1[IDLE] flag is 1. 5798 */ 5799 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 5800 #define UART_C2_RIE_MASK (0x20U) 5801 #define UART_C2_RIE_SHIFT (5U) 5802 /*! RIE - Receiver Interrupt Enable for RDRF 5803 * 0b0..Hardware interrupts from S1[RDRF] disabled; use polling. 5804 * 0b1..Hardware interrupt requested when S1[RDRF] flag is 1. 5805 */ 5806 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 5807 #define UART_C2_TCIE_MASK (0x40U) 5808 #define UART_C2_TCIE_SHIFT (6U) 5809 /*! TCIE - Transmission Complete Interrupt Enable for TC 5810 * 0b0..Hardware interrupts from TC disabled; use polling. 5811 * 0b1..Hardware interrupt requested when TC flag is 1. 5812 */ 5813 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 5814 #define UART_C2_TIE_MASK (0x80U) 5815 #define UART_C2_TIE_SHIFT (7U) 5816 /*! TIE - Transmit Interrupt Enable for TDRE 5817 * 0b0..Hardware interrupts from TDRE disabled; use polling. 5818 * 0b1..Hardware interrupt requested when TDRE flag is 1. 5819 */ 5820 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 5821 /*! @} */ 5822 5823 /*! @name S1 - UART Status Register 1 */ 5824 /*! @{ */ 5825 #define UART_S1_PF_MASK (0x1U) 5826 #define UART_S1_PF_SHIFT (0U) 5827 /*! PF - Parity Error Flag 5828 * 0b0..No parity error. 5829 * 0b1..Parity error. 5830 */ 5831 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 5832 #define UART_S1_FE_MASK (0x2U) 5833 #define UART_S1_FE_SHIFT (1U) 5834 /*! FE - Framing Error Flag 5835 * 0b0..No framing error detected. This does not guarantee the framing is correct. 5836 * 0b1..Framing error. 5837 */ 5838 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 5839 #define UART_S1_NF_MASK (0x4U) 5840 #define UART_S1_NF_SHIFT (2U) 5841 /*! NF - Noise Flag 5842 * 0b0..No noise detected. 5843 * 0b1..Noise detected in the received character in UART_D. 5844 */ 5845 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 5846 #define UART_S1_OR_MASK (0x8U) 5847 #define UART_S1_OR_SHIFT (3U) 5848 /*! OR - Receiver Overrun Flag 5849 * 0b0..No overrun. 5850 * 0b1..Receive overrun (new UART data lost). 5851 */ 5852 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 5853 #define UART_S1_IDLE_MASK (0x10U) 5854 #define UART_S1_IDLE_SHIFT (4U) 5855 /*! IDLE - Idle Line Flag 5856 * 0b0..No idle line detected. 5857 * 0b1..Idle line was detected. 5858 */ 5859 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 5860 #define UART_S1_RDRF_MASK (0x20U) 5861 #define UART_S1_RDRF_SHIFT (5U) 5862 /*! RDRF - Receive Data Register Full Flag 5863 * 0b0..Receive data register empty. 5864 * 0b1..Receive data register full. 5865 */ 5866 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 5867 #define UART_S1_TC_MASK (0x40U) 5868 #define UART_S1_TC_SHIFT (6U) 5869 /*! TC - Transmission Complete Flag 5870 * 0b0..Transmitter active (sending data, a preamble, or a break). 5871 * 0b1..Transmitter idle (transmission activity complete). 5872 */ 5873 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 5874 #define UART_S1_TDRE_MASK (0x80U) 5875 #define UART_S1_TDRE_SHIFT (7U) 5876 /*! TDRE - Transmit Data Register Empty Flag 5877 * 0b0..Transmit data register (buffer) full. 5878 * 0b1..Transmit data register (buffer) empty. 5879 */ 5880 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 5881 /*! @} */ 5882 5883 /*! @name S2 - UART Status Register 2 */ 5884 /*! @{ */ 5885 #define UART_S2_RAF_MASK (0x1U) 5886 #define UART_S2_RAF_SHIFT (0U) 5887 /*! RAF - Receiver Active Flag 5888 * 0b0..UART receiver idle waiting for a start bit. 5889 * 0b1..UART receiver active (RxD input not idle). 5890 */ 5891 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 5892 #define UART_S2_LBKDE_MASK (0x2U) 5893 #define UART_S2_LBKDE_SHIFT (1U) 5894 /*! LBKDE - LIN Break Detection Enable 5895 * 0b0..Break detection is disabled. 5896 * 0b1..Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)). 5897 */ 5898 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 5899 #define UART_S2_BRK13_MASK (0x4U) 5900 #define UART_S2_BRK13_SHIFT (2U) 5901 /*! BRK13 - Break Character Generation Length 5902 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). 5903 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). 5904 */ 5905 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 5906 #define UART_S2_RWUID_MASK (0x8U) 5907 #define UART_S2_RWUID_SHIFT (3U) 5908 /*! RWUID - Receive Wake Up Idle Detect 5909 * 0b0..During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character. 5910 * 0b1..During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character. 5911 */ 5912 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 5913 #define UART_S2_RXINV_MASK (0x10U) 5914 #define UART_S2_RXINV_SHIFT (4U) 5915 /*! RXINV - Receive Data Inversion 5916 * 0b0..Receive data not inverted. 5917 * 0b1..Receive data inverted. 5918 */ 5919 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 5920 #define UART_S2_RXEDGIF_MASK (0x40U) 5921 #define UART_S2_RXEDGIF_SHIFT (6U) 5922 /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag 5923 * 0b0..No active edge on the receive pin has occurred. 5924 * 0b1..An active edge on the receive pin has occurred. 5925 */ 5926 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 5927 #define UART_S2_LBKDIF_MASK (0x80U) 5928 #define UART_S2_LBKDIF_SHIFT (7U) 5929 /*! LBKDIF - LIN Break Detect Interrupt Flag 5930 * 0b0..No LIN break character has been detected. 5931 * 0b1..LIN break character has been detected. 5932 */ 5933 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 5934 /*! @} */ 5935 5936 /*! @name C3 - UART Control Register 3 */ 5937 /*! @{ */ 5938 #define UART_C3_PEIE_MASK (0x1U) 5939 #define UART_C3_PEIE_SHIFT (0U) 5940 /*! PEIE - Parity Error Interrupt Enable 5941 * 0b0..PF interrupts disabled; use polling). 5942 * 0b1..Hardware interrupt requested when PF is set. 5943 */ 5944 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 5945 #define UART_C3_FEIE_MASK (0x2U) 5946 #define UART_C3_FEIE_SHIFT (1U) 5947 /*! FEIE - Framing Error Interrupt Enable 5948 * 0b0..FE interrupts disabled; use polling). 5949 * 0b1..Hardware interrupt requested when FE is set. 5950 */ 5951 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 5952 #define UART_C3_NEIE_MASK (0x4U) 5953 #define UART_C3_NEIE_SHIFT (2U) 5954 /*! NEIE - Noise Error Interrupt Enable 5955 * 0b0..NF interrupts disabled; use polling). 5956 * 0b1..Hardware interrupt requested when NF is set. 5957 */ 5958 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 5959 #define UART_C3_ORIE_MASK (0x8U) 5960 #define UART_C3_ORIE_SHIFT (3U) 5961 /*! ORIE - Overrun Interrupt Enable 5962 * 0b0..OR interrupts disabled; use polling. 5963 * 0b1..Hardware interrupt requested when OR is set. 5964 */ 5965 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 5966 #define UART_C3_TXINV_MASK (0x10U) 5967 #define UART_C3_TXINV_SHIFT (4U) 5968 /*! TXINV - Transmit Data Inversion 5969 * 0b0..Transmit data not inverted. 5970 * 0b1..Transmit data inverted. 5971 */ 5972 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 5973 #define UART_C3_TXDIR_MASK (0x20U) 5974 #define UART_C3_TXDIR_SHIFT (5U) 5975 /*! TXDIR - TxD Pin Direction in Single-Wire Mode 5976 * 0b0..TxD pin is an input in single-wire mode. 5977 * 0b1..TxD pin is an output in single-wire mode. 5978 */ 5979 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 5980 #define UART_C3_T8_MASK (0x40U) 5981 #define UART_C3_T8_SHIFT (6U) 5982 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 5983 #define UART_C3_R8_MASK (0x80U) 5984 #define UART_C3_R8_SHIFT (7U) 5985 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 5986 /*! @} */ 5987 5988 /*! @name D - UART Data Register */ 5989 /*! @{ */ 5990 #define UART_D_R0T0_MASK (0x1U) 5991 #define UART_D_R0T0_SHIFT (0U) 5992 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK) 5993 #define UART_D_R1T1_MASK (0x2U) 5994 #define UART_D_R1T1_SHIFT (1U) 5995 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK) 5996 #define UART_D_R2T2_MASK (0x4U) 5997 #define UART_D_R2T2_SHIFT (2U) 5998 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK) 5999 #define UART_D_R3T3_MASK (0x8U) 6000 #define UART_D_R3T3_SHIFT (3U) 6001 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK) 6002 #define UART_D_R4T4_MASK (0x10U) 6003 #define UART_D_R4T4_SHIFT (4U) 6004 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK) 6005 #define UART_D_R5T5_MASK (0x20U) 6006 #define UART_D_R5T5_SHIFT (5U) 6007 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK) 6008 #define UART_D_R6T6_MASK (0x40U) 6009 #define UART_D_R6T6_SHIFT (6U) 6010 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK) 6011 #define UART_D_R7T7_MASK (0x80U) 6012 #define UART_D_R7T7_SHIFT (7U) 6013 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK) 6014 /*! @} */ 6015 6016 6017 /*! 6018 * @} 6019 */ /* end of group UART_Register_Masks */ 6020 6021 6022 /* UART - Peripheral instance base addresses */ 6023 /** Peripheral UART0 base address */ 6024 #define UART0_BASE (0x4006A000u) 6025 /** Peripheral UART0 base pointer */ 6026 #define UART0 ((UART_Type *)UART0_BASE) 6027 /** Peripheral UART1 base address */ 6028 #define UART1_BASE (0x4006B000u) 6029 /** Peripheral UART1 base pointer */ 6030 #define UART1 ((UART_Type *)UART1_BASE) 6031 /** Peripheral UART2 base address */ 6032 #define UART2_BASE (0x4006C000u) 6033 /** Peripheral UART2 base pointer */ 6034 #define UART2 ((UART_Type *)UART2_BASE) 6035 /** Array initializer of UART peripheral base addresses */ 6036 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE } 6037 /** Array initializer of UART peripheral base pointers */ 6038 #define UART_BASE_PTRS { UART0, UART1, UART2 } 6039 /** Interrupt vectors for the UART peripheral type */ 6040 #define UART_RX_TX_IRQS { UART0_IRQn, UART1_IRQn, UART2_IRQn } 6041 #define UART_ERR_IRQS { UART0_IRQn, UART1_IRQn, UART2_IRQn } 6042 6043 /*! 6044 * @} 6045 */ /* end of group UART_Peripheral_Access_Layer */ 6046 6047 6048 /* ---------------------------------------------------------------------------- 6049 -- WDOG Peripheral Access Layer 6050 ---------------------------------------------------------------------------- */ 6051 6052 /*! 6053 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 6054 * @{ 6055 */ 6056 6057 /** WDOG - Register Layout Typedef */ 6058 typedef struct { 6059 __IO uint8_t CS1; /**< Watchdog Control and Status Register 1, offset: 0x0 */ 6060 __IO uint8_t CS2; /**< Watchdog Control and Status Register 2, offset: 0x1 */ 6061 union { /* offset: 0x2 */ 6062 __IO uint16_t CNT; /**< WDOG_CNT register., offset: 0x2 */ 6063 struct { /* offset: 0x2 */ 6064 __IO uint8_t CNTH; /**< Watchdog Counter Register: High, offset: 0x2 */ 6065 __IO uint8_t CNTL; /**< Watchdog Counter Register: Low, offset: 0x3 */ 6066 } CNT8B; 6067 }; 6068 union { /* offset: 0x4 */ 6069 __IO uint16_t TOVAL; /**< WDOG_TOVAL register., offset: 0x4 */ 6070 struct { /* offset: 0x4 */ 6071 __IO uint8_t TOVALH; /**< Watchdog Timeout Value Register: High, offset: 0x4 */ 6072 __IO uint8_t TOVALL; /**< Watchdog Timeout Value Register: Low, offset: 0x5 */ 6073 } TOVAL8B; 6074 }; 6075 union { /* offset: 0x6 */ 6076 __IO uint16_t WIN; /**< WDOG_WIN register., offset: 0x6 */ 6077 struct { /* offset: 0x6 */ 6078 __IO uint8_t WINH; /**< Watchdog Window Register: High, offset: 0x6 */ 6079 __IO uint8_t WINL; /**< Watchdog Window Register: Low, offset: 0x7 */ 6080 } WIN8B; 6081 }; 6082 } WDOG_Type; 6083 6084 /* ---------------------------------------------------------------------------- 6085 -- WDOG Register Masks 6086 ---------------------------------------------------------------------------- */ 6087 6088 /*! 6089 * @addtogroup WDOG_Register_Masks WDOG Register Masks 6090 * @{ 6091 */ 6092 6093 /*! @name CS1 - Watchdog Control and Status Register 1 */ 6094 /*! @{ */ 6095 #define WDOG_CS1_STOP_MASK (0x1U) 6096 #define WDOG_CS1_STOP_SHIFT (0U) 6097 /*! STOP - Stop Enable 6098 * 0b0..Watchdog disabled in chip stop mode. 6099 * 0b1..Watchdog enabled in chip stop mode. 6100 */ 6101 #define WDOG_CS1_STOP(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_STOP_SHIFT)) & WDOG_CS1_STOP_MASK) 6102 #define WDOG_CS1_WAIT_MASK (0x2U) 6103 #define WDOG_CS1_WAIT_SHIFT (1U) 6104 /*! WAIT - Wait Enable 6105 * 0b0..Watchdog disabled in chip wait mode. 6106 * 0b1..Watchdog enabled in chip wait mode. 6107 */ 6108 #define WDOG_CS1_WAIT(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_WAIT_SHIFT)) & WDOG_CS1_WAIT_MASK) 6109 #define WDOG_CS1_DBG_MASK (0x4U) 6110 #define WDOG_CS1_DBG_SHIFT (2U) 6111 /*! DBG - Debug Enable 6112 * 0b0..Watchdog disabled in chip debug mode. 6113 * 0b1..Watchdog enabled in chip debug mode. 6114 */ 6115 #define WDOG_CS1_DBG(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_DBG_SHIFT)) & WDOG_CS1_DBG_MASK) 6116 #define WDOG_CS1_TST_MASK (0x18U) 6117 #define WDOG_CS1_TST_SHIFT (3U) 6118 /*! TST - Watchdog Test 6119 * 0b00..Watchdog test mode disabled. 6120 * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 6121 * 0b10..Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL. 6122 * 0b11..Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH. 6123 */ 6124 #define WDOG_CS1_TST(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_TST_SHIFT)) & WDOG_CS1_TST_MASK) 6125 #define WDOG_CS1_UPDATE_MASK (0x20U) 6126 #define WDOG_CS1_UPDATE_SHIFT (5U) 6127 /*! UPDATE - Allow updates 6128 * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 6129 * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 6130 */ 6131 #define WDOG_CS1_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_UPDATE_SHIFT)) & WDOG_CS1_UPDATE_MASK) 6132 #define WDOG_CS1_INT_MASK (0x40U) 6133 #define WDOG_CS1_INT_SHIFT (6U) 6134 /*! INT - Watchdog Interrupt 6135 * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 6136 * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks. 6137 */ 6138 #define WDOG_CS1_INT(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_INT_SHIFT)) & WDOG_CS1_INT_MASK) 6139 #define WDOG_CS1_EN_MASK (0x80U) 6140 #define WDOG_CS1_EN_SHIFT (7U) 6141 /*! EN - Watchdog Enable 6142 * 0b0..Watchdog disabled. 6143 * 0b1..Watchdog enabled. 6144 */ 6145 #define WDOG_CS1_EN(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_EN_SHIFT)) & WDOG_CS1_EN_MASK) 6146 /*! @} */ 6147 6148 /*! @name CS2 - Watchdog Control and Status Register 2 */ 6149 /*! @{ */ 6150 #define WDOG_CS2_CLK_MASK (0x3U) 6151 #define WDOG_CS2_CLK_SHIFT (0U) 6152 /*! CLK - Watchdog Clock 6153 * 0b00..Bus clock. 6154 * 0b01..1 kHz internal low-power oscillator (LPOCLK). 6155 * 0b10..32 kHz internal oscillator (ICSIRCLK). 6156 * 0b11..External clock source. 6157 */ 6158 #define WDOG_CS2_CLK(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_CLK_SHIFT)) & WDOG_CS2_CLK_MASK) 6159 #define WDOG_CS2_PRES_MASK (0x10U) 6160 #define WDOG_CS2_PRES_SHIFT (4U) 6161 /*! PRES - Watchdog Prescalar 6162 * 0b0..256 prescalar disabled. 6163 * 0b1..256 prescalar enabled. 6164 */ 6165 #define WDOG_CS2_PRES(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_PRES_SHIFT)) & WDOG_CS2_PRES_MASK) 6166 #define WDOG_CS2_FLG_MASK (0x40U) 6167 #define WDOG_CS2_FLG_SHIFT (6U) 6168 /*! FLG - Watchdog Interrupt Flag 6169 * 0b0..No interrupt occurred. 6170 * 0b1..An interrupt occurred. 6171 */ 6172 #define WDOG_CS2_FLG(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_FLG_SHIFT)) & WDOG_CS2_FLG_MASK) 6173 #define WDOG_CS2_WIN_MASK (0x80U) 6174 #define WDOG_CS2_WIN_SHIFT (7U) 6175 /*! WIN - Watchdog Window 6176 * 0b0..Window mode disabled. 6177 * 0b1..Window mode enabled. 6178 */ 6179 #define WDOG_CS2_WIN(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_WIN_SHIFT)) & WDOG_CS2_WIN_MASK) 6180 /*! @} */ 6181 6182 /*! @name CNT - WDOG_CNT register. */ 6183 /*! @{ */ 6184 #define WDOG_CNT_CNTHIGH_MASK (0xFFU) 6185 #define WDOG_CNT_CNTHIGH_SHIFT (0U) 6186 #define WDOG_CNT_CNTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) 6187 #define WDOG_CNT_CNTLOW_MASK (0xFF00U) 6188 #define WDOG_CNT_CNTLOW_SHIFT (8U) 6189 #define WDOG_CNT_CNTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) 6190 /*! @} */ 6191 6192 /*! @name CNTH - Watchdog Counter Register: High */ 6193 /*! @{ */ 6194 #define WDOG_CNTH_CNTHIGH_MASK (0xFFU) 6195 #define WDOG_CNTH_CNTHIGH_SHIFT (0U) 6196 #define WDOG_CNTH_CNTHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CNTH_CNTHIGH_SHIFT)) & WDOG_CNTH_CNTHIGH_MASK) 6197 /*! @} */ 6198 6199 /*! @name CNTL - Watchdog Counter Register: Low */ 6200 /*! @{ */ 6201 #define WDOG_CNTL_CNTLOW_MASK (0xFFU) 6202 #define WDOG_CNTL_CNTLOW_SHIFT (0U) 6203 #define WDOG_CNTL_CNTLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CNTL_CNTLOW_SHIFT)) & WDOG_CNTL_CNTLOW_MASK) 6204 /*! @} */ 6205 6206 /*! @name TOVAL - WDOG_TOVAL register. */ 6207 /*! @{ */ 6208 #define WDOG_TOVAL_TOVALHIGH_MASK (0xFFU) 6209 #define WDOG_TOVAL_TOVALHIGH_SHIFT (0U) 6210 #define WDOG_TOVAL_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) 6211 #define WDOG_TOVAL_TOVALLOW_MASK (0xFF00U) 6212 #define WDOG_TOVAL_TOVALLOW_SHIFT (8U) 6213 #define WDOG_TOVAL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) 6214 /*! @} */ 6215 6216 /*! @name TOVALH - Watchdog Timeout Value Register: High */ 6217 /*! @{ */ 6218 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFU) 6219 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) 6220 #define WDOG_TOVALH_TOVALHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) 6221 /*! @} */ 6222 6223 /*! @name TOVALL - Watchdog Timeout Value Register: Low */ 6224 /*! @{ */ 6225 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFU) 6226 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) 6227 #define WDOG_TOVALL_TOVALLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) 6228 /*! @} */ 6229 6230 /*! @name WIN - WDOG_WIN register. */ 6231 /*! @{ */ 6232 #define WDOG_WIN_WINHIGH_MASK (0xFFU) 6233 #define WDOG_WIN_WINHIGH_SHIFT (0U) 6234 #define WDOG_WIN_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) 6235 #define WDOG_WIN_WINLOW_MASK (0xFF00U) 6236 #define WDOG_WIN_WINLOW_SHIFT (8U) 6237 #define WDOG_WIN_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) 6238 /*! @} */ 6239 6240 /*! @name WINH - Watchdog Window Register: High */ 6241 /*! @{ */ 6242 #define WDOG_WINH_WINHIGH_MASK (0xFFU) 6243 #define WDOG_WINH_WINHIGH_SHIFT (0U) 6244 #define WDOG_WINH_WINHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) 6245 /*! @} */ 6246 6247 /*! @name WINL - Watchdog Window Register: Low */ 6248 /*! @{ */ 6249 #define WDOG_WINL_WINLOW_MASK (0xFFU) 6250 #define WDOG_WINL_WINLOW_SHIFT (0U) 6251 #define WDOG_WINL_WINLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) 6252 /*! @} */ 6253 6254 6255 /*! 6256 * @} 6257 */ /* end of group WDOG_Register_Masks */ 6258 6259 6260 /* WDOG - Peripheral instance base addresses */ 6261 /** Peripheral WDOG base address */ 6262 #define WDOG_BASE (0x40052000u) 6263 /** Peripheral WDOG base pointer */ 6264 #define WDOG ((WDOG_Type *)WDOG_BASE) 6265 /** Array initializer of WDOG peripheral base addresses */ 6266 #define WDOG_BASE_ADDRS { WDOG_BASE } 6267 /** Array initializer of WDOG peripheral base pointers */ 6268 #define WDOG_BASE_PTRS { WDOG } 6269 /** Interrupt vectors for the WDOG peripheral type */ 6270 #define WDOG_IRQS { WDOG_IRQn } 6271 #define WDOG_UPDATE_KEY1 (0x20C5U) 6272 #define WDOG_UPDATE_KEY_H1 (0x20U) 6273 #define WDOG_UPDATE_KEY_L1 (0xC5U) 6274 #define WDOG_UPDATE_KEY2 (0x28D9U) 6275 #define WDOG_UPDATE_KEY_H2 (0x28U) 6276 #define WDOG_UPDATE_KEY_L2 (0xD9U) 6277 #define WDOG_REFRESH_KEY1 (0x02A6U) 6278 #define WDOG_REFRESH_KEY_H1 (0x02U) 6279 #define WDOG_REFRESH_KEY_L1 (0xA6U) 6280 #define WDOG_REFRESH_KEY2 (0x80B4U) 6281 #define WDOG_REFRESH_KEY_H2 (0x80U) 6282 #define WDOG_REFRESH_KEY_L2 (0xB4U) 6283 6284 6285 /*! 6286 * @} 6287 */ /* end of group WDOG_Peripheral_Access_Layer */ 6288 6289 6290 /* 6291 ** End of section using anonymous unions 6292 */ 6293 6294 #if defined(__ARMCC_VERSION) 6295 #if (__ARMCC_VERSION >= 6010050) 6296 #pragma clang diagnostic pop 6297 #else 6298 #pragma pop 6299 #endif 6300 #elif defined(__CWCC__) 6301 #pragma pop 6302 #elif defined(__GNUC__) 6303 /* leave anonymous unions enabled */ 6304 #elif defined(__IAR_SYSTEMS_ICC__) 6305 #pragma language=default 6306 #else 6307 #error Not supported compiler type 6308 #endif 6309 6310 /*! 6311 * @} 6312 */ /* end of group Peripheral_access_layer */ 6313 6314 6315 /* ---------------------------------------------------------------------------- 6316 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 6317 ---------------------------------------------------------------------------- */ 6318 6319 /*! 6320 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 6321 * @{ 6322 */ 6323 6324 #if defined(__ARMCC_VERSION) 6325 #if (__ARMCC_VERSION >= 6010050) 6326 #pragma clang system_header 6327 #endif 6328 #elif defined(__IAR_SYSTEMS_ICC__) 6329 #pragma system_include 6330 #endif 6331 6332 /** 6333 * @brief Mask and left-shift a bit field value for use in a register bit range. 6334 * @param field Name of the register bit field. 6335 * @param value Value of the bit field. 6336 * @return Masked and shifted value. 6337 */ 6338 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 6339 /** 6340 * @brief Mask and right-shift a register value to extract a bit field value. 6341 * @param field Name of the register bit field. 6342 * @param value Value of the register. 6343 * @return Masked and shifted bit field value. 6344 */ 6345 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 6346 6347 /*! 6348 * @} 6349 */ /* end of group Bit_Field_Generic_Macros */ 6350 6351 6352 /* ---------------------------------------------------------------------------- 6353 -- SDK Compatibility 6354 ---------------------------------------------------------------------------- */ 6355 6356 /*! 6357 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 6358 * @{ 6359 */ 6360 6361 /* No SDK compatibility issues. */ 6362 6363 /*! 6364 * @} 6365 */ /* end of group SDK_Compatibility_Symbols */ 6366 6367 6368 #endif /* _MKE02Z4_H_ */ 6369 6370
