1 /* 2 * Copyright 2017-2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 9 #ifndef FSL_FTFX_ADAPTER_H 10 #define FSL_FTFX_ADAPTER_H 11 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 16 #define INVALID_REG_MASK (0) 17 #define INVALID_REG_SHIFT (0) 18 #define INVALID_REG_ADDRESS (NULL) 19 #define INVALID_REG_VALUE (0x00U) 20 21 /* @brief Flash register access type defines */ 22 #define FTFx_REG8_ACCESS_TYPE volatile uint8_t * 23 #define FTFx_REG32_ACCESS_TYPE volatile uint32_t * 24 25 /*! 26 * @name Common flash register info defines 27 * @{ 28 */ 29 #if defined(FTFA) 30 #define FTFx FTFA 31 #define FTFx_BASE FTFA_BASE 32 #define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK 33 #define FTFx_FSTAT_CCIF_SHIFT FTFA_FSTAT_CCIF_SHIFT 34 #define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK 35 #define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK 36 #define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK 37 #define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK 38 #define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK 39 #define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK 40 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM 41 #define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK 42 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ 43 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM 44 #define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK 45 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ 46 #elif defined(FTFE) 47 #define FTFx FTFE 48 #define FTFx_BASE FTFE_BASE 49 #define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK 50 #define FTFx_FSTAT_CCIF_SHIFT FTFE_FSTAT_CCIF_SHIFT 51 #define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK 52 #define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK 53 #define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK 54 #define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK 55 #define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK 56 #define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK 57 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM 58 #define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK 59 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ 60 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM 61 #define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK 62 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ 63 #elif defined(FTFL) 64 #define FTFx FTFL 65 #define FTFx_BASE FTFL_BASE 66 #define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK 67 #define FTFx_FSTAT_CCIF_SHIFT FTFL_FSTAT_CCIF_SHIFT 68 #define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK 69 #define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK 70 #define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK 71 #define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK 72 #define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK 73 #define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK 74 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM 75 #define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK 76 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ 77 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM 78 #define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK 79 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ 80 #else 81 #error "Unknown flash controller" 82 #endif 83 /*! @} */ 84 85 /*! 86 * @name Common flash register access info defines 87 * @{ 88 */ 89 #define FTFx_FCCOB3_REG (FTFx->FCCOB3) 90 #define FTFx_FCCOB5_REG (FTFx->FCCOB5) 91 #define FTFx_FCCOB6_REG (FTFx->FCCOB6) 92 #define FTFx_FCCOB7_REG (FTFx->FCCOB7) 93 94 #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) 95 #if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK) 96 #define FTFx_FLASH1_HAS_INT_PROT_REG (1) 97 #define FTFx_FPROTSH_REG (FTFx->FPROTSH) 98 #define FTFx_FPROTSL_REG (FTFx->FPROTSL) 99 #else 100 #define FTFx_FLASH1_HAS_INT_PROT_REG (0) 101 #endif 102 #endif 103 104 #if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK) 105 #define FTFx_FLASH0_HAS_HIGH_PROT_REG (1) 106 #define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3) 107 #define FTFx_FPROTH3_REG (FTFx->FPROTH3) 108 #define FTFx_FPROTH2_REG (FTFx->FPROTH2) 109 #define FTFx_FPROTH1_REG (FTFx->FPROTH1) 110 #define FTFx_FPROTH0_REG (FTFx->FPROTH0) 111 #else 112 #define FTFx_FLASH0_HAS_HIGH_PROT_REG (0) 113 #endif 114 115 #if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK) 116 #define FTFx_FPROT_LOW_REG (FTFx->FPROTL3) 117 #define FTFx_FPROTL3_REG (FTFx->FPROTL3) 118 #define FTFx_FPROTL2_REG (FTFx->FPROTL2) 119 #define FTFx_FPROTL1_REG (FTFx->FPROTL1) 120 #define FTFx_FPROTL0_REG (FTFx->FPROTL0) 121 #elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK) 122 #define FTFx_FPROT_LOW_REG (FTFx->FPROT3) 123 #define FTFx_FPROTL3_REG (FTFx->FPROT3) 124 #define FTFx_FPROTL2_REG (FTFx->FPROT2) 125 #define FTFx_FPROTL1_REG (FTFx->FPROT1) 126 #define FTFx_FPROTL0_REG (FTFx->FPROT0) 127 #endif 128 129 #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) 130 #if defined(FTFA_FACSSS_SGSIZE_S_MASK) || defined(FTFE_FACSSS_SGSIZE_S_MASK) || defined(FTFL_FACSSS_SGSIZE_S_MASK) 131 #define FTFx_FLASH1_HAS_INT_XACC_REG (1) 132 #define FTFx_XACCSH_REG (FTFx->XACCSH) 133 #define FTFx_XACCSL_REG (FTFx->XACCSL) 134 #define FTFx_FACSSS_REG (FTFx->FACSSS) 135 #define FTFx_FACSNS_REG (FTFx->FACSNS) 136 #else 137 #define FTFx_FLASH1_HAS_INT_XACC_REG (0) 138 #endif 139 #endif 140 141 #if (defined(FTFA_FACSS_SGSIZE_MASK) || defined(FTFE_FACSS_SGSIZE_MASK) || defined(FTFL_FACSS_SGSIZE_MASK) || \ 142 defined(FTFA_FACSS_SGSIZE_S_MASK) || defined(FTFE_FACSS_SGSIZE_S_MASK) || defined(FTFL_FACSS_SGSIZE_S_MASK)) 143 #define FTFx_FLASH0_HAS_INT_XACC_REG (1) 144 #define FTFx_XACCH3_REG (FTFx->XACCH3) 145 #define FTFx_XACCL3_REG (FTFx->XACCL3) 146 #define FTFx_FACSS_REG (FTFx->FACSS) 147 #define FTFx_FACSN_REG (FTFx->FACSN) 148 #else 149 #define FTFx_FLASH0_HAS_INT_XACC_REG (0) 150 #endif 151 /*! @} */ 152 153 /*! 154 * @brief MCM cache register access info defines. 155 */ 156 #if defined(MCM_PLACR_CFCC_MASK) 157 #define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK 158 #define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT 159 #else 160 #define MCM_CACHE_CLEAR_MASK INVALID_REG_MASK 161 #define MCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT 162 #endif 163 164 #if defined(MCM0) 165 #define MCM0_CACHE_REG MCM0->PLACR 166 #elif defined(MCM) && (!defined(MCM1)) 167 #define MCM0_CACHE_REG MCM->PLACR 168 #else 169 #define MCM0_CACHE_REG (INVALID_REG_ADDRESS) 170 #endif 171 172 #if defined(MCM1) 173 #define MCM1_CACHE_REG MCM1->PLACR 174 #elif defined(MCM) && (!defined(MCM0)) 175 #define MCM1_CACHE_REG MCM->PLACR 176 #else 177 #define MCM1_CACHE_REG (INVALID_REG_ADDRESS) 178 #endif 179 180 /*! 181 * @brief FMC cache register access info defines. 182 */ 183 #if defined(FMC_PFB01CR_S_INV_MASK) 184 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_INV_MASK 185 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_INV_SHIFT 186 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR 187 #elif defined(FMC_PFB01CR_S_B_INV_MASK) 188 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_B_INV_MASK 189 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_B_INV_SHIFT 190 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR 191 #elif defined(FMC_PFB0CR_S_INV_MASK) 192 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_INV_MASK 193 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_INV_SHIFT 194 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR 195 #elif defined(FMC_PFB0CR_S_B_INV_MASK) 196 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_B_INV_MASK 197 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_B_INV_SHIFT 198 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR 199 #else 200 #define FMC_SPECULATION_INVALIDATE_MASK INVALID_REG_MASK 201 #define FMC_SPECULATION_INVALIDATE_SHIFT INVALID_REG_SHIFT 202 #define FMC_SPECULATION_INVALIDATE(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 203 #define FMC_SPECULATION_INVALIDATE_REG (INVALID_REG_ADDRESS) 204 #endif 205 206 #if defined(FMC_PFB01CR_CINV_WAY_MASK) 207 #define FMC_CACHE_CLEAR_MASK FMC_PFB01CR_CINV_WAY_MASK 208 #define FMC_CACHE_CLEAR_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT 209 #define FMC_CACHE_CLEAR(x) FMC_PFB01CR_CINV_WAY(x) 210 #elif defined(FMC_PFB0CR_CINV_WAY_MASK) 211 #define FMC_CACHE_CLEAR_MASK FMC_PFB0CR_CINV_WAY_MASK 212 #define FMC_CACHE_CLEAR_SHIFT FMC_PFB0CR_CINV_WAY_SHIFT 213 #define FMC_CACHE_CLEAR(x) FMC_PFB0CR_CINV_WAY(x) 214 #else 215 #define FMC_CACHE_CLEAR_MASK INVALID_REG_MASK 216 #define FMC_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT 217 #define FMC_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 218 #endif 219 220 #if defined(FMC_PFB01CR_B0DPE_MASK) 221 #define FMC_CACHE_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK 222 #define FMC_CACHE_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK 223 #define FMC_CACHE_REG FMC->PFB01CR 224 #elif defined(FMC_PFB0CR_B0DPE_MASK) 225 #define FMC_CACHE_B0DPE_MASK FMC_PFB0CR_B0DPE_MASK 226 #define FMC_CACHE_B0IPE_MASK FMC_PFB0CR_B0IPE_MASK 227 #define FMC_CACHE_REG FMC->PFB0CR 228 #else 229 #define FMC_CACHE_B0DPE_MASK INVALID_REG_MASK 230 #define FMC_CACHE_B0IPE_MASK INVALID_REG_MASK 231 #define FMC_CACHE_REG (INVALID_REG_ADDRESS) 232 #endif 233 234 /*! 235 * @brief MSCM cache register access info defines. 236 */ 237 #if defined(MSCM_OCMDR_OCM1_MASK) 238 #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCM1_MASK 239 #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCM1_SHIFT 240 #define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCM1(x) 241 #elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) 242 #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR0_OCM1_MASK 243 #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR0_OCM1_SHIFT 244 #define MSCM_SPECULATION_SET(x) MSCM_OCMDR0_OCM1(x) 245 #elif defined(MSCM_OCMDR_OCMC1_MASK) 246 #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCMC1_MASK 247 #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCMC1_SHIFT 248 #define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCMC1(x) 249 #else 250 #define MSCM_SPECULATION_SET_MASK INVALID_REG_MASK 251 #define MSCM_SPECULATION_SET_SHIFT INVALID_REG_SHIFT 252 #define MSCM_SPECULATION_SET(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 253 #endif 254 255 #if defined(MSCM_OCMDR_OCM2_MASK) 256 #define MSCM_CACHE_CLEAR_MASK MSCM_OCMDR_OCM2_MASK 257 #define MSCM_CACHE_CLEAR_SHIFT MSCM_OCMDR_OCM2_SHIFT 258 #define MSCM_CACHE_CLEAR(x) MSCM_OCMDR_OCM2(x) 259 #else 260 #define MSCM_CACHE_CLEAR_MASK INVALID_REG_MASK 261 #define MSCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT 262 #define MSCM_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 263 #endif 264 265 #if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) 266 #define MSCM_OCMDR0_REG MSCM->OCMDR[0] 267 #define MSCM_OCMDR1_REG MSCM->OCMDR[1] 268 #elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) 269 #define MSCM_OCMDR0_REG MSCM->OCMDR0 270 #define MSCM_OCMDR1_REG MSCM->OCMDR1 271 #else 272 #define MSCM_OCMDR0_REG (INVALID_REG_ADDRESS) 273 #define MSCM_OCMDR1_REG (INVALID_REG_ADDRESS) 274 #endif 275 276 /*! 277 * @brief MSCM prefetch speculation defines. 278 */ 279 #define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) 280 #define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) 281 #define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) 282 #define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) 283 284 /*! 285 * @brief SIM PFSIZE register access info defines. 286 */ 287 #if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) 288 #define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_CORE0_PFSIZE_MASK 289 #define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_CORE0_PFSIZE_SHIFT 290 #define SIM_FCFG1_REG SIM->FCFG1 291 #elif defined(SIM_FCFG1_PFSIZE_MASK) 292 #define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_PFSIZE_MASK 293 #define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_PFSIZE_SHIFT 294 #define SIM_FCFG1_REG SIM->FCFG1 295 #else 296 #define SIM_FLASH0_PFSIZE_MASK INVALID_REG_MASK 297 #define SIM_FLASH0_PFSIZE_SHIFT INVALID_REG_SHIFT 298 #define SIM_FCFG1_REG INVALID_REG_VALUE 299 #endif 300 301 #if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) 302 #define SIM_FLASH1_PFSIZE_MASK SIM_FCFG1_CORE1_PFSIZE_MASK 303 #define SIM_FLASH1_PFSIZE_SHIFT SIM_FCFG1_CORE1_PFSIZE_SHIFT 304 #else 305 #define SIM_FLASH1_PFSIZE_MASK INVALID_REG_MASK 306 #define SIM_FLASH1_PFSIZE_SHIFT INVALID_REG_SHIFT 307 #endif 308 309 /*! 310 * @name Dual core/flash configuration 311 * @{ 312 */ 313 /*! @brief Redefines some flash features. */ 314 #if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID) 315 #if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u) 316 #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 317 #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT 318 #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE 319 #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE 320 #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE 321 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 322 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 323 #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 324 #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS 325 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT 326 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE 327 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE 328 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE 329 #if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \ 330 defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT) 331 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT 332 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT 333 #else 334 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 335 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 336 #endif 337 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT 338 #elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u) 339 #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS 340 #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT 341 #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE 342 #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE 343 #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE 344 #if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \ 345 defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT) 346 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT 347 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT 348 #else 349 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 350 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 351 #endif 352 #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT 353 #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 354 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT 355 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE 356 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE 357 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE 358 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 359 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 360 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 361 #endif 362 #else /* undfine FSL_FEATURE_FLASH_CURRENT_CORE_ID */ 363 #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 364 #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT 365 #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE 366 #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE 367 #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE 368 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 369 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 370 #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 371 #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) 372 #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS 373 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT 374 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE 375 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE 376 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE 377 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 378 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 379 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 380 #else /* undfine FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH or FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS */ 381 #define FLASH1_FEATURE_PFLASH_START_ADDRESS 0 382 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT 0 383 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE 0 384 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE 0 385 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE 0 386 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 0 387 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 0 388 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 0 389 #endif 390 #endif 391 392 #if FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT > FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 393 #define MAX_FLASH_PROT_REGION_COUNT FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT 394 #else 395 #define MAX_FLASH_PROT_REGION_COUNT FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 396 #endif 397 398 /*! @} */ 399 400 #endif /* FSL_FTFX_ADAPTER_H */ 401
