1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup BSP_MCU_RZG3S 9 * @{ 10 **********************************************************************************************************************/ 11 12 /** @} (end addtogroup BSP_MCU_RZG3S) */ 13 14 #ifndef BSP_OVERRIDE_H 15 #define BSP_OVERRIDE_H 16 17 /*********************************************************************************************************************** 18 * Includes <System Includes> , "Project Includes" 19 **********************************************************************************************************************/ 20 21 /*********************************************************************************************************************** 22 * Macro definitions 23 **********************************************************************************************************************/ 24 25 /* Define overrides required for this MCU. */ 26 #define BSP_OVERRIDE_ADC_INCLUDE 27 #define BSP_OVERRIDE_ADC_INFO_T 28 #define BSP_OVERRIDE_BSP_ACC_CONTROL_IP_T 29 #define BSP_OVERRIDE_BSP_ACCESS_CONTROL 30 #define BSP_OVERRIDE_BSP_PIN_T 31 #define BSP_OVERRIDE_BSP_PORT_T 32 #define BSP_OVERRIDE_DMAC_B_EXTERNAL_DETECTION_T 33 #define BSP_OVERRIDE_FSP_IP_T 34 #define BSP_OVERRIDE_FSP_PRIV_CLOCK_T 35 #define BSP_OVERRIDE_IOPORT_PERIPHERAL_T 36 #define BSP_OVERRIDE_TRANSFER_ADDR_MODE_T 37 #define BSP_OVERRIDE_TRANSFER_INFO_T 38 #define BSP_OVERRIDE_TRANSFER_MODE_T 39 #define BSP_OVERRIDE_TRANSFER_SIZE_T 40 41 /* Override definitions. */ 42 43 /*============================================== 44 * Access Control Level Configuration Macros Overrides 45 *==============================================*/ 46 47 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM0 (R_SYSC->SYS_SLVACCCTL0) 48 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM0 (R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Pos) 49 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM1 (R_SYSC->SYS_SLVACCCTL0) 50 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM1 (R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Pos) 51 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM2 (R_SYSC->SYS_SLVACCCTL0) 52 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM2 (R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Pos) 53 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRAM3 (R_SYSC->SYS_SLVACCCTL0) 54 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRAM3 (R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Pos) 55 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC0 (R_SYSC->SYS_SLVACCCTL2) 56 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC0 (R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Pos) 57 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC1 (R_SYSC->SYS_SLVACCCTL2) 58 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC1 (R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Pos) 59 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC2 (R_SYSC->SYS_SLVACCCTL2) 60 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC2 (R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Pos) 61 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC3 (R_SYSC->SYS_SLVACCCTL2) 62 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC3 (R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Pos) 63 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC5 (R_SYSC->SYS_SLVACCCTL2) 64 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC5 (R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Pos) 65 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TZC6 (R_SYSC->SYS_SLVACCCTL2) 66 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TZC6 (R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Pos) 67 #define BSP_ACCESS_CONTROL_REG_ACCCNT_CST (R_SYSC->SYS_SLVACCCTL3) 68 #define BSP_ACCESS_CONTROL_POS_ACCCNT_CST (R_SYSC_SYS_SLVACCCTL3_CST_SL_Pos) 69 #define BSP_ACCESS_CONTROL_REG_ACCCNT_CPG (R_SYSC->SYS_SLVACCCTL3) 70 #define BSP_ACCESS_CONTROL_POS_ACCCNT_CPG (R_SYSC_SYS_SLVACCCTL3_CPG_SL_Pos) 71 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SYSC (R_SYSC->SYS_SLVACCCTL3) 72 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SYSC (R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Pos) 73 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SYC (R_SYSC->SYS_SLVACCCTL3) 74 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SYC (R_SYSC_SYS_SLVACCCTL3_SYC_SL_Pos) 75 #define BSP_ACCESS_CONTROL_REG_ACCCNT_GIC (R_SYSC->SYS_SLVACCCTL3) 76 #define BSP_ACCESS_CONTROL_POS_ACCCNT_GIC (R_SYSC_SYS_SLVACCCTL3_GIC_SL_Pos) 77 #define BSP_ACCESS_CONTROL_REG_ACCCNT_IA55_IM33 (R_SYSC->SYS_SLVACCCTL3) 78 #define BSP_ACCESS_CONTROL_POS_ACCCNT_IA55_IM33 (R_SYSC_SYS_SLVACCCTL3_IA55_IM33_SL_Pos) 79 #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPIO (R_SYSC->SYS_SLVACCCTL3) 80 #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPIO (R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Pos) 81 #define BSP_ACCESS_CONTROL_REG_ACCCNT_MHU (R_SYSC->SYS_SLVACCCTL3) 82 #define BSP_ACCESS_CONTROL_POS_ACCCNT_MHU (R_SYSC_SYS_SLVACCCTL3_MHU_SL_Pos) 83 #define BSP_ACCESS_CONTROL_REG_ACCCNT_DMAC0 (R_SYSC->SYS_SLVACCCTL4) 84 #define BSP_ACCESS_CONTROL_POS_ACCCNT_DMAC0 (R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Pos) 85 #define BSP_ACCESS_CONTROL_REG_ACCCNT_DMAC1 (R_SYSC->SYS_SLVACCCTL4) 86 #define BSP_ACCESS_CONTROL_POS_ACCCNT_DMAC1 (R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Pos) 87 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM0 (R_SYSC->SYS_SLVACCCTL4) 88 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM0 (R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Pos) 89 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM1 (R_SYSC->SYS_SLVACCCTL4) 90 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM1 (R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Pos) 91 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM2 (R_SYSC->SYS_SLVACCCTL4) 92 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM2 (R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Pos) 93 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM3 (R_SYSC->SYS_SLVACCCTL4) 94 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM3 (R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Pos) 95 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM4 (R_SYSC->SYS_SLVACCCTL4) 96 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM4 (R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Pos) 97 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM5 (R_SYSC->SYS_SLVACCCTL4) 98 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM5 (R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Pos) 99 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM6 (R_SYSC->SYS_SLVACCCTL4) 100 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM6 (R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Pos) 101 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OSTM7 (R_SYSC->SYS_SLVACCCTL4) 102 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OSTM7 (R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Pos) 103 #define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT0 (R_SYSC->SYS_SLVACCCTL4) 104 #define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT0 (R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Pos) 105 #define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT1 (R_SYSC->SYS_SLVACCCTL4) 106 #define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT1 (R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Pos) 107 #define BSP_ACCESS_CONTROL_REG_ACCCNT_WDT2 (R_SYSC->SYS_SLVACCCTL4) 108 #define BSP_ACCESS_CONTROL_POS_ACCCNT_WDT2 (R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Pos) 109 #define BSP_ACCESS_CONTROL_REG_ACCCNT_RTC (R_SYSC->SYS_SLVACCCTL4) 110 #define BSP_ACCESS_CONTROL_POS_ACCCNT_RTC (R_SYSC_SYS_SLVACCCTL4_RTC_SL_Pos) 111 #define BSP_ACCESS_CONTROL_REG_ACCCNT_MTU3A (R_SYSC->SYS_SLVACCCTL5) 112 #define BSP_ACCESS_CONTROL_POS_ACCCNT_MTU3A (R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Pos) 113 #define BSP_ACCESS_CONTROL_REG_ACCCNT_POE3 (R_SYSC->SYS_SLVACCCTL5) 114 #define BSP_ACCESS_CONTROL_POS_ACCCNT_POE3 (R_SYSC_SYS_SLVACCCTL5_POE3_SL_Pos) 115 #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPT (R_SYSC->SYS_SLVACCCTL5) 116 #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPT (R_SYSC_SYS_SLVACCCTL5_GPT_SL_Pos) 117 #define BSP_ACCESS_CONTROL_REG_ACCCNT_POEG (R_SYSC->SYS_SLVACCCTL5) 118 #define BSP_ACCESS_CONTROL_POS_ACCCNT_POEG (R_SYSC_SYS_SLVACCCTL5_POEG_SL_Pos) 119 #define BSP_ACCESS_CONTROL_REG_ACCCNT_DDR (R_SYSC->SYS_SLVACCCTL5) 120 #define BSP_ACCESS_CONTROL_POS_ACCCNT_DDR (R_SYSC_SYS_SLVACCCTL5_DDR_SL_Pos) 121 #define BSP_ACCESS_CONTROL_REG_ACCCNT_XSPI (R_SYSC->SYS_SLVACCCTL5) 122 #define BSP_ACCESS_CONTROL_POS_ACCCNT_XSPI (R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Pos) 123 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OCTA (R_SYSC->SYS_SLVACCCTL5) 124 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OCTA (R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Pos) 125 #define BSP_ACCESS_CONTROL_REG_ACCCNT_USBT (R_SYSC->SYS_SLVACCCTL6) 126 #define BSP_ACCESS_CONTROL_POS_ACCCNT_USBT (R_SYSC_SYS_SLVACCCTL6_USBT_SL_Pos) 127 #define BSP_ACCESS_CONTROL_REG_ACCCNT_USB20 (R_SYSC->SYS_SLVACCCTL6) 128 #define BSP_ACCESS_CONTROL_POS_ACCCNT_USB20 (R_SYSC_SYS_SLVACCCTL6_USB20_SL_Pos) 129 #define BSP_ACCESS_CONTROL_REG_ACCCNT_USB21 (R_SYSC->SYS_SLVACCCTL6) 130 #define BSP_ACCESS_CONTROL_POS_ACCCNT_USB21 (R_SYSC_SYS_SLVACCCTL6_USB21_SL_Pos) 131 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI0 (R_SYSC->SYS_SLVACCCTL6) 132 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI0 (R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Pos) 133 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI1 (R_SYSC->SYS_SLVACCCTL6) 134 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI1 (R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Pos) 135 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SDHI2 (R_SYSC->SYS_SLVACCCTL6) 136 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SDHI2 (R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Pos) 137 #define BSP_ACCESS_CONTROL_REG_ACCCNT_ETH0 (R_SYSC->SYS_SLVACCCTL6) 138 #define BSP_ACCESS_CONTROL_POS_ACCCNT_ETH0 (R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Pos) 139 #define BSP_ACCESS_CONTROL_REG_ACCCNT_ETH1 (R_SYSC->SYS_SLVACCCTL6) 140 #define BSP_ACCESS_CONTROL_POS_ACCCNT_ETH1 (R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Pos) 141 #define BSP_ACCESS_CONTROL_REG_ACCCNT_PCIE (R_SYSC->SYS_SLVACCCTL6) 142 #define BSP_ACCESS_CONTROL_POS_ACCCNT_PCIE (R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Pos) 143 #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C0 (R_SYSC->SYS_SLVACCCTL7) 144 #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C0 (R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Pos) 145 #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C1 (R_SYSC->SYS_SLVACCCTL7) 146 #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C1 (R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Pos) 147 #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C2 (R_SYSC->SYS_SLVACCCTL7) 148 #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C2 (R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Pos) 149 #define BSP_ACCESS_CONTROL_REG_ACCCNT_I2C3 (R_SYSC->SYS_SLVACCCTL7) 150 #define BSP_ACCESS_CONTROL_POS_ACCCNT_I2C3 (R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Pos) 151 #define BSP_ACCESS_CONTROL_REG_ACCCNT_I3C (R_SYSC->SYS_SLVACCCTL7) 152 #define BSP_ACCESS_CONTROL_POS_ACCCNT_I3C (R_SYSC_SYS_SLVACCCTL7_I3C_SL_Pos) 153 #define BSP_ACCESS_CONTROL_REG_ACCCNT_CANFD (R_SYSC->SYS_SLVACCCTL7) 154 #define BSP_ACCESS_CONTROL_POS_ACCCNT_CANFD (R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Pos) 155 #define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI0 (R_SYSC->SYS_SLVACCCTL7) 156 #define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI0 (R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Pos) 157 #define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI1 (R_SYSC->SYS_SLVACCCTL7) 158 #define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI1 (R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Pos) 159 #define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI2 (R_SYSC->SYS_SLVACCCTL7) 160 #define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI2 (R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Pos) 161 #define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI3 (R_SYSC->SYS_SLVACCCTL7) 162 #define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI3 (R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Pos) 163 #define BSP_ACCESS_CONTROL_REG_ACCCNT_RSPI4 (R_SYSC->SYS_SLVACCCTL7) 164 #define BSP_ACCESS_CONTROL_POS_ACCCNT_RSPI4 (R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Pos) 165 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF0 (R_SYSC->SYS_SLVACCCTL8) 166 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF0 (R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Pos) 167 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF1 (R_SYSC->SYS_SLVACCCTL8) 168 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF1 (R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Pos) 169 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF2 (R_SYSC->SYS_SLVACCCTL8) 170 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF2 (R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Pos) 171 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF3 (R_SYSC->SYS_SLVACCCTL8) 172 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF3 (R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Pos) 173 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF4 (R_SYSC->SYS_SLVACCCTL8) 174 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF4 (R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Pos) 175 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCIF5 (R_SYSC->SYS_SLVACCCTL8) 176 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCIF5 (R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Pos) 177 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCI0 (R_SYSC->SYS_SLVACCCTL8) 178 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCI0 (R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Pos) 179 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SCI1 (R_SYSC->SYS_SLVACCCTL8) 180 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SCI1 (R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Pos) 181 #define BSP_ACCESS_CONTROL_REG_ACCCNT_IRDA (R_SYSC->SYS_SLVACCCTL8) 182 #define BSP_ACCESS_CONTROL_POS_ACCCNT_IRDA (R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Pos) 183 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF0 (R_SYSC->SYS_SLVACCCTL9) 184 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF0 (R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Pos) 185 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF1 (R_SYSC->SYS_SLVACCCTL9) 186 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF1 (R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Pos) 187 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF2 (R_SYSC->SYS_SLVACCCTL9) 188 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF2 (R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Pos) 189 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SSIF3 (R_SYSC->SYS_SLVACCCTL9) 190 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SSIF3 (R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Pos) 191 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SRC (R_SYSC->SYS_SLVACCCTL9) 192 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SRC (R_SYSC_SYS_SLVACCCTL9_SRC_SL_Pos) 193 #define BSP_ACCESS_CONTROL_REG_ACCCNT_SPDIF (R_SYSC->SYS_SLVACCCTL9) 194 #define BSP_ACCESS_CONTROL_POS_ACCCNT_SPDIF (R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Pos) 195 #define BSP_ACCESS_CONTROL_REG_ACCCNT_PDM (R_SYSC->SYS_SLVACCCTL9) 196 #define BSP_ACCESS_CONTROL_POS_ACCCNT_PDM (R_SYSC_SYS_SLVACCCTL9_PDM_SL_Pos) 197 #define BSP_ACCESS_CONTROL_REG_ACCCNT_ADC (R_SYSC->SYS_SLVACCCTL10) 198 #define BSP_ACCESS_CONTROL_POS_ACCCNT_ADC (R_SYSC_SYS_SLVACCCTL10_ADC_SL_Pos) 199 #define BSP_ACCESS_CONTROL_REG_ACCCNT_TSU (R_SYSC->SYS_SLVACCCTL10) 200 #define BSP_ACCESS_CONTROL_POS_ACCCNT_TSU (R_SYSC_SYS_SLVACCCTL10_TSU_SL_Pos) 201 #define BSP_ACCESS_CONTROL_REG_ACCCNT_OTP (R_SYSC->SYS_SLVACCCTL11) 202 #define BSP_ACCESS_CONTROL_POS_ACCCNT_OTP (R_SYSC_SYS_SLVACCCTL11_OTP_SL_Pos) 203 #define BSP_ACCESS_CONTROL_REG_ACCCNT_VBATT (R_SYSC->SYS_SLVACCCTL11) 204 #define BSP_ACCESS_CONTROL_POS_ACCCNT_VBATT (R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Pos) 205 #define BSP_ACCESS_CONTROL_REG_ACCCNT_CA55 (R_SYSC->SYS_SLVACCCTL12) 206 #define BSP_ACCESS_CONTROL_POS_ACCCNT_CA55 (R_SYSC_SYS_SLVACCCTL12_CA55_SL_Pos) 207 #define BSP_ACCESS_CONTROL_REG_ACCCNT_CM33 (R_SYSC->SYS_SLVACCCTL12) 208 #define BSP_ACCESS_CONTROL_POS_ACCCNT_CM33 (R_SYSC_SYS_SLVACCCTL12_CM33_SL_Pos) 209 #define BSP_ACCESS_CONTROL_REG_ACCCNT_CM33FPU (R_SYSC->SYS_SLVACCCTL12) 210 #define BSP_ACCESS_CONTROL_POS_ACCCNT_CM33FPU (R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Pos) 211 #define BSP_ACCESS_CONTROL_REG_ACCCNT_LSI (R_SYSC->SYS_SLVACCCTL14) 212 #define BSP_ACCESS_CONTROL_POS_ACCCNT_LSI (R_SYSC_SYS_SLVACCCTL14_LSI_SL_Pos) 213 #define BSP_ACCESS_CONTROL_REG_ACCCNT_AOF (R_SYSC->SYS_SLVACCCTL16) 214 #define BSP_ACCESS_CONTROL_POS_ACCCNT_AOF (R_SYSC_SYS_SLVACCCTL16_AOF_SL_Pos) 215 #define BSP_ACCESS_CONTROL_REG_ACCCNT_LP (R_SYSC->SYS_SLVACCCTL17) 216 #define BSP_ACCESS_CONTROL_POS_ACCCNT_LP (R_SYSC_SYS_SLVACCCTL17_LP_SL_Pos) 217 #define BSP_ACCESS_CONTROL_REG_ACCCNT_GPREG (R_SYSC->SYS_SLVACCCTL18) 218 #define BSP_ACCESS_CONTROL_POS_ACCCNT_GPREG (R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Pos) 219 #define BSP_ACCESS_CONTROL_REG_ACCCNT_IPCONT (R_SYSC->SYS_SLVACCCTL20) 220 #define BSP_ACCESS_CONTROL_POS_ACCCNT_IPCONT (R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Pos) 221 222 /*============================================== 223 * CPG control macros Overrides 224 *==============================================*/ 225 226 #define BSP_CLKON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKON_GTM) 227 #define BSP_CLKON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKON_GTM_CLK0_ON_Pos + (channel))) 228 #define BSP_CLKMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKMON_GTM) 229 #define BSP_CLKMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKMON_GTM_CLK0_MON_Pos + (channel))) 230 #define BSP_RST_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RST_GTM) 231 #define BSP_RST_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RST_GTM_UNIT0_RSTB_Pos + (channel))) 232 #define BSP_RSTMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RSTMON_GTM) 233 #define BSP_RSTMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RSTMON_GTM_RST0_MON_Pos + (channel))) 234 235 #define BSP_CLKON_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_CLKON_SPI) 236 #define BSP_CLKON_BIT_FSP_IP_XSPI(channel) (0xFU << (R_CPG_CPG_CLKON_SPI_CLK0_ON_Pos)) 237 #define BSP_CLKMON_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_CLKMON_SPI) 238 #define BSP_CLKMON_BIT_FSP_IP_XSPI(channel) (0xFU << (R_CPG_CPG_CLKMON_SPI_CLK0_MON_Pos)) 239 #define BSP_RST_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_RST_SPI) 240 #define BSP_RST_BIT_FSP_IP_XSPI(channel) (3U << (R_CPG_CPG_RST_SPI_UNIT0_RSTB_Pos)) 241 #define BSP_RSTMON_REG_FSP_IP_XSPI(channel) (R_CPG->CPG_RSTMON_SPI) 242 #define BSP_RSTMON_BIT_FSP_IP_XSPI(channel) (3U << (R_CPG_CPG_RSTMON_SPI_RST0_MON_Pos)) 243 244 #define BSP_DELAY_LOOP_CYCLES (49) 245 246 #define BSP_MSTP_REG_FSP_IP_SCIF(channel) *((4U >= \ 247 channel) ? &R_CPG->CPG_BUS_MCPU2_MSTOP : &R_CPG->CPG_BUS_MCPU3_MSTOP) 248 #define BSP_MSTP_BIT_FSP_IP_SCIF(channel) ((4U >= \ 249 channel) ? (1U << (R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP1_ON_Pos + channel)) \ 250 : (1U << R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP4_ON_Pos)) 251 252 #define BSP_MSTP_REG_FSP_IP_XSPI(channel) R_CPG->CPG_BUS_MCPU1_MSTOP 253 #define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP1_ON_Pos) 254 255 #define BSP_MSTP_REG_FSP_IP_RSPI(channel) *((1U >= channel) ? &R_CPG->CPG_BUS_MCPU1_MSTOP \ 256 : ((2U == channel) ? &R_CPG->CPG_BUS_MCPU2_MSTOP \ 257 : &R_CPG->CPG_BUS_MCPU3_MSTOP)) 258 #define BSP_MSTP_BIT_FSP_IP_RSPI(channel) ((1U >= \ 259 channel) ? (1U << (R_CPG_CPG_BUS_MCPU1_MSTOP_MSTOP14_ON_Pos + channel)) \ 260 : ((2U == channel) ? (1U << R_CPG_CPG_BUS_MCPU2_MSTOP_MSTOP0_ON_Pos) \ 261 : (1U << \ 262 (R_CPG_CPG_BUS_MCPU3_MSTOP_MSTOP2_ON_Pos + \ 263 (uint32_t) (channel - 3))))) 264 265 /*============================================== 266 * IOPORT-Related Macros Overrides 267 *==============================================*/ 268 269 #define OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET (24) 270 271 /*============================================== 272 * SYSC-Related Macros Overrides 273 *==============================================*/ 274 275 #if BSP_CURRENT_CORE == RZG3S_CORE_CM33 276 #define R_BSP_IM33_DISABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 | \ 277 R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;} 278 #define R_BSP_IM33_ENABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 & \ 279 ~R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;} 280 #define R_BSP_WAIT_CM33_RESET() {while ((R_SYSC->SYS_LP_CM33CTL0 & \ 281 R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Msk) == 0U) \ 282 { /* wait */}; \ 283 } 284 #elif BSP_CURRENT_CORE == RZG3S_CORE_CM33_FPU 285 #define R_BSP_IM33_DISABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 | \ 286 R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk;} 287 #define R_BSP_IM33_ENABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 & \ 288 ~R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk;} 289 #define R_BSP_WAIT_CM33_RESET() {while ((R_SYSC->SYS_LP_CM33FPUCTL0 & \ 290 R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Msk) == 0U) \ 291 { /* wait */}; \ 292 } 293 #endif 294 295 /*********************************************************************************************************************** 296 * Typedef definitions 297 **********************************************************************************************************************/ 298 299 /*============================================== 300 * BSP-Related Definitions Overrides 301 *==============================================*/ 302 303 /** Superset list of all possible IO ports. */ 304 typedef enum e_bsp_io_port 305 { 306 BSP_IO_PORT_00 = 0x0000, /* IO port 0 */ 307 BSP_IO_PORT_01 = 0x1000, /* IO port 1 */ 308 BSP_IO_PORT_02 = 0x1100, /* IO port 2 */ 309 BSP_IO_PORT_03 = 0x1200, /* IO port 3 */ 310 BSP_IO_PORT_04 = 0x1300, /* IO port 4 */ 311 BSP_IO_PORT_05 = 0x0100, /* IO port 5 */ 312 BSP_IO_PORT_06 = 0x0200, /* IO port 6 */ 313 BSP_IO_PORT_07 = 0x1400, /* IO port 7 */ 314 BSP_IO_PORT_08 = 0x1500, /* IO port 8 */ 315 BSP_IO_PORT_09 = 0x1600, /* IO port 9 */ 316 BSP_IO_PORT_10 = 0x1700, /* IO port 10 */ 317 BSP_IO_PORT_11 = 0x0300, /* IO port 11 */ 318 BSP_IO_PORT_12 = 0x0400, /* IO port 12 */ 319 BSP_IO_PORT_13 = 0x0500, /* IO port 13 */ 320 BSP_IO_PORT_14 = 0x0600, /* IO port 14 */ 321 BSP_IO_PORT_15 = 0x0700, /* IO port 15 */ 322 BSP_IO_PORT_16 = 0x0800, /* IO port 16 */ 323 BSP_IO_PORT_17 = 0x0900, /* IO port 17 */ 324 BSP_IO_PORT_18 = 0x0A00, /* IO port 18 */ 325 } bsp_io_port_t; 326 327 /** Superset list of all possible IO port pins. */ 328 typedef enum e_bsp_io_port_pin_t 329 { 330 BSP_IO_PORT_00_PIN_00 = 0x0000, /* IO port 0 pin 0 */ 331 BSP_IO_PORT_00_PIN_01 = 0x0001, /* IO port 0 pin 1 */ 332 BSP_IO_PORT_00_PIN_02 = 0x0002, /* IO port 0 pin 2 */ 333 BSP_IO_PORT_00_PIN_03 = 0x0003, /* IO port 0 pin 3 */ 334 335 BSP_IO_PORT_05_PIN_00 = 0x0100, /* IO port 5 pin 0 */ 336 BSP_IO_PORT_05_PIN_01 = 0x0101, /* IO port 5 pin 1 */ 337 BSP_IO_PORT_05_PIN_02 = 0x0102, /* IO port 5 pin 2 */ 338 BSP_IO_PORT_05_PIN_03 = 0x0103, /* IO port 5 pin 3 */ 339 BSP_IO_PORT_05_PIN_04 = 0x0104, /* IO port 5 pin 4 */ 340 341 BSP_IO_PORT_06_PIN_00 = 0x0200, /* IO port 6 pin 0 */ 342 BSP_IO_PORT_06_PIN_01 = 0x0201, /* IO port 6 pin 1 */ 343 BSP_IO_PORT_06_PIN_02 = 0x0202, /* IO port 6 pin 2 */ 344 BSP_IO_PORT_06_PIN_03 = 0x0203, /* IO port 6 pin 3 */ 345 BSP_IO_PORT_06_PIN_04 = 0x0204, /* IO port 6 pin 4 */ 346 347 BSP_IO_PORT_11_PIN_00 = 0x0300, /* IO port 11 pin 0 */ 348 BSP_IO_PORT_11_PIN_01 = 0x0301, /* IO port 11 pin 1 */ 349 BSP_IO_PORT_11_PIN_02 = 0x0302, /* IO port 11 pin 2 */ 350 BSP_IO_PORT_11_PIN_03 = 0x0303, /* IO port 11 pin 3 */ 351 352 BSP_IO_PORT_12_PIN_00 = 0x0400, /* IO port 12 pin 0 */ 353 BSP_IO_PORT_12_PIN_01 = 0x0401, /* IO port 12 pin 1 */ 354 355 BSP_IO_PORT_13_PIN_00 = 0x0500, /* IO port 13 pin 0 */ 356 BSP_IO_PORT_13_PIN_01 = 0x0501, /* IO port 13 pin 1 */ 357 BSP_IO_PORT_13_PIN_02 = 0x0502, /* IO port 13 pin 2 */ 358 BSP_IO_PORT_13_PIN_03 = 0x0503, /* IO port 13 pin 3 */ 359 BSP_IO_PORT_13_PIN_04 = 0x0504, /* IO port 13 pin 4 */ 360 361 BSP_IO_PORT_14_PIN_00 = 0x0600, /* IO port 14 pin 0 */ 362 BSP_IO_PORT_14_PIN_01 = 0x0601, /* IO port 14 pin 1 */ 363 BSP_IO_PORT_14_PIN_02 = 0x0602, /* IO port 14 pin 2 */ 364 365 BSP_IO_PORT_15_PIN_00 = 0x0700, /* IO port 15 pin 0 */ 366 BSP_IO_PORT_15_PIN_01 = 0x0701, /* IO port 15 pin 1 */ 367 BSP_IO_PORT_15_PIN_02 = 0x0702, /* IO port 15 pin 2 */ 368 BSP_IO_PORT_15_PIN_03 = 0x0703, /* IO port 15 pin 3 */ 369 370 BSP_IO_PORT_16_PIN_00 = 0x0800, /* IO port 16 pin 0 */ 371 BSP_IO_PORT_16_PIN_01 = 0x0801, /* IO port 16 pin 1 */ 372 373 BSP_IO_PORT_17_PIN_00 = 0x0900, /* IO port 17 pin 0 */ 374 BSP_IO_PORT_17_PIN_01 = 0x0901, /* IO port 17 pin 1 */ 375 BSP_IO_PORT_17_PIN_02 = 0x0902, /* IO port 17 pin 2 */ 376 BSP_IO_PORT_17_PIN_03 = 0x0903, /* IO port 17 pin 3 */ 377 378 BSP_IO_PORT_18_PIN_00 = 0x0A00, /* IO port 18 pin 0 */ 379 BSP_IO_PORT_18_PIN_01 = 0x0A01, /* IO port 18 pin 1 */ 380 BSP_IO_PORT_18_PIN_02 = 0x0A02, /* IO port 18 pin 2 */ 381 BSP_IO_PORT_18_PIN_03 = 0x0A03, /* IO port 18 pin 3 */ 382 BSP_IO_PORT_18_PIN_04 = 0x0A04, /* IO port 18 pin 4 */ 383 BSP_IO_PORT_18_PIN_05 = 0x0A05, /* IO port 18 pin 5 */ 384 385 BSP_IO_PORT_01_PIN_00 = 0x1000, /* IO port 1 pin 0 */ 386 BSP_IO_PORT_01_PIN_01 = 0x1001, /* IO port 1 pin 1 */ 387 BSP_IO_PORT_01_PIN_02 = 0x1002, /* IO port 1 pin 2 */ 388 BSP_IO_PORT_01_PIN_03 = 0x1003, /* IO port 1 pin 3 */ 389 BSP_IO_PORT_01_PIN_04 = 0x1004, /* IO port 1 pin 4 */ 390 391 BSP_IO_PORT_02_PIN_00 = 0x1100, /* IO port 2 pin 0 */ 392 BSP_IO_PORT_02_PIN_01 = 0x1101, /* IO port 2 pin 1 */ 393 BSP_IO_PORT_02_PIN_02 = 0x1102, /* IO port 2 pin 2 */ 394 BSP_IO_PORT_02_PIN_03 = 0x1103, /* IO port 2 pin 3 */ 395 396 BSP_IO_PORT_03_PIN_00 = 0x1200, /* IO port 3 pin 0 */ 397 BSP_IO_PORT_03_PIN_01 = 0x1201, /* IO port 3 pin 1 */ 398 BSP_IO_PORT_03_PIN_02 = 0x1202, /* IO port 3 pin 2 */ 399 BSP_IO_PORT_03_PIN_03 = 0x1203, /* IO port 3 pin 3 */ 400 401 BSP_IO_PORT_04_PIN_00 = 0x1300, /* IO port 4 pin 0 */ 402 BSP_IO_PORT_04_PIN_01 = 0x1301, /* IO port 4 pin 1 */ 403 BSP_IO_PORT_04_PIN_02 = 0x1302, /* IO port 4 pin 2 */ 404 BSP_IO_PORT_04_PIN_03 = 0x1303, /* IO port 4 pin 3 */ 405 BSP_IO_PORT_04_PIN_04 = 0x1304, /* IO port 4 pin 4 */ 406 BSP_IO_PORT_04_PIN_05 = 0x1305, /* IO port 4 pin 5 */ 407 408 BSP_IO_PORT_07_PIN_00 = 0x1400, /* IO port 7 pin 0 */ 409 BSP_IO_PORT_07_PIN_01 = 0x1401, /* IO port 7 pin 1 */ 410 BSP_IO_PORT_07_PIN_02 = 0x1402, /* IO port 7 pin 2 */ 411 BSP_IO_PORT_07_PIN_03 = 0x1403, /* IO port 7 pin 3 */ 412 BSP_IO_PORT_07_PIN_04 = 0x1404, /* IO port 7 pin 4 */ 413 414 BSP_IO_PORT_08_PIN_00 = 0x1500, /* IO port 8 pin 0 */ 415 BSP_IO_PORT_08_PIN_01 = 0x1501, /* IO port 8 pin 1 */ 416 BSP_IO_PORT_08_PIN_02 = 0x1502, /* IO port 8 pin 2 */ 417 BSP_IO_PORT_08_PIN_03 = 0x1503, /* IO port 8 pin 3 */ 418 BSP_IO_PORT_08_PIN_04 = 0x1504, /* IO port 8 pin 4 */ 419 420 BSP_IO_PORT_09_PIN_00 = 0x1600, /* IO port 9 pin 0 */ 421 BSP_IO_PORT_09_PIN_01 = 0x1601, /* IO port 9 pin 1 */ 422 BSP_IO_PORT_09_PIN_02 = 0x1602, /* IO port 9 pin 2 */ 423 BSP_IO_PORT_09_PIN_03 = 0x1603, /* IO port 9 pin 3 */ 424 425 BSP_IO_PORT_10_PIN_00 = 0x1700, /* IO port 10 pin 0 */ 426 BSP_IO_PORT_10_PIN_01 = 0x1701, /* IO port 10 pin 1 */ 427 BSP_IO_PORT_10_PIN_02 = 0x1702, /* IO port 10 pin 2 */ 428 BSP_IO_PORT_10_PIN_03 = 0x1703, /* IO port 10 pin 3 */ 429 BSP_IO_PORT_10_PIN_04 = 0x1704, /* IO port 10 pin 4 */ 430 431 /* Special purpose port */ 432 BSP_IO_NMI = 0xFFFF0000, /* NMI */ 433 434 BSP_IO_TMS_SWDIO = 0xFFFF0100, /* TMS_SWDIO */ 435 BSP_IO_TDO = 0xFFFF0101, /* TDO */ 436 437 BSP_IO_AUDIO_CLK1 = 0xFFFF0200, /* AUDIO_CLK1 */ 438 BSP_IO_AUDIO_CLK2 = 0xFFFF0201, /* AUDIO_CLK2 */ 439 440 BSP_IO_XSPI_SPCLK = 0xFFFF0400, /* XSPI_SPCLK */ 441 BSP_IO_XSPI_RESET_N = 0xFFFF0401, /* XSPI_RESET_N */ 442 BSP_IO_XSPI_WP_N = 0xFFFF0402, /* XSPI_WP_N */ 443 BSP_IO_XSPI_DS = 0xFFFF0403, /* XSPI_DS */ 444 BSP_IO_XSPI_CS0_N = 0xFFFF0404, /* XSPI_CS0_N */ 445 BSP_IO_XSPI_CS1_N = 0xFFFF0405, /* XSPI_CS1_N */ 446 447 BSP_IO_XSPI_IO0 = 0xFFFF0500, /* XSPI_IO0 */ 448 BSP_IO_XSPI_IO1 = 0xFFFF0501, /* XSPI_IO1 */ 449 BSP_IO_XSPI_IO2 = 0xFFFF0502, /* XSPI_IO2 */ 450 BSP_IO_XSPI_IO3 = 0xFFFF0503, /* XSPI_IO3 */ 451 BSP_IO_XSPI_IO4 = 0xFFFF0504, /* XSPI_IO4 */ 452 BSP_IO_XSPI_IO5 = 0xFFFF0505, /* XSPI_IO5 */ 453 BSP_IO_XSPI_IO6 = 0xFFFF0506, /* XSPI_IO6 */ 454 BSP_IO_XSPI_IO7 = 0xFFFF0507, /* XSPI_IO7 */ 455 456 BSP_IO_WDTOVF_PERROUT = 0xFFFF0600, /* WDTOVF_PERROUT */ 457 458 BSP_IO_I3C_SDA = 0xFFFF0900, /* I3C_SDA */ 459 BSP_IO_I3C_SCL = 0xFFFF0901, /* I3C_SCL */ 460 461 BSP_IO_SD0_CLK = 0xFFFF1000, /* CD0_CLK */ 462 BSP_IO_SD0_CMD = 0xFFFF1001, /* CD0_CMD */ 463 BSP_IO_SD0_RST_N = 0xFFFF1002, /* CD0_RST_N */ 464 465 BSP_IO_SD0_DATA0 = 0xFFFF1100, /* SD0_DATA0 */ 466 BSP_IO_SD0_DATA1 = 0xFFFF1101, /* SD0_DATA1 */ 467 BSP_IO_SD0_DATA2 = 0xFFFF1102, /* SD0_DATA2 */ 468 BSP_IO_SD0_DATA3 = 0xFFFF1103, /* SD0_DATA3 */ 469 BSP_IO_SD0_DATA4 = 0xFFFF1104, /* SD0_DATA4 */ 470 BSP_IO_SD0_DATA5 = 0xFFFF1105, /* SD0_DATA5 */ 471 BSP_IO_SD0_DATA6 = 0xFFFF1106, /* SD0_DATA6 */ 472 BSP_IO_SD0_DATA7 = 0xFFFF1107, /* SD0_DATA7 */ 473 474 BSP_IO_SD1_CLK = 0xFFFF1200, /* SD1_CLK */ 475 BSP_IO_SD1_CMD = 0xFFFF1201, /* SD1_CMD */ 476 477 BSP_IO_SD1_DATA0 = 0xFFFF1300, /* SD1_DATA0 */ 478 BSP_IO_SD1_DATA1 = 0xFFFF1301, /* SD1_DATA1 */ 479 BSP_IO_SD1_DATA2 = 0xFFFF1302, /* SD1_DATA2 */ 480 BSP_IO_SD1_DATA3 = 0xFFFF1303, /* SD1_DATA3 */ 481 } bsp_io_port_pin_t; 482 483 /*============================================== 484 * DMAC_B External Detection Overrides 485 *==============================================*/ 486 487 /** Detection method of the external DMA request signal. See RZ/T2M hardware manual Table 14.19 DMA Transfer Request Detection Operation Setting Table. */ 488 typedef enum e_dmac_b_external_detection 489 { 490 DMAC_B_EXTERNAL_DETECTION_NO_DETECTION = 0, ///< Not using hardware detection. 491 } dmac_b_external_detection_t; 492 493 /** access control. */ 494 typedef enum e_acc_control_ip 495 { 496 ACCCNT_SRAM0 = 0, 497 ACCCNT_SRAM1, 498 ACCCNT_SRAM2, 499 ACCCNT_SRAM3, 500 ACCCNT_TZC0, 501 ACCCNT_TZC1, 502 ACCCNT_TZC2, 503 ACCCNT_TZC3, 504 ACCCNT_TZC5, 505 ACCCNT_TZC6, 506 ACCCNT_CST, 507 ACCCNT_CPG, 508 ACCCNT_SYSC, 509 ACCCNT_SYC, 510 ACCCNT_GIC, 511 ACCCNT_IA55_IM33, 512 ACCCNT_GPIO, 513 ACCCNT_MHU, 514 ACCCNT_DMAC0, 515 ACCCNT_DMAC1, 516 ACCCNT_OSTM0, 517 ACCCNT_OSTM1, 518 ACCCNT_OSTM2, 519 ACCCNT_OSTM3, 520 ACCCNT_OSTM4, 521 ACCCNT_OSTM5, 522 ACCCNT_OSTM6, 523 ACCCNT_OSTM7, 524 ACCCNT_WDT0, 525 ACCCNT_WDT1, 526 ACCCNT_WDT2, 527 ACCCNT_RTC, 528 ACCCNT_MTU3A, 529 ACCCNT_POE3, 530 ACCCNT_GPT, 531 ACCCNT_POEG, 532 ACCCNT_DDR, 533 ACCCNT_XSPI, 534 ACCCNT_OCTA, 535 ACCCNT_USBT, 536 ACCCNT_USB20, 537 ACCCNT_USB21, 538 ACCCNT_SDHI0, 539 ACCCNT_SDHI1, 540 ACCCNT_SDHI2, 541 ACCCNT_ETH0, 542 ACCCNT_ETH1, 543 ACCCNT_PCIE, 544 ACCCNT_I2C0, 545 ACCCNT_I2C1, 546 ACCCNT_I2C2, 547 ACCCNT_I2C3, 548 ACCCNT_I3C, 549 ACCCNT_CANFD, 550 ACCCNT_RSPI0, 551 ACCCNT_RSPI1, 552 ACCCNT_RSPI2, 553 ACCCNT_RSPI3, 554 ACCCNT_RSPI4, 555 ACCCNT_SCIF0, 556 ACCCNT_SCIF1, 557 ACCCNT_SCIF2, 558 ACCCNT_SCIF3, 559 ACCCNT_SCIF4, 560 ACCCNT_SCIF5, 561 ACCCNT_SCI0, 562 ACCCNT_SCI1, 563 ACCCNT_IRDA, 564 ACCCNT_SSIF0, 565 ACCCNT_SSIF1, 566 ACCCNT_SSIF2, 567 ACCCNT_SSIF3, 568 ACCCNT_SRC, 569 ACCCNT_SPDIF, 570 ACCCNT_PDM, 571 ACCCNT_ADC, 572 ACCCNT_TSU, 573 ACCCNT_OTP, 574 ACCCNT_VBATT, 575 ACCCNT_CA55, 576 ACCCNT_CM33, 577 ACCCNT_CM33FPU, 578 ACCCNT_LSI, 579 ACCCNT_AOF, 580 ACCCNT_LP, 581 ACCCNT_GPREG, 582 ACCCNT_IPCONT, 583 } fsp_acc_control_ip_t; 584 585 /** Available modules. */ 586 typedef enum e_fsp_ip 587 { 588 FSP_IP_GTM = 0, ///< General Timer 589 FSP_IP_GPT = 1, ///< General PWM Timer 590 FSP_IP_POEG = 2, ///< Port Output Enable for GPT 591 FSP_IP_PORT = 3, ///< I/O Ports 592 FSP_IP_IM33 = 4, ///< IM33 (Interrupt controller) 593 FSP_IP_SCIF = 5, ///< Serial Communications Interface with FIFO 594 FSP_IP_RIIC = 6, ///< I2C Bus Interface 595 FSP_IP_RSPI = 7, ///< Renesas Serial Peripheral Interface 596 FSP_IP_MHU = 8, ///< Message Handling Unit 597 FSP_IP_DMAC = 9, ///< Direct Memory Access Controller 598 FSP_IP_DMAC_s = 9, ///< Direct Memory Access Controller 599 FSP_IP_SSI = 10, ///< Serial Sound Interface 600 FSP_IP_CANFD = 11, ///< CANFD Interface (RS-CANFD) 601 FSP_IP_ADC = 12, ///< A/D Converter 602 FSP_IP_TSU = 13, ///< Thermal Sensor Unit 603 FSP_IP_WDT = 14, ///< Watchdog Timer 604 FSP_IP_SCI = 15, ///< Serial Communications Interface 605 FSP_IP_XSPI = 16 ///< Expanded Serial Peripheral Interface 606 } fsp_ip_t; 607 608 /* Private enum used in R_FSP_SystemClockHzGet. */ 609 typedef enum e_fsp_priv_clock 610 { 611 FSP_PRIV_CLOCK_ICLK = 0, /* Cortex-A55 Clock */ 612 FSP_PRIV_CLOCK_I2CLK, /* Cortex-M33 Clock */ 613 FSP_PRIV_CLOCK_I3CLK, /* Cortex-M33 FPU Clock */ 614 FSP_PRIV_CLOCK_S0CLK, /* DDR-PHY Clock */ 615 FSP_PRIV_CLOCK_OC0CLK, /* OCTA0 Clock */ 616 FSP_PRIV_CLOCK_OC1CLK, /* OCTA1 Clock */ 617 FSP_PRIV_CLOCK_SPI0CLK, /* SPI0 Clock */ 618 FSP_PRIV_CLOCK_SPI1CLK, /* SPI1 Clock */ 619 FSP_PRIV_CLOCK_SD0CLK, /* SDH0 Clock */ 620 FSP_PRIV_CLOCK_SD1CLK, /* SDH1 Clock */ 621 FSP_PRIV_CLOCK_SD2CLK, /* SDH2 Clock */ 622 FSP_PRIV_CLOCK_M0CLK, /* VCP, LCDC Clock */ 623 FSP_PRIV_CLOCK_HPCLK, /* Ethernet Clock */ 624 FSP_PRIV_CLOCK_TSUCLK, /* TSU Clock */ 625 FSP_PRIV_CLOCK_ZTCLK, /* JAUTH Clock */ 626 FSP_PRIV_CLOCK_P0CLK, /* APB-BUS Clock */ 627 FSP_PRIV_CLOCK_P1CLK, /* AXI-BUS Clock */ 628 FSP_PRIV_CLOCK_P2CLK, /* P2CLK */ 629 FSP_PRIV_CLOCK_P3CLK, /* P3CLK */ 630 FSP_PRIV_CLOCK_P4CLK, /* P4CLK */ 631 FSP_PRIV_CLOCK_P5CLK, /* P5CLK */ 632 FSP_PRIV_CLOCK_ATCLK, /* ATCLK */ 633 FSP_PRIV_CLOCK_OSCCLK, /* OSC Clock */ 634 FSP_PRIV_CLOCK_OSCCLK2, /* OSC2 Clock */ 635 FSP_PRIV_CLOCK_NUM, 636 } fsp_priv_clock_t; 637 638 /*============================================== 639 * IOPORT Overrides 640 *==============================================*/ 641 642 /** Superset of all peripheral functions. */ 643 typedef enum e_ioport_peripheral 644 { 645 /** Pin will function as a Mode1 peripheral pin */ 646 IOPORT_PERIPHERAL_MODE1 = (0x0UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 647 648 /** Pin will function as a Mode2 peripheral pin */ 649 IOPORT_PERIPHERAL_MODE2 = (0x1UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 650 651 /** Pin will function as a Mode3 peripheral pin */ 652 IOPORT_PERIPHERAL_MODE3 = (0x2UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 653 654 /** Pin will function as a Mode4 peripheral pin */ 655 IOPORT_PERIPHERAL_MODE4 = (0x3UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 656 657 /** Pin will function as a Mode5 peripheral pin */ 658 IOPORT_PERIPHERAL_MODE5 = (0x4UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 659 660 /** Pin will function as a Mode6 peripheral pin */ 661 IOPORT_PERIPHERAL_MODE6 = (0x5UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 662 663 /** Pin will function as a Mode7 peripheral pin */ 664 IOPORT_PERIPHERAL_MODE7 = (0x6UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 665 666 /** Pin will function as a Mode8 peripheral pin */ 667 IOPORT_PERIPHERAL_MODE8 = (0x7UL << OVERRIDE_IOPORT_PRV_PFS_PSEL_OFFSET), 668 } ioport_peripheral_t; 669 670 /*============================================== 671 * Transfer API Overrides 672 *==============================================*/ 673 674 /** Transfer mode describes what will happen when a transfer request occurs. */ 675 typedef enum e_transfer_mode 676 { 677 /** Normal mode. */ 678 TRANSFER_MODE_NORMAL = 0, 679 680 /** Block mode. */ 681 TRANSFER_MODE_BLOCK = 1 682 } transfer_mode_t; 683 684 /** Transfer size specifies the size of each individual transfer. */ 685 typedef enum e_transfer_size 686 { 687 TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value 688 TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value 689 TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value 690 TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value 691 TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value 692 TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value 693 TRANSFER_SIZE_64_BYTE = 6, ///< Each transfer transfers a 512-bit value 694 TRANSFER_SIZE_128_BYTE = 7 ///< Each transfer transfers a 1024-bit value 695 } transfer_size_t; 696 697 /** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ 698 typedef enum e_transfer_addr_mode 699 { 700 /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ 701 TRANSFER_ADDR_MODE_INCREMENTED = 0, 702 703 /** Address pointer remains fixed after each transfer. */ 704 TRANSFER_ADDR_MODE_FIXED = 1 705 } transfer_addr_mode_t; 706 707 typedef struct st_transfer_info 708 { 709 /** Select what happens to destination address after each transfer. */ 710 transfer_addr_mode_t dest_addr_mode; 711 712 /** Select what happens to source address after each transfer. */ 713 transfer_addr_mode_t src_addr_mode; 714 715 /** Select mode from @ref transfer_mode_t. */ 716 transfer_mode_t mode; 717 718 /** Source address. */ 719 void const * volatile p_src; 720 721 /** Destination address. */ 722 void * volatile p_dest; 723 724 /** The total number of transfer bytes. */ 725 volatile uint32_t length; 726 727 /** Select source data size to transfer at once. */ 728 transfer_size_t src_size; 729 730 /** Select destination data size to transfer at once. */ 731 transfer_size_t dest_size; 732 733 /** Next1 Register set settings */ 734 void const * p_next1_src; 735 void * p_next1_dest; 736 uint32_t next1_length; 737 } transfer_info_t; 738 739 /*============================================== 740 * ADC API Overrides 741 *==============================================*/ 742 743 /** ADC Information Structure for Transfer Interface */ 744 typedef struct st_adc_info 745 { 746 volatile const void * p_address; ///< The address to start reading the data from 747 uint32_t length; ///< The total number of transfers to read 748 transfer_size_t transfer_size; ///< The size of each transfer 749 uint32_t calibration_data1; ///< Temperature sensor calibration data1 750 uint32_t calibration_data2; ///< Temperature sensor calibration data2 751 } adc_info_t; 752 753 /*********************************************************************************************************************** 754 * Exported global variables 755 **********************************************************************************************************************/ 756 757 /*********************************************************************************************************************** 758 * Exported global functions (to be accessed by other files) 759 **********************************************************************************************************************/ 760 761 #endif 762
