1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _S32K344_FEATURES_H_ 8 #define _S32K344_FEATURES_H_ 9 10 #include "autoconf.h" 11 12 /* SOC module features */ 13 14 /* @brief LPUART availability on the SoC. */ 15 #define FSL_FEATURE_SOC_LPUART_COUNT (16) 16 /* @brief FLEXCAN availability on the SoC. */ 17 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (6) 18 /* @brief LPI2C availability on the SoC. */ 19 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 20 /* @brief LPSPI availability on the SoC. */ 21 #define FSL_FEATURE_SOC_LPSPI_COUNT (6) 22 /* @brief EDMA availability on the SoC. */ 23 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 24 25 /* LPUART module features */ 26 27 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 28 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 29 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 30 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 31 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 32 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 33 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 34 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 35 /* @brief Has 32-bit register MODIR */ 36 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 37 /* @brief Hardware flow control (RTS, CTS) is supported. */ 38 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 39 /* @brief Infrared (modulation) is supported. */ 40 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 41 /* @brief 2 bits long stop bit is available. */ 42 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 43 /* @brief If 10-bit mode is supported. */ 44 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 45 /* @brief If 7-bit mode is supported. */ 46 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 47 /* @brief Baud rate fine adjustment is available. */ 48 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 49 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 50 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 51 /* @brief Baud rate oversampling is available. */ 52 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 53 /* @brief Baud rate oversampling is available. */ 54 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 55 /* @brief Peripheral type. */ 56 #define FSL_FEATURE_LPUART_IS_SCI (1) 57 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 58 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 59 /* @brief Supports two match addresses to filter incoming frames. */ 60 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 61 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 62 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 63 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 64 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 65 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 66 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 67 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 68 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 69 /* @brief Has improved smart card (ISO7816 protocol) support. */ 70 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 71 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 72 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 73 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 74 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 75 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 76 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 77 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 78 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 79 /* @brief Has separate DMA RX and TX requests. */ 80 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 81 /* @brief Has separate RX and TX interrupts. */ 82 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 83 /* @brief Has LPAURT_PARAM. */ 84 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 85 /* @brief Has LPUART_VERID. */ 86 #define FSL_FEATURE_LPUART_HAS_VERID (1) 87 /* @brief Has LPUART_GLOBAL. */ 88 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 89 /* @brief Has LPUART_PINCFG. */ 90 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 91 92 /* FLEXCAN module features */ 93 94 /* @brief Message buffer size */ 95 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) \ 96 (((x) == CAN0) ? (96) : \ 97 (((x) == CAN1) ? (64) : \ 98 (((x) == CAN2) ? (64) : \ 99 (((x) == CAN3) ? (32) : \ 100 (((x) == CAN4) ? (32) : \ 101 (((x) == CAN5) ? (32) : (-1))))))) 102 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 103 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 104 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 105 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 106 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 107 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 108 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 109 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER ((CONFIG_CAN_MAX_MB > 32) ? 1 : 0) 110 /* @brief Instance has extended bit timing register (register CBT). */ 111 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 112 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 113 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 114 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 115 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 116 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ 117 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) 118 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ 119 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) 120 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled 121 * to be transmitted at a specific moment during the arbitration process). */ 122 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 123 /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that 124 * is enabled to be transmitted in a specific moment during the arbitration process). */ 125 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) 126 /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is 127 * transmitted into the CAN bus when the Message Buffer under transmission is either aborted 128 * or deactivated while the CAN bus is in the Bus Idle state). */ 129 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) 130 /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode 131 * or the Low-Power Mode are entered during a Bus-Off state). */ 132 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) 133 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ 134 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) 135 /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ 136 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) 137 /* @brief Has memory error control (register MECR). */ 138 #define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) 139 /* @brief Init memory base 1 */ 140 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) 141 /* @brief Init memory size 1 */ 142 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA5F) 143 /* @brief Init memory base 2 */ 144 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20) 145 /* @brief Init memory size 2 */ 146 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25DF) 147 /* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ 148 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0) 149 /* @brief Has Pretended Networking mode support. */ 150 #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) 151 /* @brief Has Enhanced Rx FIFO. */ 152 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (0) 153 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ 154 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) 155 156 /* LPI2C module features */ 157 158 /* @brief Has separate DMA RX and TX requests. */ 159 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 160 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 161 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 162 163 /* LPSPI module features */ 164 165 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 166 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) 167 /* @brief Has separate DMA RX and TX requests. */ 168 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 169 /* @brief Has CCR1 (related to existence of registers CCR1). */ 170 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) 171 /* @brief Is affected by errata S32K3X4-0P55A-1P55A-ERRATA / ERR050456 (LPSPI: Reset to fifo does not work as expected). */ 172 #define FSL_FEATURE_LPSPI_HAS_ERRATA_050456 (1) 173 174 /* EDMA module features */ 175 176 /* 177 * @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], 178 * ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], 179 * SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). 180 * (Valid only for eDMA modules.) Note: this is including channels used as offset. 181 */ 182 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (148) 183 /* @brief Total number of DMA channels on all modules. Note: this is including channels used as offset. */ 184 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (148) 185 /* @brief Has DMA_Error interrupt vector. */ 186 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) 187 /* @brief If channel clock controlled independently */ 188 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) 189 /* @brief Has no register bit fields MP_CSR[EBW]. */ 190 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) 191 192 #define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) 193 194 /* DMAMUX module features */ 195 196 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 197 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 198 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 199 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 200 /* @brief Register CHCFGn width. */ 201 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 202 203 /* @brief Memory map has offset between subsystems. */ 204 #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) 205 206 #endif /* _S32K344_FEATURES_H_ */ 207
