1 /* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _S32K344_FEATURES_H_ 8 #define _S32K344_FEATURES_H_ 9 10 #include <zephyr/autoconf.h> 11 12 /* SOC module features */ 13 14 /* @brief LPUART availability on the SoC. */ 15 #define FSL_FEATURE_SOC_LPUART_COUNT (16) 16 /* @brief FLEXCAN availability on the SoC. */ 17 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (6) 18 /* @brief LPI2C availability on the SoC. */ 19 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 20 /* @brief LPSPI availability on the SoC. */ 21 #define FSL_FEATURE_SOC_LPSPI_COUNT (6) 22 /* @brief EDMA availability on the SoC. */ 23 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 24 /* @brief DMAMUX availability on the SoC. */ 25 #define FSL_FEATURE_SOC_DMAMUX_COUNT (2) 26 /* @brief FLEXIO availability on the SoC. */ 27 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 28 29 /* LPUART module features */ 30 31 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 32 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 33 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 34 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 35 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 36 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 37 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 38 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 39 /* @brief Has 32-bit register MODIR */ 40 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 41 /* @brief Hardware flow control (RTS, CTS) is supported. */ 42 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 43 /* @brief Infrared (modulation) is supported. */ 44 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 45 /* @brief 2 bits long stop bit is available. */ 46 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 47 /* @brief If 10-bit mode is supported. */ 48 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 49 /* @brief If 7-bit mode is supported. */ 50 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 51 /* @brief Baud rate fine adjustment is available. */ 52 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 53 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 54 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 55 /* @brief Baud rate oversampling is available. */ 56 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 57 /* @brief Baud rate oversampling is available. */ 58 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 59 /* @brief Peripheral type. */ 60 #define FSL_FEATURE_LPUART_IS_SCI (1) 61 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 62 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 63 /* @brief Supports two match addresses to filter incoming frames. */ 64 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 65 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 66 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 67 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 68 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 69 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 70 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 71 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 72 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 73 /* @brief Has improved smart card (ISO7816 protocol) support. */ 74 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 75 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 76 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 77 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 78 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 79 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 80 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 81 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 82 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 83 /* @brief Has separate DMA RX and TX requests. */ 84 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 85 /* @brief Has separate RX and TX interrupts. */ 86 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 87 /* @brief Has LPAURT_PARAM. */ 88 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 89 /* @brief Has LPUART_VERID. */ 90 #define FSL_FEATURE_LPUART_HAS_VERID (1) 91 /* @brief Has LPUART_GLOBAL. */ 92 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 93 /* @brief Has LPUART_PINCFG. */ 94 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 95 96 /* FLEXCAN module features */ 97 98 /* @brief Message buffer size */ 99 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) \ 100 (((x) == CAN0) ? (96) : \ 101 (((x) == CAN1) ? (64) : \ 102 (((x) == CAN2) ? (64) : \ 103 (((x) == CAN3) ? (32) : \ 104 (((x) == CAN4) ? (32) : \ 105 (((x) == CAN5) ? (32) : (-1))))))) 106 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 107 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 108 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 109 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 110 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 111 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 112 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 113 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER ((CONFIG_CAN_MAX_MB > 32) ? 1 : 0) 114 /* @brief Instance has extended bit timing register (register CBT). */ 115 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 116 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 117 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 118 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 119 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 120 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ 121 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) 122 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ 123 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) 124 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled 125 * to be transmitted at a specific moment during the arbitration process). */ 126 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 127 /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that 128 * is enabled to be transmitted in a specific moment during the arbitration process). */ 129 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) 130 /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is 131 * transmitted into the CAN bus when the Message Buffer under transmission is either aborted 132 * or deactivated while the CAN bus is in the Bus Idle state). */ 133 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) 134 /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode 135 * or the Low-Power Mode are entered during a Bus-Off state). */ 136 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) 137 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ 138 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) 139 /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ 140 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) 141 /* @brief Has memory error control (register MECR). */ 142 #define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) 143 /* @brief Init memory base 1 */ 144 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) 145 /* @brief Init memory size 1 */ 146 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA5F) 147 /* @brief Init memory base 2 */ 148 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20) 149 /* @brief Init memory size 2 */ 150 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25DF) 151 /* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ 152 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0) 153 /* @brief Has Pretended Networking mode support. */ 154 #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) 155 /* @brief Has Enhanced Rx FIFO. */ 156 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (0) 157 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ 158 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (0) 159 160 /* LPI2C module features */ 161 162 /* @brief Has separate DMA RX and TX requests. */ 163 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 164 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 165 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 166 167 /* LPSPI module features */ 168 169 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 170 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) 171 /* @brief Has separate DMA RX and TX requests. */ 172 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 173 /* @brief Has CCR1 (related to existence of registers CCR1). */ 174 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1) 175 /* @brief Is affected by errata S32K3X4-0P55A-1P55A-ERRATA / ERR050456 (LPSPI: Reset to fifo does not work as expected). */ 176 #define FSL_FEATURE_LPSPI_HAS_ERRATA_050456 (0) 177 178 /* EDMA module features */ 179 180 /* 181 * @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], 182 * ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], 183 * SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). 184 * (Valid only for eDMA modules.) Note: this is including channels used as offset. 185 */ 186 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (148) 187 /* @brief Total number of DMA channels on all modules. Note: this is including channels used as offset. */ 188 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (148) 189 /* @brief Has DMA_Error interrupt vector. */ 190 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) 191 /* @brief If channel clock controlled independently */ 192 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) 193 /* @brief Has no register bit fields MP_CSR[EBW]. */ 194 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) 195 196 #define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) 197 198 /* DMAMUX module features */ 199 200 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 201 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 202 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 203 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 204 /* @brief Register CHCFGn width. */ 205 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 206 207 /* FLEXIO module features */ 208 209 /* @brief Has pin input output related registers */ 210 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) 211 /* @brief Has doze mode in Flexio */ 212 #define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (0) 213 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 214 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 215 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 216 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 217 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 218 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 219 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 220 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 221 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 222 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 223 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 224 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 225 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 226 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 227 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 228 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 229 /* @brief Reset value of the FLEXIO_VERID register */ 230 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x02010003) 231 /* @brief Reset value of the FLEXIO_PARAM register */ 232 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x04200808) 233 /* @brief Flexio DMA request base channel */ 234 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 235 236 /* @brief Memory map has offset between subsystems. */ 237 #define FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET (1) 238 239 #endif /* _S32K344_FEATURES_H_ */ 240
