1 /* 2 * Copyright 2023-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _S32Z270_FEATURES_H_ 8 #define _S32Z270_FEATURES_H_ 9 10 /* SOC module features */ 11 12 /* @brief PIT availability on the SoC. */ 13 #define FSL_FEATURE_SOC_PIT_COUNT (2) 14 15 /* PIT module features */ 16 17 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 18 #define FSL_FEATURE_PIT_TIMER_COUNT (6) 19 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 20 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 21 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 22 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 23 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 24 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 25 /* @brief Has timer enable control. */ 26 #define FSL_FEATURE_PIT_HAS_MDIS (1) 27 28 29 /* I3C module features */ 30 31 /* @brief Has TERM bitfile in MERRWARN register. */ 32 #define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) 33 /* @brief SOC has no reset driver. */ 34 #define FSL_FEATURE_I3C_HAS_NO_RESET (1) 35 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ 36 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) 37 /* @brief Register SCONFIG do not have IDRAND bitfield. */ 38 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) 39 /* @brief Register SCONFIG has HDROK bitfield. */ 40 #define FSL_FEATURE_I3C_HAS_HDROK (1) 41 /* @brief Has ERRATA_051617. */ 42 #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) 43 44 /* FLEXCAN module features */ 45 46 /* @brief Message buffer size */ 47 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (128) 48 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 49 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) 50 /* @brief Instance has doze mode support (register bit field MCR[DOZE]). */ 51 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) 52 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 53 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (0) 54 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 55 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) 56 /* @brief Instance has extended bit timing register (register CBT). */ 57 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 58 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 59 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 60 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 61 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 62 /* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ 63 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (0) 64 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ 65 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (0) 66 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled 67 * to be transmitted at a specific moment during the arbitration process). */ 68 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 69 /* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that 70 * is enabled to be transmitted in a specific moment during the arbitration process). */ 71 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) 72 /* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is 73 * transmitted into the CAN bus when the Message Buffer under transmission is either aborted 74 * or deactivated while the CAN bus is in the Bus Idle state). */ 75 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) 76 /* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode 77 * or the Low-Power Mode are entered during a Bus-Off state). */ 78 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) 79 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ 80 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) 81 /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ 82 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) 83 /* @brief Has memory error control (register MECR). */ 84 #define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) 85 /* @brief Init memory base 1 */ 86 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) 87 /* @brief Init memory size 1 */ 88 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60) 89 /* @brief Init memory base 2 */ 90 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20) 91 /* @brief Init memory size 2 */ 92 #define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25E0) 93 /* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ 94 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0) 95 /* @brief Has Pretended Networking mode support. */ 96 #define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (0) 97 /* @brief Has Enhanced Rx FIFO. */ 98 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (0) 99 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ 100 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) 101 /* @brief Does not support Memory Error Control (bitfield MECR[HANCEI]. */ 102 #define FSL_FEATURE_FLEXCAN_HAS_NO_HANCEI_SUPPORT (1) 103 /* @brief Does not support Memory Error Control (bitfield MECR[FANCEI]. */ 104 #define FSL_FEATURE_FLEXCAN_HAS_NO_FANCEI_SUPPORT (1) 105 /* @brief Does not support Memory Error Control (bitfield MECR[CEI]. */ 106 #define FSL_FEATURE_FLEXCAN_HAS_NO_CEI_SUPPORT (1) 107 /* @brief Does not support Wake Up interrupt (bitfield MCR[WAKMSK]. */ 108 #define FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT (1) 109 /* @brief Does not support Self Wake Up (bitfield MCR[SLFWAK]. */ 110 #define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (1) 111 /* @brief Does not support Wake Up Source (bitfield MCR[WAKSRC]. */ 112 #define FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT (1) 113 /* @brief EDMA availability on the SoC. */ 114 #define FSL_FEATURE_SOC_EDMA_COUNT (4) 115 116 /* EDMA module features */ 117 118 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 119 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 120 /* @brief If 8 bytes transfer supported. */ 121 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 122 /* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ 123 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ 124 (((x) == DMA0) ? (32) : \ 125 (((x) == DMA1) ? (16) : \ 126 (((x) == DMA4) ? (16) : \ 127 (((x) == DMA5) ? (16) : (0))))) 128 /* @brief Has register CH_CSR. */ 129 /* @brief If 16 bytes transfer supported. */ 130 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 131 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 132 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (0) 133 /* @brief Has register bit fields MP_CSR[GMRC]. */ 134 #define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) 135 /* @brief If 64 bytes transfer supported. */ 136 #define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) 137 /* @brief Has DMA_Error interrupt vector. */ 138 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 139 /* @brief Has register bit fields CR[CLM]. */ 140 #define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0) 141 /* @brief If 128 bytes transfer supported. */ 142 #define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) 143 /* @brief Has register access permission. */ 144 #define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1) 145 /* @brief NBYTES must be multiple of 8 when using scatter gather. */ 146 #define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) 147 /* @brief If 128 bytes transfer supported. */ 148 #define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) 149 /* @brief If channel clock controlled independently */ 150 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) 151 /* @brief NBYTES must be multiple of 8 when using scatter gather. */ 152 #define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) 153 /* @brief Has register CH_CSR. */ 154 #define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) 155 /* @brief Has channel mux */ 156 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (0) 157 /* @brief Has no register bit fields MP_CSR[EBW]. */ 158 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (0) 159 /* @brief Instance has channel mux */ 160 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (0) 161 /* @brief If dma has common clock gate */ 162 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) 163 /* @brief Has register CH_SBR. */ 164 #define FSL_FEATURE_EDMA_HAS_SBR (1) 165 /* @brief If dma channel IRQ support parameter */ 166 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) 167 /* @brief Has no register bit fields CH_SBR[ATTR]. */ 168 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) 169 /* @brief Has register bit field CH_CSR[SWAP]. */ 170 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) 171 /* @brief Instance has register bit field CH_CSR[SWAP]. */ 172 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) 173 /* @brief Has register bit field CH_SBR[INSTR]. */ 174 #define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) 175 /* @brief Whether has prot register. */ 176 #define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) 177 /* @brief Instance has register bit field CH_SBR[INSTR]. */ 178 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) 179 /* @brief Whether has MP channel mux. */ 180 #define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) 181 /* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ 182 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) 183 /* @brief Instance has register CH_MATTR. */ 184 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) 185 /* @brief Has register bit field CH_CSR[SIGNEXT]. */ 186 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) 187 /* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ 188 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) 189 /* @brief Has register bit field TCD_CSR[BWC]. */ 190 #define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) 191 /* @brief Instance has register bit field TCD_CSR[BWC]. */ 192 #define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) 193 /* @brief Has register bit fields TCD_CSR[TMC]. */ 194 #define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) 195 /* @brief Instance has register bit fields TCD_CSR[TMC]. */ 196 #define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) 197 198 /* @brief edma5 has different tcd type. */ 199 #define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) 200 /* @brief Has no register bit fields CH_SBR[SEC]. */ 201 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) 202 203 /* DMAMUX module features */ 204 205 /* @brief Total number of DMA channels on all modules. Note: this is including channels used as offset. */ 206 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (80) 207 /* @brief DMAMUX availability on the SoC. */ 208 #define FSL_FEATURE_SOC_DMAMUX_COUNT (5) 209 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 210 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 211 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 212 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 213 /* @brief Register CHCFGn width. */ 214 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 215 216 /* I2C module features */ 217 218 /* @brief LPI2C availability on the SoC. */ 219 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 220 /* @brief Has separate DMA RX and TX requests. */ 221 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 222 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 223 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) 224 225 /* DSPI module features */ 226 227 /* @brief DSPI availability on the SoC. */ 228 #define FSL_FEATURE_SOC_DSPI_COUNT (1) 229 /* @brief Receive/transmit FIFO size in number of items. */ 230 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (16) 231 /* @brief Maximum transfer data width in bits. */ 232 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 233 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 234 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (3) 235 /* @brief Number of chip select pins. */ 236 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) 237 /* @brief Number of CTAR registers. */ 238 #define FSL_FEATURE_DSPI_CTAR_COUNT (6) 239 /* @brief Has chip select strobe capability on the PCS5 pin. */ 240 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 241 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 242 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 243 /* @brief Has 16-bit data transfer support. */ 244 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 245 /* @brief Has separate DMA RX and TX requests. */ 246 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 247 /* @brief Does not support Transmit FIFO Fill Flag (bitfield SR[TFUF]. */ 248 #define FSL_FEATURE_DSPI_HAS_NO_SR_TFUF_SUPPORT (1) 249 /* @brief Does not support Transmit FIFO Underflow Request Enable (bitfield RSER[TFUF_RE]. */ 250 #define FSL_FEATURE_DSPI_HAS_NO_RSER_TFUF_RE_SUPPORT (1) 251 /* @brief Does not support Slave mode . */ 252 #define FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT (1) 253 254 #endif /* _S32Z270_FEATURES_H_ */ 255
