1 /**************************************************************************//**
2 * @file clk.h
3 * @version V3.0
4 * @brief Clock Controller (CLK) driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 ******************************************************************************/
9 #ifndef __CLK_H__
10 #define __CLK_H__
11
12
13 #ifdef __cplusplus
14 extern "C"
15 {
16 #endif
17
18
19
20 /** @addtogroup Standard_Driver Standard Driver
21 @{
22 */
23
24 /** @addtogroup CLK_Driver CLK Driver
25 @{
26 */
27
28 /** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
29 @{
30 */
31
32
33 #define FREQ_2MHZ 2000000UL
34 #define FREQ_4MHZ 4000000UL
35 #define FREQ_8MHZ 8000000UL
36 #define FREQ_12MHZ 12000000UL
37 #define FREQ_24MHZ 24000000UL
38 #define FREQ_25MHZ 25000000UL
39 #define FREQ_48MHZ 48000000UL
40 #define FREQ_50MHZ 50000000UL
41 #define FREQ_64MHZ 64000000UL
42 #define FREQ_75MHZ 75000000UL
43 #define FREQ_84MHZ 84000000UL
44 #define FREQ_96MHZ 96000000UL
45 #define FREQ_144MHZ 144000000UL
46 #define FREQ_200MHZ 200000000UL
47
48
49
50 /*---------------------------------------------------------------------------------------------------------*/
51 /* CLKSEL0 constant definitions. */
52 /*---------------------------------------------------------------------------------------------------------*/
53 #define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HXT */
54 #define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LXT */
55 #define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as PLL */
56 #define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LIRC */
57 #define CLK_CLKSEL0_HCLKSEL_HIRC48 (0x05UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC48 */
58 #define CLK_CLKSEL0_HCLKSEL_MIRC (0x06UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as MIRC */
59 #define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC */
60
61 #define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
62 #define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as LXT */
63 #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
64 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HCLK/2 */
65 #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HIRC/2 */
66 #define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
67
68 #define CLK_CLKSEL0_SDH0SEL_HXT (0x00UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HXT */
69 #define CLK_CLKSEL0_SDH0SEL_PLL (0x01UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as PLL */
70 #define CLK_CLKSEL0_SDH0SEL_HCLK (0x02UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HCLK */
71 #define CLK_CLKSEL0_SDH0SEL_HIRC (0x03UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HIRC */
72
73 #define CLK_CLKSEL0_USBSEL_HIRC48 (0x00UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as HIRC48 */
74 #define CLK_CLKSEL0_USBSEL_PLL (0x01UL<<CLK_CLKSEL0_USBSEL_Pos) /*!< Setting USB clock source as PLL */
75
76
77 /*---------------------------------------------------------------------------------------------------------*/
78 /* CLKSEL1 constant definitions. */
79 /*---------------------------------------------------------------------------------------------------------*/
80 #define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LXT */
81 #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */
82 #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LIRC */
83
84 #define CLK_CLKSEL1_LCDSEL_LIRC (0x0UL<<CLK_CLKSEL1_LCDSEL_Pos) /*!< Setting LCD clock source as LIRC */
85 #define CLK_CLKSEL1_LCDSEL_LXT (0x1UL<<CLK_CLKSEL1_LCDSEL_Pos) /*!< Setting LCD clock source as LXT */
86
87 #define CLK_CLKSEL1_LCDCPSEL_MIRC1P2M (0x0UL<<CLK_CLKSEL1_LCDCPSEL_Pos) /*!< Setting LCD charge pump clock source as MIRC1P2M */
88 #define CLK_CLKSEL1_LCDCPSEL_MIRC (0x1UL<<CLK_CLKSEL1_LCDCPSEL_Pos) /*!< Setting LCD charge pump clock source as MIRC */
89
90 #define CLK_CLKSEL1_EWDTSEL_LXT (0x1UL<<CLK_CLKSEL1_EWDTSEL_Pos) /*!< Setting EWDT clock source as LXT */
91 #define CLK_CLKSEL1_EWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_EWDTSEL_Pos) /*!< Setting EWDT clock source as HCLK/2048 */
92 #define CLK_CLKSEL1_EWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_EWDTSEL_Pos) /*!< Setting EWDT clock source as LIRC */
93
94 #define CLK_CLKSEL1_EWWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_EWWDTSEL_Pos) /*!< Setting EWWDT clock source as HCLK/2048 */
95 #define CLK_CLKSEL1_EWWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_EWWDTSEL_Pos) /*!< Setting EWWDT clock source as LIRC */
96
97 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */
98 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */
99 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */
100 #define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
101 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LIRC */
102 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HIRC */
103
104 #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HXT */
105 #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LXT */
106 #define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK0 */
107 #define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger */
108 #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LIRC */
109 #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HIRC */
110
111 #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HXT */
112 #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LXT */
113 #define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK1 */
114 #define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger */
115 #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LIRC */
116 #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HIRC */
117
118 #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HXT */
119 #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LXT */
120 #define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK1 */
121 #define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger */
122 #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LIRC */
123 #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HIRC */
124
125 #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HXT */
126 #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as LXT */
127 #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK */
128 #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HIRC */
129
130 #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as HCLK/2048 */
131 #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as LIRC */
132
133
134 /*---------------------------------------------------------------------------------------------------------*/
135 /* CLKSEL2 constant definitions. */
136 /*---------------------------------------------------------------------------------------------------------*/
137 #define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Setting EPWM0 clock source as PCLK0 */
138 #define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Setting EPWM1 clock source as PCLK1 */
139
140 #define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting BPWM0 clock source as PCLK0 */
141 #define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting BPWM1 clock source as PCLK1 */
142
143 #define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as HXT */
144 #define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as PLL */
145 #define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as PCLK0 */
146 #define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting QSPI0 clock source as HIRC */
147
148 #define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HXT */
149 #define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL */
150 #define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK1 */
151 #define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HIRC */
152
153 #define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HXT */
154 #define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL */
155 #define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK0 */
156 #define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HIRC */
157
158 #define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HXT */
159 #define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL */
160 #define CLK_CLKSEL2_SPI2SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK1 */
161 #define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HIRC */
162
163 #define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HXT */
164 #define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PLL */
165 #define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK0 */
166 #define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HIRC */
167
168 #define CLK_CLKSEL2_UART0SEL_HXT (0x0UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Setting UART0 clock source as HXT */
169 #define CLK_CLKSEL2_UART0SEL_PLL (0x1UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Setting UART0 clock source as PLL */
170 #define CLK_CLKSEL2_UART0SEL_LXT (0x2UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Setting UART0 clock source as LXT */
171 #define CLK_CLKSEL2_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Setting UART0 clock source as HIRC */
172 #define CLK_CLKSEL2_UART0SEL_PCLK0 (0x4UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Setting UART0 clock source as PCLK0 */
173
174 #define CLK_CLKSEL2_UART1SEL_HXT (0x0UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Setting UART1 clock source as HXT */
175 #define CLK_CLKSEL2_UART1SEL_PLL (0x1UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Setting UART1 clock source as PLL */
176 #define CLK_CLKSEL2_UART1SEL_LXT (0x2UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Setting UART1 clock source as LXT */
177 #define CLK_CLKSEL2_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Setting UART1 clock source as HIRC */
178 #define CLK_CLKSEL2_UART1SEL_PCLK1 (0x4UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Setting UART1 clock source as PCLK1 */
179
180 #define CLK_CLKSEL2_UART2SEL_HXT (0x0UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Setting UART2 clock source as HXT */
181 #define CLK_CLKSEL2_UART2SEL_PLL (0x1UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Setting UART2 clock source as PLL */
182 #define CLK_CLKSEL2_UART2SEL_LXT (0x2UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Setting UART2 clock source as LXT */
183 #define CLK_CLKSEL2_UART2SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Setting UART2 clock source as HIRC */
184 #define CLK_CLKSEL2_UART2SEL_PCLK0 (0x4UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Setting UART2 clock source as PCLK0 */
185
186 #define CLK_CLKSEL2_UART3SEL_HXT (0x0UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Setting UART3 clock source as HXT */
187 #define CLK_CLKSEL2_UART3SEL_PLL (0x1UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Setting UART3 clock source as PLL */
188 #define CLK_CLKSEL2_UART3SEL_LXT (0x2UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Setting UART3 clock source as LXT */
189 #define CLK_CLKSEL2_UART3SEL_HIRC (0x3UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Setting UART3 clock source as HIRC */
190 #define CLK_CLKSEL2_UART3SEL_PCLK1 (0x4UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Setting UART3 clock source as PCLK1 */
191
192
193
194 /*---------------------------------------------------------------------------------------------------------*/
195 /* CLKSEL3 constant definitions. */
196 /*---------------------------------------------------------------------------------------------------------*/
197 #define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HXT */
198 #define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL */
199 #define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK0 */
200 #define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HIRC */
201
202 #define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as HXT */
203 #define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PLL */
204 #define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PCLK1 */
205 #define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as HIRC */
206
207 #define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as HXT */
208 #define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PLL */
209 #define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PCLK1 */
210 #define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as HIRC */
211
212 #define CLK_CLKSEL3_TMR4SEL_HXT (0x0UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as HXT */
213 #define CLK_CLKSEL3_TMR4SEL_LXT (0x1UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as LXT */
214 #define CLK_CLKSEL3_TMR4SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as PCLK0 */
215 #define CLK_CLKSEL3_TMR4SEL_EXT_TRG (0x3UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as external trigger */
216 #define CLK_CLKSEL3_TMR4SEL_MIRC (0x4UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as MIRC */
217 #define CLK_CLKSEL3_TMR4SEL_LIRC (0x5UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as LIRC */
218 #define CLK_CLKSEL3_TMR4SEL_HIRC (0x7UL<<CLK_CLKSEL3_TMR4SEL_Pos) /*!< Setting Timer 4 clock source as HIRC */
219
220 #define CLK_CLKSEL3_TMR5SEL_HXT (0x0UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as HXT */
221 #define CLK_CLKSEL3_TMR5SEL_LXT (0x1UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as LXT */
222 #define CLK_CLKSEL3_TMR5SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as PCLK0 */
223 #define CLK_CLKSEL3_TMR5SEL_EXT_TRG (0x3UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as external trigger */
224 #define CLK_CLKSEL3_TMR5SEL_MIRC (0x4UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as MIRC */
225 #define CLK_CLKSEL3_TMR5SEL_LIRC (0x5UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as LIRC */
226 #define CLK_CLKSEL3_TMR5SEL_HIRC (0x7UL<<CLK_CLKSEL3_TMR5SEL_Pos) /*!< Setting Timer 5 clock source as HIRC */
227
228 #define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as HXT */
229 #define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PLL */
230 #define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PCLK0 */
231 #define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as HIRC */
232
233 #define CLK_CLKSEL3_UART4SEL_HXT (0x0UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as HXT */
234 #define CLK_CLKSEL3_UART4SEL_PLL (0x1UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as PLL */
235 #define CLK_CLKSEL3_UART4SEL_LXT (0x2UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as LXT */
236 #define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as HIRC */
237 #define CLK_CLKSEL3_UART4SEL_PCLK0 (0x4UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as PCLK0 */
238
239 #define CLK_CLKSEL3_UART5SEL_HXT (0x0UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as HXT */
240 #define CLK_CLKSEL3_UART5SEL_PLL (0x1UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as PLL */
241 #define CLK_CLKSEL3_UART5SEL_LXT (0x2UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as LXT */
242 #define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as HIRC */
243 #define CLK_CLKSEL3_UART5SEL_PCLK1 (0x4UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as PCLK1 */
244
245 #define RTC_LXTCTL_RTCCKSEL_LXT (0x0UL<<RTC_LXTCTL_RTCCKSEL_Pos) /*!< Setting RTC clock source as LXT */
246 #define RTC_LXTCTL_RTCCKSEL_LIRC (0x1UL<<RTC_LXTCTL_RTCCKSEL_Pos) /*!< Setting RTC clock source as LIRC */
247
248
249 /*---------------------------------------------------------------------------------------------------------*/
250 /* CLKDIV0 constant definitions. */
251 /*---------------------------------------------------------------------------------------------------------*/
252 #define CLK_CLKDIV0_HCLK(x) (((x)-1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
253 #define CLK_CLKDIV0_USB(x) (((x)-1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 */
254 #define CLK_CLKDIV0_UART0(x) (((x)-1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 */
255 #define CLK_CLKDIV0_UART1(x) (((x)-1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 */
256 #define CLK_CLKDIV0_EADC(x) (((x)-1UL) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 */
257 #define CLK_CLKDIV0_SDH0(x) (((x)-1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 */
258
259
260 /*---------------------------------------------------------------------------------------------------------*/
261 /* CLKDIV1 constant definitions. */
262 /*---------------------------------------------------------------------------------------------------------*/
263 #define CLK_CLKDIV1_SC0(x) (((x)-1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */
264 #define CLK_CLKDIV1_SC1(x) (((x)-1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 */
265 #define CLK_CLKDIV1_SC2(x) (((x)-1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 */
266
267
268 /*---------------------------------------------------------------------------------------------------------*/
269 /* CLKDIV4 constant definitions. */
270 /*---------------------------------------------------------------------------------------------------------*/
271 #define CLK_CLKDIV4_UART2(x) (((x)-1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 */
272 #define CLK_CLKDIV4_UART3(x) (((x)-1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 */
273 #define CLK_CLKDIV4_UART4(x) (((x)-1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 */
274 #define CLK_CLKDIV4_UART5(x) (((x)-1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 */
275
276
277 /*---------------------------------------------------------------------------------------------------------*/
278 /* PLLCTL constant definitions. PLL = FIN * (2*NF) / NR / NO */
279 /*---------------------------------------------------------------------------------------------------------*/
280 #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 2MHz < FIN/NR < 8MHz */
281 #define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 2MHz < FIN/NR < 8MHz */
282
283 #define CLK_PLLCTL_NF(x) ((x)-2UL) /*!< x must be constant and 2 <= x <= 513. 96MHz < FIN*(2*NF)/NR < 200MHz */
284 #define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 2 <= x <= 33. 2MHz < FIN/NR < 8MHz */
285
286 #define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
287 #define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
288 #define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
289
290 #define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with HXT */
291 #define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with HIRC */
292
293 #define CLK_PLLCTL_64MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 64MHz PLL output with HXT */
294 #define CLK_PLLCTL_64MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 64Hz PLL output with HIRC */
295
296 #define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(14UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 84MHz PLL output with HXT */
297 #define CLK_PLLCTL_84MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(14UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 84Hz PLL output with HIRC */
298
299 #define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT */
300 #define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HIRC */
301
302 #define CLK_PLLCTL_128MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 128MHz PLL output with HXT */
303 #define CLK_PLLCTL_128MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 128MHz PLL output with HIRC */
304
305 #define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(12UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT */
306 #define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(12UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC */
307
308 #define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT */
309 #define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC */
310
311
312 /*---------------------------------------------------------------------------------------------------------*/
313 /* MODULE constant definitions. */
314 /*---------------------------------------------------------------------------------------------------------*/
315 /* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
316
317 #define MODULE_APBCLK(x) (((x) >>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
318 #define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
319 #define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index */
320 #define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index */
321 #define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */
322 #define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index */
323 #define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index */
324 #define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index */
325 #define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index */
326 #define NA MODULE_NoMsk /*!< Not Available */
327
328 #define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
329 #define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
330 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index */
331 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index */
332 #define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */
333 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index */
334 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index */
335 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
336
337
338 /* AHBCLK */
339 #define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA0CKEN_Pos)|\
340 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
341 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
342
343 #define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA1CKEN_Pos)|\
344 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
345 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
346
347 #define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_ISPCKEN_Pos)|\
348 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
349 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */
350
351 #define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EBICKEN_Pos)|\
352 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
353 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */
354
355 #define EXST_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EXSTCKEN_Pos)|\
356 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
357 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EXST Module */
358
359 #define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SDH0CKEN_Pos)|\
360 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
361 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(24UL))/*!< SDH0 Module */
362
363 #define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\
364 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
365 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
366
367 #define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\
368 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
369 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */
370
371 #define KS_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_KSCKEN_Pos)|\
372 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
373 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< KS Module */
374
375 #define TRACE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_TRACECKEN_Pos)|\
376 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
377 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRACE Module */
378
379 #define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_FMCIDLE_Pos)|\
380 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
381 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */
382
383 #define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\
384 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
385 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */
386
387 #define SRAM0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM0CKEN_Pos)|\
388 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
389 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM0 Module */
390
391 #define SRAM1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM1CKEN_Pos)|\
392 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
393 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM1 Module */
394
395 #define SRAM2_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM2CKEN_Pos)|\
396 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
397 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM2 Module */
398
399 #define GPA_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPACKEN_Pos)|\
400 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
401 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPA Module */
402
403 #define GPB_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPBCKEN_Pos)|\
404 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
405 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPB Module */
406
407 #define GPC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPCCKEN_Pos)|\
408 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
409 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPC Module */
410
411 #define GPD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPDCKEN_Pos)|\
412 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
413 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPD Module */
414
415 #define GPE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPECKEN_Pos)|\
416 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
417 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPE Module */
418
419 #define GPF_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPFCKEN_Pos)|\
420 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
421 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPF Module */
422
423 #define GPG_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPGCKEN_Pos)|\
424 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
425 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPG Module */
426
427 #define GPH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPHCKEN_Pos)|\
428 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
429 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPH Module */
430
431 /* APBCLK0 */
432 #define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
433 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
434 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */
435
436 #define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
437 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
438 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */
439
440 #define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\
441 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
442 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */
443
444 #define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\
445 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
446 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */
447
448 #define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\
449 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
450 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */
451
452 #define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\
453 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
454 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */
455
456 #define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\
457 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
458 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */
459
460 #define TMR4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR4CKEN_Pos) |\
461 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(8UL)|\
462 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR4 Module */
463
464 #define TMR5_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR5CKEN_Pos) |\
465 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
466 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR5 Module */
467
468 #define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\
469 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
470 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */
471
472 #define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\
473 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
474 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */
475
476 #define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\
477 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
478 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */
479
480 #define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\
481 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
482 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */
483
484 #define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\
485 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
486 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */
487
488 #define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\
489 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
490 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */
491
492 #define SPI0_MODULE (MODULE_APBCLK_ENC(1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\
493 MODULE_CLKSEL_ENC(2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
494 MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */
495
496 #define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\
497 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\
498 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */
499
500 #define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\
501 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\
502 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */
503
504 #define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\
505 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
506 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */
507
508 #define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\
509 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
510 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */
511
512 #define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\
513 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
514 MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */
515
516 #define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\
517 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
518 MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */
519
520 #define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\
521 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
522 MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */
523
524 #define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\
525 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
526 MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */
527
528 #define TAMPER_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TAMPERCKEN_Pos)|\
529 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\
530 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TAMPER Module */
531
532 #define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\
533 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
534 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */
535
536 #define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\
537 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
538 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */
539
540 #define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\
541 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
542 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(4UL)) /*!< USBD Module */
543
544 #define EADC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADCCKEN_Pos)|\
545 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\
546 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC Module */
547
548 #define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\
549 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
550 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< I2S0 Module */
551
552 #define EWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\
553 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
554 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< EWDT Module */
555
556 #define EWWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\
557 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\
558 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EWWDT Module */
559
560
561 /* APBCLK1 */
562 #define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\
563 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
564 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */
565
566 #define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\
567 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
568 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */
569
570 #define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\
571 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
572 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */
573
574 #define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos) |\
575 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
576 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */
577
578 #define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\
579 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
580 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */
581
582 #define USCI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI1CKEN_Pos)|\
583 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
584 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */
585
586 #define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\
587 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
588 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */
589
590 #define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\
591 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
592 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */
593
594 #define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\
595 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
596 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */
597
598 #define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\
599 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
600 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */
601
602 #define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\
603 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
604 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */
605
606 #define QEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI0CKEN_Pos)|\
607 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
608 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI0 Module */
609
610 #define QEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI1CKEN_Pos)|\
611 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
612 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI1 Module */
613
614 #define LCD_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCKEN_Pos)|\
615 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(2UL)|\
616 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< LCD Module */
617
618 #define LCDCP_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCPCKEN_Pos)|\
619 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(3UL)|\
620 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< LCDCP Module */
621
622 #define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\
623 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
624 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */
625
626 #define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\
627 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
628 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */
629
630 #define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\
631 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
632 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */
633
634
635 /*---------------------------------------------------------------------------------------------------------*/
636 /* PDMSEL constant definitions. */
637 /*---------------------------------------------------------------------------------------------------------*/
638 #define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Power-down mode */
639 #define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Low leakage Power-down mode */
640 #define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Fast Wake-up Power-down mode */
641 #define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Ultra Low leakage Power-down mode */
642 #define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Standby Power-down mode */
643 #define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Deep Power-down mode */
644
645 /*---------------------------------------------------------------------------------------------------------*/
646 /* WKTMRIS constant definitions. */
647 /*---------------------------------------------------------------------------------------------------------*/
648 #define CLK_PMUCTL_WKTMRIS_410 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 410 LIRC clocks (12.8 ms) */
649 #define CLK_PMUCTL_WKTMRIS_819 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 819 LIRC clocks (25.6 ms) */
650 #define CLK_PMUCTL_WKTMRIS_1638 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1638 LIRC clocks (51.2 ms) */
651 #define CLK_PMUCTL_WKTMRIS_3277 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 3277 LIRC clocks (102.4ms) */
652 #define CLK_PMUCTL_WKTMRIS_13107 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 13107 LIRC clocks (409.6ms) */
653 #define CLK_PMUCTL_WKTMRIS_26214 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 26214 LIRC clocks (819.2ms) */
654 #define CLK_PMUCTL_WKTMRIS_52429 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 52429 LIRC clocks (1638.4ms) */
655 #define CLK_PMUCTL_WKTMRIS_209715 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 209715 LIRC clocks (6553.6ms) */
656
657 /*---------------------------------------------------------------------------------------------------------*/
658 /* SWKDBCLKSEL constant definitions. */
659 /*---------------------------------------------------------------------------------------------------------*/
660 #define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */
661 #define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */
662 #define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */
663 #define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */
664 #define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */
665 #define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */
666 #define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */
667 #define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */
668 #define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */
669 #define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */
670 #define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */
671 #define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */
672 #define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */
673 #define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */
674 #define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */
675 #define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */
676
677 /*---------------------------------------------------------------------------------------------------------*/
678 /* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
679 /*---------------------------------------------------------------------------------------------------------*/
680 #define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin (GPC.0) at Deep Power-down mode \hideinitializer */
681 #define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
682 #define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
683 #define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) both edge at Deep Power-down mode \hideinitializer */
684
685 #define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
686 #define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
687 #define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
688 #define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */
689
690 #define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
691 #define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */
692 #define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */
693 #define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */
694
695 #define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
696 #define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */
697 #define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */
698 #define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */
699
700 #define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
701 #define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */
702 #define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */
703 #define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */
704
705 #define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
706 #define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */
707 #define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */
708 #define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */
709
710 /*---------------------------------------------------------------------------------------------------------*/
711 /* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
712 /*---------------------------------------------------------------------------------------------------------*/
713 #define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up */
714 #define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */
715 #define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */
716 #define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function */
717 #define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function */
718
719
720 /**@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
721
722 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
723 @{
724 */
725
726 /**
727 * @brief Disable Wake-up Timer
728 * @param None
729 * @return None
730 * @details This macro disables Wake-up timer at Standby or Deep Power-down mode.
731 */
732 #define CLK_DISABLE_WKTMR() \
733 do{ \
734 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
735 CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk; \
736 }while(0)
737
738 /**
739 * @brief Enable Wake-up Timer
740 * @param None
741 * @return None
742 * @details This macro enables Wake-up timer at Standby or Deep Power-down mode.
743 */
744 #define CLK_ENABLE_WKTMR() \
745 do{ \
746 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
747 CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk; \
748 }while(0)
749
750 /**
751 * @brief Disable DPD Mode Wake-up Pin
752 * @param None
753 * @return None
754 * @details This macro disables Wake-up pin at Deep Power-down mode.
755 */
756 #define CLK_DISABLE_DPDWKPIN() \
757 do{ \
758 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
759 CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk; \
760 }while(0)
761
762 /**
763 * @brief Disable DPD Mode Wake-up Pin 0
764 * @param None
765 * @return None
766 * @details This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode.
767 */
768 #define CLK_DISABLE_DPDWKPIN0() \
769 do{ \
770 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
771 CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN0EN_Msk; \
772 }while(0)
773
774 /**
775 * @brief Disable DPD Mode Wake-up Pin 1
776 * @param None
777 * @return None
778 * @details This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode.
779 */
780 #define CLK_DISABLE_DPDWKPIN1() \
781 do{ \
782 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
783 CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN1EN_Msk; \
784 }while(0)
785
786 /**
787 * @brief Disable DPD Mode Wake-up Pin 2
788 * @param None
789 * @return None
790 * @details This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode.
791 */
792 #define CLK_DISABLE_DPDWKPIN2() \
793 do{ \
794 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
795 CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN2EN_Msk; \
796 }while(0)
797
798 /**
799 * @brief Disable DPD Mode Wake-up Pin 3
800 * @param None
801 * @return None
802 * @details This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode.
803 */
804 #define CLK_DISABLE_DPDWKPIN3() \
805 do{ \
806 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
807 CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN3EN_Msk; \
808 }while(0)
809
810 /**
811 * @brief Disable DPD Mode Wake-up Pin 4
812 * @param None
813 * @return None
814 * @details This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode.
815 */
816 #define CLK_DISABLE_DPDWKPIN4() \
817 do{ \
818 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
819 CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN4EN_Msk; \
820 }while(0)
821
822 /**
823 * @brief Disable SPD Mode ACMP Wake-up
824 * @param None
825 * @return None
826 * @details This macro disables ACMP wake-up at Standby Power-down mode.
827 */
828 #define CLK_DISABLE_SPDACMP() \
829 do{ \
830 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
831 CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk; \
832 }while(0)
833
834 /**
835 * @brief Enable SPD Mode ACMP Wake-up
836 * @param None
837 * @return None
838 * @details This macro enables ACMP wake-up at Standby Power-down mode.
839 */
840 #define CLK_ENABLE_SPDACMP() \
841 do{ \
842 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
843 CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk; \
844 }while(0)
845
846 /**
847 * @brief Disable SPD and DPD Mode RTC Wake-up
848 * @param None
849 * @return None
850 * @details This macro disables RTC Wake-up at Standby or Deep Power-down mode.
851 */
852 #define CLK_DISABLE_RTCWK() \
853 do{ \
854 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
855 CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk; \
856 }while(0)
857
858 /**
859 * @brief Enable SPD and DPD Mode RTC Wake-up
860 * @param None
861 * @return None
862 * @details This macro enables RTC Wake-up at Standby or Deep Power-down mode.
863 */
864 #define CLK_ENABLE_RTCWK() \
865 do{ \
866 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
867 CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk; \
868 }while(0)
869
870 /**
871 * @brief Set Wake-up Timer Time-out Interval
872 *
873 * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
874 * - \ref CLK_PMUCTL_WKTMRIS_410
875 * - \ref CLK_PMUCTL_WKTMRIS_819
876 * - \ref CLK_PMUCTL_WKTMRIS_1638
877 * - \ref CLK_PMUCTL_WKTMRIS_3277
878 * - \ref CLK_PMUCTL_WKTMRIS_13107
879 * - \ref CLK_PMUCTL_WKTMRIS_26214
880 * - \ref CLK_PMUCTL_WKTMRIS_52429
881 * - \ref CLK_PMUCTL_WKTMRIS_209715
882 *
883 * @return None
884 *
885 * @details This function set Wake-up Timer Time-out Interval.
886 *
887 *
888 */
889 #define CLK_SET_WKTMR_INTERVAL(u32Interval) \
890 do{ \
891 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
892 CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval); \
893 }while(0)
894
895 /**
896 * @brief Set De-bounce Sampling Cycle Time
897 *
898 * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
899 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
900 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
901 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
902 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
903 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
904 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
905 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
906 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
907 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
908 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
909 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
910 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
911 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
912 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
913 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
914 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
915 *
916 * @return None
917 *
918 * @details This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up.
919 *
920 *
921 */
922 #define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
923
924 /**
925 * @brief Disable SPD Mode Tamper Wake-up
926 * @param None
927 * @return None
928 * @details This macro disables tamper Wake-up at Standby Power-down mode.
929 */
930 #define CLK_DISABLE_SPDTAMPER() \
931 do{ \
932 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
933 CLK->PMUCTL &= ~CLK_PMUCTL_TAMPERWK_Msk; \
934 }while(0)
935
936 /**
937 * @brief Enable SPD and DPD Mode RTC Wake-up
938 * @param None
939 * @return None
940 * @details This macro enables tamper Wake-up at Standby Power-down mode.
941 */
942 #define CLK_ENABLE_SPDTAMPER() \
943 do{ \
944 while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
945 CLK->PMUCTL |= CLK_PMUCTL_TAMPERWK_Msk; \
946 }while(0)
947
948
949 /*---------------------------------------------------------------------------------------------------------*/
950 /* static inline functions */
951 /*---------------------------------------------------------------------------------------------------------*/
952 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
953 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
954 __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
955
956
957 /**
958 * @brief This function execute delay function.
959 * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex:
960 * 96MHz => 174762us, 84MHz => 199728us,
961 * 64MHz => 262143us, 48MHz => 349525us ...
962 * @return None
963 * @details Use the SysTick to generate the delay time and the UNIT is in us.
964 * The SysTick clock source is from HCLK, i.e the same as system core clock.
965 * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
966 */
CLK_SysTickDelay(uint32_t us)967 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
968 {
969 SysTick->LOAD = us * CyclesPerUs;
970 SysTick->VAL = (0x0UL);
971 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
972
973 /* Waiting for down-count to zero */
974 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
975 {
976 }
977
978 /* Disable SysTick counter */
979 SysTick->CTRL = 0UL;
980 }
981
982 /**
983 * @brief This function execute long delay function.
984 * @param[in] us Delay time.
985 * @return None
986 * @details Use the SysTick to generate the long delay time and the UNIT is in us.
987 * The SysTick clock source is from HCLK, i.e the same as system core clock.
988 * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
989 */
CLK_SysTickLongDelay(uint32_t us)990 __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
991 {
992 uint32_t u32Delay;
993
994 /* It should <= 65536us for each delay loop */
995 u32Delay = 65536UL;
996
997 do
998 {
999 if(us > u32Delay)
1000 {
1001 us -= u32Delay;
1002 }
1003 else
1004 {
1005 u32Delay = us;
1006 us = 0UL;
1007 }
1008
1009 SysTick->LOAD = u32Delay * CyclesPerUs;
1010 SysTick->VAL = (0x0UL);
1011 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
1012
1013 /* Waiting for down-count to zero */
1014 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
1015
1016 /* Disable SysTick counter */
1017 SysTick->CTRL = 0UL;
1018
1019 }
1020 while(us > 0UL);
1021
1022 }
1023
1024
1025 void CLK_DisableCKO(void);
1026 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
1027 void CLK_PowerDown(void);
1028 void CLK_Idle(void);
1029 uint32_t CLK_GetHXTFreq(void);
1030 uint32_t CLK_GetLXTFreq(void);
1031 uint32_t CLK_GetHCLKFreq(void);
1032 uint32_t CLK_GetPCLK0Freq(void);
1033 uint32_t CLK_GetPCLK1Freq(void);
1034 uint32_t CLK_GetCPUFreq(void);
1035 uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
1036 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
1037 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
1038 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
1039 void CLK_EnableXtalRC(uint32_t u32ClkMask);
1040 void CLK_DisableXtalRC(uint32_t u32ClkMask);
1041 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
1042 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
1043 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
1044 void CLK_DisablePLL(void);
1045 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
1046 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
1047 void CLK_DisableSysTick(void);
1048 void CLK_SetPowerDownMode(uint32_t u32PDMode);
1049 void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
1050 uint32_t CLK_GetPMUWKSrc(void);
1051 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
1052 uint32_t CLK_GetPLLClockFreq(void);
1053 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
1054 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
1055
1056
1057 /**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
1058
1059 /**@}*/ /* end of group CLK_Driver */
1060
1061 /**@}*/ /* end of group Standard_Driver */
1062
1063
1064 #ifdef __cplusplus
1065 }
1066 #endif
1067
1068
1069 #endif /* __CLK_H__ */
1070
