1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_fmpsmbus.h 4 * @author MCD Application Team 5 * @brief Header file of FMPSMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_FMPSMBUS_H 21 #define STM32F4xx_HAL_FMPSMBUS_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMPI2C_CR1_PE) 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FMPSMBUS 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types 41 * @{ 42 */ 43 44 /** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition 45 * @brief FMPSMBUS Configuration Structure definition 46 * @{ 47 */ 48 typedef struct 49 { 50 uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. 51 This parameter calculated by referring to FMPSMBUS initialization section 52 in Reference manual */ 53 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 54 This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ 55 56 uint32_t OwnAddress1; /*!< Specifies the first device own address. 57 This parameter can be a 7-bit or 10-bit address. */ 58 59 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 60 This parameter can be a value of @ref FMPSMBUS_addressing_mode */ 61 62 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 63 This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ 64 65 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 66 This parameter can be a 7-bit address. */ 67 68 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 69 if dual addressing mode is selected 70 This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ 71 72 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 73 This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ 74 75 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 76 This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ 77 78 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 79 This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ 80 81 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 82 This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ 83 84 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. 85 (Enable bits and different timeout values) 86 This parameter calculated by referring to FMPSMBUS initialization section 87 in Reference manual */ 88 } FMPSMBUS_InitTypeDef; 89 /** 90 * @} 91 */ 92 93 /** @defgroup HAL_state_definition HAL state definition 94 * @brief HAL State definition 95 * @{ 96 */ 97 #define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ 98 #define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ 99 #define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ 100 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 101 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 102 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 103 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 104 #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 105 #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 106 #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition 112 * @brief FMPSMBUS Error Code definition 113 * @{ 114 */ 115 #define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 116 #define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 117 #define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 118 #define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 119 #define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 120 #define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 121 #define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 122 #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 123 #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 124 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 125 #define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 126 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 127 #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 128 /** 129 * @} 130 */ 131 132 /** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition 133 * @brief FMPSMBUS handle Structure definition 134 * @{ 135 */ 136 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 137 typedef struct __FMPSMBUS_HandleTypeDef 138 #else 139 typedef struct 140 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 141 { 142 FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ 143 144 FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ 145 146 uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ 147 148 uint16_t XferSize; /*!< FMPSMBUS transfer size */ 149 150 __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ 151 152 __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ 153 154 __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ 155 156 HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ 157 158 __IO uint32_t State; /*!< FMPSMBUS communication state */ 159 160 __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ 161 162 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 163 void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 164 /*!< FMPSMBUS Master Tx Transfer completed callback */ 165 void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 166 /*!< FMPSMBUS Master Rx Transfer completed callback */ 167 void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 168 /*!< FMPSMBUS Slave Tx Transfer completed callback */ 169 void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 170 /*!< FMPSMBUS Slave Rx Transfer completed callback */ 171 void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 172 /*!< FMPSMBUS Listen Complete callback */ 173 void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 174 /*!< FMPSMBUS Error callback */ 175 176 void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 177 /*!< FMPSMBUS Slave Address Match callback */ 178 179 void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 180 /*!< FMPSMBUS Msp Init callback */ 181 void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 182 /*!< FMPSMBUS Msp DeInit callback */ 183 184 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 185 } FMPSMBUS_HandleTypeDef; 186 187 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 188 /** 189 * @brief HAL FMPSMBUS Callback ID enumeration definition 190 */ 191 typedef enum 192 { 193 HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ 194 HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ 195 HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ 196 HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ 197 HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ 198 HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ 199 200 HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ 201 HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ 202 203 } HAL_FMPSMBUS_CallbackIDTypeDef; 204 205 /** 206 * @brief HAL FMPSMBUS Callback pointer definition 207 */ 208 typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); 209 /*!< pointer to an FMPSMBUS callback function */ 210 typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, 211 uint16_t AddrMatchCode); 212 /*!< pointer to an FMPSMBUS Address Match callback function */ 213 214 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 215 /** 216 * @} 217 */ 218 219 /** 220 * @} 221 */ 222 /* Exported constants --------------------------------------------------------*/ 223 224 /** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants 225 * @{ 226 */ 227 228 /** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter 229 * @{ 230 */ 231 #define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) 232 #define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF 233 /** 234 * @} 235 */ 236 237 /** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode 238 * @{ 239 */ 240 #define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 241 #define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 242 /** 243 * @} 244 */ 245 246 /** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode 247 * @{ 248 */ 249 250 #define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) 251 #define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN 252 /** 253 * @} 254 */ 255 256 /** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks 257 * @{ 258 */ 259 260 #define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) 261 #define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) 262 #define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) 263 #define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) 264 #define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) 265 #define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) 266 #define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) 267 #define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) 268 /** 269 * @} 270 */ 271 272 273 /** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode 274 * @{ 275 */ 276 #define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) 277 #define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN 278 /** 279 * @} 280 */ 281 282 /** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode 283 * @{ 284 */ 285 #define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) 286 #define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH 287 /** 288 * @} 289 */ 290 291 /** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode 292 * @{ 293 */ 294 #define FMPSMBUS_PEC_DISABLE (0x00000000U) 295 #define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN 296 /** 297 * @} 298 */ 299 300 /** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode 301 * @{ 302 */ 303 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN 304 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) 305 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN 306 /** 307 * @} 308 */ 309 310 /** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition 311 * @{ 312 */ 313 314 #define FMPSMBUS_SOFTEND_MODE (0x00000000U) 315 #define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD 316 #define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND 317 #define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE 318 /** 319 * @} 320 */ 321 322 /** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition 323 * @{ 324 */ 325 326 #define FMPSMBUS_NO_STARTSTOP (0x00000000U) 327 #define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) 328 #define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) 329 #define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) 330 /** 331 * @} 332 */ 333 334 /** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition 335 * @{ 336 */ 337 338 /* List of XferOptions in usage of : 339 * 1- Restart condition when direction change 340 * 2- No Restart condition in other use cases 341 */ 342 #define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE 343 #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) 344 #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 345 #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 346 #define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) 347 #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 348 #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 349 350 /* List of XferOptions in usage of : 351 * 1- Restart condition in all use cases (direction change or not) 352 */ 353 #define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 354 #define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 355 #define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 356 #define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 357 /** 358 * @} 359 */ 360 361 /** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition 362 * @brief FMPSMBUS Interrupt definition 363 * Elements values convention: 0xXXXXXXXX 364 * - XXXXXXXX : Interrupt control mask 365 * @{ 366 */ 367 #define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE 368 #define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE 369 #define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE 370 #define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE 371 #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE 372 #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE 373 #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE 374 #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ 375 FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) 376 #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ 377 FMPSMBUS_IT_RXI) 378 #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) 379 #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) 380 /** 381 * @} 382 */ 383 384 /** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition 385 * @brief Flag definition 386 * Elements values convention: 0xXXXXYYYY 387 * - XXXXXXXX : Flag mask 388 * @{ 389 */ 390 391 #define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE 392 #define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS 393 #define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE 394 #define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR 395 #define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF 396 #define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF 397 #define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC 398 #define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR 399 #define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR 400 #define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO 401 #define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR 402 #define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR 403 #define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT 404 #define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT 405 #define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY 406 #define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR 407 /** 408 * @} 409 */ 410 411 /** 412 * @} 413 */ 414 415 /* Exported macros ------------------------------------------------------------*/ 416 /** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros 417 * @{ 418 */ 419 420 /** @brief Reset FMPSMBUS handle state. 421 * @param __HANDLE__ specifies the FMPSMBUS Handle. 422 * @retval None 423 */ 424 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 425 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 426 (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ 427 (__HANDLE__)->MspInitCallback = NULL; \ 428 (__HANDLE__)->MspDeInitCallback = NULL; \ 429 } while(0) 430 #else 431 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) 432 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 433 434 /** @brief Enable the specified FMPSMBUS interrupts. 435 * @param __HANDLE__ specifies the FMPSMBUS Handle. 436 * @param __INTERRUPT__ specifies the interrupt source to enable. 437 * This parameter can be one of the following values: 438 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 439 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 440 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 441 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 442 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 443 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 444 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 445 * 446 * @retval None 447 */ 448 #define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 449 450 /** @brief Disable the specified FMPSMBUS interrupts. 451 * @param __HANDLE__ specifies the FMPSMBUS Handle. 452 * @param __INTERRUPT__ specifies the interrupt source to disable. 453 * This parameter can be one of the following values: 454 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 455 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 456 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 457 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 458 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 459 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 460 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 461 * 462 * @retval None 463 */ 464 #define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 465 466 /** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not. 467 * @param __HANDLE__ specifies the FMPSMBUS Handle. 468 * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. 469 * This parameter can be one of the following values: 470 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 471 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 472 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 473 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 474 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 475 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 476 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 477 * 478 * @retval The new state of __IT__ (SET or RESET). 479 */ 480 #define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 481 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 482 483 /** @brief Check whether the specified FMPSMBUS flag is set or not. 484 * @param __HANDLE__ specifies the FMPSMBUS Handle. 485 * @param __FLAG__ specifies the flag to check. 486 * This parameter can be one of the following values: 487 * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty 488 * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status 489 * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty 490 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 491 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 492 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 493 * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) 494 * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload 495 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 496 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 497 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 498 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 499 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 500 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 501 * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy 502 * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) 503 * 504 * @retval The new state of __FLAG__ (SET or RESET). 505 */ 506 #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) 507 #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 508 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 509 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 510 511 /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. 512 * @param __HANDLE__ specifies the FMPSMBUS Handle. 513 * @param __FLAG__ specifies the flag to clear. 514 * This parameter can be any combination of the following values: 515 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 516 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 517 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 518 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 519 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 520 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 521 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 522 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 523 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 524 * 525 * @retval None 526 */ 527 #define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 528 529 /** @brief Enable the specified FMPSMBUS peripheral. 530 * @param __HANDLE__ specifies the FMPSMBUS Handle. 531 * @retval None 532 */ 533 #define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 534 535 /** @brief Disable the specified FMPSMBUS peripheral. 536 * @param __HANDLE__ specifies the FMPSMBUS Handle. 537 * @retval None 538 */ 539 #define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 540 541 /** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode. 542 * @param __HANDLE__ specifies the FMPSMBUS Handle. 543 * @retval None 544 */ 545 #define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) 546 547 /** 548 * @} 549 */ 550 551 552 /* Private constants ---------------------------------------------------------*/ 553 554 /* Private macros ------------------------------------------------------------*/ 555 /** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros 556 * @{ 557 */ 558 559 #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ 560 ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) 561 562 #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 563 564 #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ 565 ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) 566 567 #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ 568 ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) 569 570 #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ 571 ((MASK) == FMPSMBUS_OA2_MASK01) || \ 572 ((MASK) == FMPSMBUS_OA2_MASK02) || \ 573 ((MASK) == FMPSMBUS_OA2_MASK03) || \ 574 ((MASK) == FMPSMBUS_OA2_MASK04) || \ 575 ((MASK) == FMPSMBUS_OA2_MASK05) || \ 576 ((MASK) == FMPSMBUS_OA2_MASK06) || \ 577 ((MASK) == FMPSMBUS_OA2_MASK07)) 578 579 #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ 580 ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) 581 582 #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ 583 ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) 584 585 #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ 586 ((PEC) == FMPSMBUS_PEC_ENABLE)) 587 588 #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ 589 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ 590 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) 591 592 #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ 593 ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ 594 ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ 595 ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ 596 ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 597 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 598 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ 599 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ 600 FMPSMBUS_RELOAD_MODE ))) 601 602 603 #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ 604 ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ 605 ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ 606 ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) 607 608 609 #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 610 ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ 611 ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ 612 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 613 ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ 614 ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ 615 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 616 ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) 617 618 #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ 619 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 620 ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ 621 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 622 623 #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 624 (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ 625 FMPI2C_CR1_PECEN))) 626 #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 627 (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ 628 FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ 629 FMPI2C_CR2_RD_WRN))) 630 631 #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ 632 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ 633 (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ 634 (~FMPI2C_CR2_RD_WRN)) : \ 635 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 636 (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ 637 (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) 638 639 #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) 640 #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) 641 #define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) 642 #define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) 643 #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) 644 645 #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 646 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 647 #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 648 649 #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 650 #define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 651 652 /** 653 * @} 654 */ 655 656 /* Include FMPSMBUS HAL Extended module */ 657 #include "stm32f4xx_hal_fmpsmbus_ex.h" 658 659 /* Exported functions --------------------------------------------------------*/ 660 /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions 661 * @{ 662 */ 663 664 /** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 665 * @{ 666 */ 667 668 /* Initialization and de-initialization functions ****************************/ 669 HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); 670 HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 671 void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 672 void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 673 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); 674 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); 675 676 /* Callbacks Register/UnRegister functions ***********************************/ 677 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 678 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 679 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, 680 pFMPSMBUS_CallbackTypeDef pCallback); 681 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 682 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); 683 684 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 685 pFMPSMBUS_AddrCallbackTypeDef pCallback); 686 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 687 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 688 /** 689 * @} 690 */ 691 692 /** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions 693 * @{ 694 */ 695 696 /* IO operation functions *****************************************************/ 697 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 698 * @{ 699 */ 700 /******* Blocking mode: Polling */ 701 HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, 702 uint32_t Timeout); 703 /** 704 * @} 705 */ 706 707 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 708 * @{ 709 */ 710 /******* Non-Blocking mode: Interrupt */ 711 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 712 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 713 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 714 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 715 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); 716 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 717 uint32_t XferOptions); 718 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 719 uint32_t XferOptions); 720 721 HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 722 HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 723 HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 724 HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 725 /** 726 * @} 727 */ 728 729 /** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 730 * @{ 731 */ 732 /******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 733 void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 734 void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 735 void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 736 void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 737 void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 738 void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 739 void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 740 void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 741 void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 742 743 /** 744 * @} 745 */ 746 747 /** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 748 * @{ 749 */ 750 751 /* Peripheral State and Errors functions **************************************************/ 752 uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); 753 uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); 754 755 /** 756 * @} 757 */ 758 759 /** 760 * @} 761 */ 762 763 /* Private Functions ---------------------------------------------------------*/ 764 /** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions 765 * @{ 766 */ 767 /* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ 768 /** 769 * @} 770 */ 771 772 /** 773 * @} 774 */ 775 776 /** 777 * @} 778 */ 779 780 /** 781 * @} 782 */ 783 784 #endif /* FMPI2C_CR1_PE */ 785 #ifdef __cplusplus 786 } 787 #endif 788 789 790 #endif /* STM32F4xx_HAL_FMPSMBUS_H */ 791
