1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_fmpi2c.h 4 * @author MCD Application Team 5 * @brief Header file of FMPI2C HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_FMPI2C_H 21 #define STM32F4xx_HAL_FMPI2C_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMPI2C_CR1_PE) 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FMPI2C 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types 41 * @{ 42 */ 43 44 /** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition 45 * @brief FMPI2C Configuration Structure definition 46 * @{ 47 */ 48 typedef struct 49 { 50 uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value. 51 This parameter calculated by referring to FMPI2C initialization section 52 in Reference manual */ 53 54 uint32_t OwnAddress1; /*!< Specifies the first device own address. 55 This parameter can be a 7-bit or 10-bit address. */ 56 57 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. 58 This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */ 59 60 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 61 This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */ 62 63 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 64 This parameter can be a 7-bit address. */ 65 66 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing 67 mode is selected. 68 This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */ 69 70 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 71 This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */ 72 73 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 74 This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ 75 76 } FMPI2C_InitTypeDef; 77 78 /** 79 * @} 80 */ 81 82 /** @defgroup HAL_state_structure_definition HAL state structure definition 83 * @brief HAL State structure definition 84 * @note HAL FMPI2C State value coding follow below described bitmap :\n 85 * b7-b6 Error information\n 86 * 00 : No Error\n 87 * 01 : Abort (Abort user request on going)\n 88 * 10 : Timeout\n 89 * 11 : Error\n 90 * b5 Peripheral initialization status\n 91 * 0 : Reset (peripheral not initialized)\n 92 * 1 : Init done (peripheral initialized and ready to use. HAL FMPI2C Init function called)\n 93 * b4 (not used)\n 94 * x : Should be set to 0\n 95 * b3\n 96 * 0 : Ready or Busy (No Listen mode ongoing)\n 97 * 1 : Listen (peripheral in Address Listen Mode)\n 98 * b2 Intrinsic process state\n 99 * 0 : Ready\n 100 * 1 : Busy (peripheral busy with some configuration or internal operations)\n 101 * b1 Rx state\n 102 * 0 : Ready (no Rx operation ongoing)\n 103 * 1 : Busy (Rx operation ongoing)\n 104 * b0 Tx state\n 105 * 0 : Ready (no Tx operation ongoing)\n 106 * 1 : Busy (Tx operation ongoing) 107 * @{ 108 */ 109 typedef enum 110 { 111 HAL_FMPI2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 112 HAL_FMPI2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ 113 HAL_FMPI2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ 114 HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ 115 HAL_FMPI2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 116 HAL_FMPI2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ 117 HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission 118 process is ongoing */ 119 HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception 120 process is ongoing */ 121 HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ 122 HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ 123 HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */ 124 125 } HAL_FMPI2C_StateTypeDef; 126 127 /** 128 * @} 129 */ 130 131 /** @defgroup HAL_mode_structure_definition HAL mode structure definition 132 * @brief HAL Mode structure definition 133 * @note HAL FMPI2C Mode value coding follow below described bitmap :\n 134 * b7 (not used)\n 135 * x : Should be set to 0\n 136 * b6\n 137 * 0 : None\n 138 * 1 : Memory (HAL FMPI2C communication is in Memory Mode)\n 139 * b5\n 140 * 0 : None\n 141 * 1 : Slave (HAL FMPI2C communication is in Slave Mode)\n 142 * b4\n 143 * 0 : None\n 144 * 1 : Master (HAL FMPI2C communication is in Master Mode)\n 145 * b3-b2-b1-b0 (not used)\n 146 * xxxx : Should be set to 0000 147 * @{ 148 */ 149 typedef enum 150 { 151 HAL_FMPI2C_MODE_NONE = 0x00U, /*!< No FMPI2C communication on going */ 152 HAL_FMPI2C_MODE_MASTER = 0x10U, /*!< FMPI2C communication is in Master Mode */ 153 HAL_FMPI2C_MODE_SLAVE = 0x20U, /*!< FMPI2C communication is in Slave Mode */ 154 HAL_FMPI2C_MODE_MEM = 0x40U /*!< FMPI2C communication is in Memory Mode */ 155 156 } HAL_FMPI2C_ModeTypeDef; 157 158 /** 159 * @} 160 */ 161 162 /** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition 163 * @brief FMPI2C Error Code definition 164 * @{ 165 */ 166 #define HAL_FMPI2C_ERROR_NONE (0x00000000U) /*!< No error */ 167 #define HAL_FMPI2C_ERROR_BERR (0x00000001U) /*!< BERR error */ 168 #define HAL_FMPI2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 169 #define HAL_FMPI2C_ERROR_AF (0x00000004U) /*!< ACKF error */ 170 #define HAL_FMPI2C_ERROR_OVR (0x00000008U) /*!< OVR error */ 171 #define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ 172 #define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 173 #define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ 174 #define HAL_FMPI2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ 175 #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) 176 #define HAL_FMPI2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 177 #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ 178 #define HAL_FMPI2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 179 /** 180 * @} 181 */ 182 183 /** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition 184 * @brief FMPI2C handle Structure definition 185 * @{ 186 */ 187 typedef struct __FMPI2C_HandleTypeDef 188 { 189 FMPI2C_TypeDef *Instance; /*!< FMPI2C registers base address */ 190 191 FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */ 192 193 uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */ 194 195 uint16_t XferSize; /*!< FMPI2C transfer size */ 196 197 __IO uint16_t XferCount; /*!< FMPI2C transfer counter */ 198 199 __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can 200 be a value of @ref FMPI2C_XFEROPTIONS */ 201 202 __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */ 203 204 HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); 205 /*!< FMPI2C transfer IRQ handler function pointer */ 206 207 DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */ 208 209 DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */ 210 211 HAL_LockTypeDef Lock; /*!< FMPI2C locking object */ 212 213 __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */ 214 215 __IO HAL_FMPI2C_ModeTypeDef Mode; /*!< FMPI2C communication mode */ 216 217 __IO uint32_t ErrorCode; /*!< FMPI2C Error code */ 218 219 __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ 220 221 #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) 222 void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 223 /*!< FMPI2C Master Tx Transfer completed callback */ 224 void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 225 /*!< FMPI2C Master Rx Transfer completed callback */ 226 void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 227 /*!< FMPI2C Slave Tx Transfer completed callback */ 228 void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 229 /*!< FMPI2C Slave Rx Transfer completed callback */ 230 void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 231 /*!< FMPI2C Listen Complete callback */ 232 void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 233 /*!< FMPI2C Memory Tx Transfer completed callback */ 234 void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 235 /*!< FMPI2C Memory Rx Transfer completed callback */ 236 void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 237 /*!< FMPI2C Error callback */ 238 void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 239 /*!< FMPI2C Abort callback */ 240 241 void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); 242 /*!< FMPI2C Slave Address Match callback */ 243 244 void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 245 /*!< FMPI2C Msp Init callback */ 246 void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); 247 /*!< FMPI2C Msp DeInit callback */ 248 249 #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ 250 } FMPI2C_HandleTypeDef; 251 252 #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) 253 /** 254 * @brief HAL FMPI2C Callback ID enumeration definition 255 */ 256 typedef enum 257 { 258 HAL_FMPI2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPI2C Master Tx Transfer completed callback ID */ 259 HAL_FMPI2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPI2C Master Rx Transfer completed callback ID */ 260 HAL_FMPI2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPI2C Slave Tx Transfer completed callback ID */ 261 HAL_FMPI2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPI2C Slave Rx Transfer completed callback ID */ 262 HAL_FMPI2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPI2C Listen Complete callback ID */ 263 HAL_FMPI2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< FMPI2C Memory Tx Transfer callback ID */ 264 HAL_FMPI2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< FMPI2C Memory Rx Transfer completed callback ID */ 265 HAL_FMPI2C_ERROR_CB_ID = 0x07U, /*!< FMPI2C Error callback ID */ 266 HAL_FMPI2C_ABORT_CB_ID = 0x08U, /*!< FMPI2C Abort callback ID */ 267 268 HAL_FMPI2C_MSPINIT_CB_ID = 0x09U, /*!< FMPI2C Msp Init callback ID */ 269 HAL_FMPI2C_MSPDEINIT_CB_ID = 0x0AU /*!< FMPI2C Msp DeInit callback ID */ 270 271 } HAL_FMPI2C_CallbackIDTypeDef; 272 273 /** 274 * @brief HAL FMPI2C Callback pointer definition 275 */ 276 typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); 277 /*!< pointer to an FMPI2C callback function */ 278 typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, 279 uint16_t AddrMatchCode); 280 /*!< pointer to an FMPI2C Address Match callback function */ 281 282 #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ 283 /** 284 * @} 285 */ 286 287 /** 288 * @} 289 */ 290 /* Exported constants --------------------------------------------------------*/ 291 292 /** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants 293 * @{ 294 */ 295 296 /** @defgroup FMPI2C_XFEROPTIONS FMPI2C Sequential Transfer Options 297 * @{ 298 */ 299 #define FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE) 300 #define FMPI2C_FIRST_AND_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE)) 301 #define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE)) 302 #define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) 303 #define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) 304 #define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE) 305 306 /* List of XferOptions in usage of : 307 * 1- Restart condition in all use cases (direction change or not) 308 */ 309 #define FMPI2C_OTHER_FRAME (0x000000AAU) 310 #define FMPI2C_OTHER_AND_LAST_FRAME (0x0000AA00U) 311 /** 312 * @} 313 */ 314 315 /** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode 316 * @{ 317 */ 318 #define FMPI2C_ADDRESSINGMODE_7BIT (0x00000001U) 319 #define FMPI2C_ADDRESSINGMODE_10BIT (0x00000002U) 320 /** 321 * @} 322 */ 323 324 /** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode 325 * @{ 326 */ 327 #define FMPI2C_DUALADDRESS_DISABLE (0x00000000U) 328 #define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN 329 /** 330 * @} 331 */ 332 333 /** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks 334 * @{ 335 */ 336 #define FMPI2C_OA2_NOMASK ((uint8_t)0x00U) 337 #define FMPI2C_OA2_MASK01 ((uint8_t)0x01U) 338 #define FMPI2C_OA2_MASK02 ((uint8_t)0x02U) 339 #define FMPI2C_OA2_MASK03 ((uint8_t)0x03U) 340 #define FMPI2C_OA2_MASK04 ((uint8_t)0x04U) 341 #define FMPI2C_OA2_MASK05 ((uint8_t)0x05U) 342 #define FMPI2C_OA2_MASK06 ((uint8_t)0x06U) 343 #define FMPI2C_OA2_MASK07 ((uint8_t)0x07U) 344 /** 345 * @} 346 */ 347 348 /** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode 349 * @{ 350 */ 351 #define FMPI2C_GENERALCALL_DISABLE (0x00000000U) 352 #define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN 353 /** 354 * @} 355 */ 356 357 /** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode 358 * @{ 359 */ 360 #define FMPI2C_NOSTRETCH_DISABLE (0x00000000U) 361 #define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH 362 /** 363 * @} 364 */ 365 366 /** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size 367 * @{ 368 */ 369 #define FMPI2C_MEMADD_SIZE_8BIT (0x00000001U) 370 #define FMPI2C_MEMADD_SIZE_16BIT (0x00000002U) 371 /** 372 * @} 373 */ 374 375 /** @defgroup FMPI2C_XFERDIRECTION FMPI2C Transfer Direction Master Point of View 376 * @{ 377 */ 378 #define FMPI2C_DIRECTION_TRANSMIT (0x00000000U) 379 #define FMPI2C_DIRECTION_RECEIVE (0x00000001U) 380 /** 381 * @} 382 */ 383 384 /** @defgroup FMPI2C_RELOAD_END_MODE FMPI2C Reload End Mode 385 * @{ 386 */ 387 #define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD 388 #define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND 389 #define FMPI2C_SOFTEND_MODE (0x00000000U) 390 /** 391 * @} 392 */ 393 394 /** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode 395 * @{ 396 */ 397 #define FMPI2C_NO_STARTSTOP (0x00000000U) 398 #define FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) 399 #define FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) 400 #define FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) 401 /** 402 * @} 403 */ 404 405 /** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition 406 * @brief FMPI2C Interrupt definition 407 * Elements values convention: 0xXXXXXXXX 408 * - XXXXXXXX : Interrupt control mask 409 * @{ 410 */ 411 #define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE 412 #define FMPI2C_IT_TCI FMPI2C_CR1_TCIE 413 #define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE 414 #define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE 415 #define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE 416 #define FMPI2C_IT_RXI FMPI2C_CR1_RXIE 417 #define FMPI2C_IT_TXI FMPI2C_CR1_TXIE 418 /** 419 * @} 420 */ 421 422 /** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition 423 * @{ 424 */ 425 #define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE 426 #define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS 427 #define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE 428 #define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR 429 #define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF 430 #define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF 431 #define FMPI2C_FLAG_TC FMPI2C_ISR_TC 432 #define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR 433 #define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR 434 #define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO 435 #define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR 436 #define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR 437 #define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT 438 #define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT 439 #define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY 440 #define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR 441 /** 442 * @} 443 */ 444 445 /** 446 * @} 447 */ 448 449 /* Exported macros -----------------------------------------------------------*/ 450 451 /** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros 452 * @{ 453 */ 454 455 /** @brief Reset FMPI2C handle state. 456 * @param __HANDLE__ specifies the FMPI2C Handle. 457 * @retval None 458 */ 459 #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) 460 #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ 461 (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ 462 (__HANDLE__)->MspInitCallback = NULL; \ 463 (__HANDLE__)->MspDeInitCallback = NULL; \ 464 } while(0) 465 #else 466 #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET) 467 #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ 468 469 /** @brief Enable the specified FMPI2C interrupt. 470 * @param __HANDLE__ specifies the FMPI2C Handle. 471 * @param __INTERRUPT__ specifies the interrupt source to enable. 472 * This parameter can be one of the following values: 473 * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable 474 * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable 475 * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable 476 * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable 477 * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable 478 * @arg @ref FMPI2C_IT_RXI RX interrupt enable 479 * @arg @ref FMPI2C_IT_TXI TX interrupt enable 480 * 481 * @retval None 482 */ 483 #define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 484 485 /** @brief Disable the specified FMPI2C interrupt. 486 * @param __HANDLE__ specifies the FMPI2C Handle. 487 * @param __INTERRUPT__ specifies the interrupt source to disable. 488 * This parameter can be one of the following values: 489 * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable 490 * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable 491 * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable 492 * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable 493 * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable 494 * @arg @ref FMPI2C_IT_RXI RX interrupt enable 495 * @arg @ref FMPI2C_IT_TXI TX interrupt enable 496 * 497 * @retval None 498 */ 499 #define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 500 501 /** @brief Check whether the specified FMPI2C interrupt source is enabled or not. 502 * @param __HANDLE__ specifies the FMPI2C Handle. 503 * @param __INTERRUPT__ specifies the FMPI2C interrupt source to check. 504 * This parameter can be one of the following values: 505 * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable 506 * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable 507 * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable 508 * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable 509 * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable 510 * @arg @ref FMPI2C_IT_RXI RX interrupt enable 511 * @arg @ref FMPI2C_IT_TXI TX interrupt enable 512 * 513 * @retval The new state of __INTERRUPT__ (SET or RESET). 514 */ 515 #define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ 516 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 517 518 /** @brief Check whether the specified FMPI2C flag is set or not. 519 * @param __HANDLE__ specifies the FMPI2C Handle. 520 * @param __FLAG__ specifies the flag to check. 521 * This parameter can be one of the following values: 522 * @arg @ref FMPI2C_FLAG_TXE Transmit data register empty 523 * @arg @ref FMPI2C_FLAG_TXIS Transmit interrupt status 524 * @arg @ref FMPI2C_FLAG_RXNE Receive data register not empty 525 * @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode) 526 * @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag 527 * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag 528 * @arg @ref FMPI2C_FLAG_TC Transfer complete (master mode) 529 * @arg @ref FMPI2C_FLAG_TCR Transfer complete reload 530 * @arg @ref FMPI2C_FLAG_BERR Bus error 531 * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost 532 * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun 533 * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception 534 * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag 535 * @arg @ref FMPI2C_FLAG_ALERT SMBus alert 536 * @arg @ref FMPI2C_FLAG_BUSY Bus busy 537 * @arg @ref FMPI2C_FLAG_DIR Transfer direction (slave mode) 538 * 539 * @retval The new state of __FLAG__ (SET or RESET). 540 */ 541 #define FMPI2C_FLAG_MASK (0x0001FFFFU) 542 #define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ 543 (__FLAG__)) == (__FLAG__)) ? SET : RESET) 544 545 /** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit. 546 * @param __HANDLE__ specifies the FMPI2C Handle. 547 * @param __FLAG__ specifies the flag to clear. 548 * This parameter can be any combination of the following values: 549 * @arg @ref FMPI2C_FLAG_TXE Transmit data register empty 550 * @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode) 551 * @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag 552 * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag 553 * @arg @ref FMPI2C_FLAG_BERR Bus error 554 * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost 555 * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun 556 * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception 557 * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag 558 * @arg @ref FMPI2C_FLAG_ALERT SMBus alert 559 * 560 * @retval None 561 */ 562 #define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \ 563 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ 564 ((__HANDLE__)->Instance->ICR = (__FLAG__))) 565 566 /** @brief Enable the specified FMPI2C peripheral. 567 * @param __HANDLE__ specifies the FMPI2C Handle. 568 * @retval None 569 */ 570 #define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 571 572 /** @brief Disable the specified FMPI2C peripheral. 573 * @param __HANDLE__ specifies the FMPI2C Handle. 574 * @retval None 575 */ 576 #define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 577 578 /** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode. 579 * @param __HANDLE__ specifies the FMPI2C Handle. 580 * @retval None 581 */ 582 #define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) 583 /** 584 * @} 585 */ 586 587 /* Include FMPI2C HAL Extended module */ 588 #include "stm32f4xx_hal_fmpi2c_ex.h" 589 590 /* Exported functions --------------------------------------------------------*/ 591 /** @addtogroup FMPI2C_Exported_Functions 592 * @{ 593 */ 594 595 /** @addtogroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions 596 * @{ 597 */ 598 /* Initialization and de-initialization functions******************************/ 599 HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c); 600 HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c); 601 void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c); 602 void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c); 603 604 /* Callbacks Register/UnRegister functions ***********************************/ 605 #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) 606 HAL_StatusTypeDef HAL_FMPI2C_RegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID, 607 pFMPI2C_CallbackTypeDef pCallback); 608 HAL_StatusTypeDef HAL_FMPI2C_UnRegisterCallback(FMPI2C_HandleTypeDef *hfmpi2c, HAL_FMPI2C_CallbackIDTypeDef CallbackID); 609 610 HAL_StatusTypeDef HAL_FMPI2C_RegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, pFMPI2C_AddrCallbackTypeDef pCallback); 611 HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2c); 612 #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ 613 /** 614 * @} 615 */ 616 617 /** @addtogroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions 618 * @{ 619 */ 620 /* IO operation functions ****************************************************/ 621 /******* Blocking mode: Polling */ 622 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 623 uint16_t Size, uint32_t Timeout); 624 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 625 uint16_t Size, uint32_t Timeout); 626 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, 627 uint32_t Timeout); 628 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, 629 uint32_t Timeout); 630 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, 631 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); 632 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, 633 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); 634 HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, 635 uint32_t Timeout); 636 637 /******* Non-Blocking mode: Interrupt */ 638 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 639 uint16_t Size); 640 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 641 uint16_t Size); 642 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); 643 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); 644 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, 645 uint16_t MemAddSize, uint8_t *pData, uint16_t Size); 646 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, 647 uint16_t MemAddSize, uint8_t *pData, uint16_t Size); 648 649 HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 650 uint16_t Size, uint32_t XferOptions); 651 HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 652 uint16_t Size, uint32_t XferOptions); 653 HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, 654 uint32_t XferOptions); 655 HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, 656 uint32_t XferOptions); 657 HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); 658 HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c); 659 HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress); 660 661 /******* Non-Blocking mode: DMA */ 662 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 663 uint16_t Size); 664 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 665 uint16_t Size); 666 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); 667 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size); 668 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, 669 uint16_t MemAddSize, uint8_t *pData, uint16_t Size); 670 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, 671 uint16_t MemAddSize, uint8_t *pData, uint16_t Size); 672 673 HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 674 uint16_t Size, uint32_t XferOptions); 675 HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, 676 uint16_t Size, uint32_t XferOptions); 677 HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, 678 uint32_t XferOptions); 679 HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, 680 uint32_t XferOptions); 681 /** 682 * @} 683 */ 684 685 /** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 686 * @{ 687 */ 688 /******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ 689 void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c); 690 void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c); 691 void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 692 void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 693 void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 694 void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 695 void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); 696 void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 697 void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 698 void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 699 void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c); 700 void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c); 701 /** 702 * @} 703 */ 704 705 /** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions 706 * @{ 707 */ 708 /* Peripheral State, Mode and Error functions *********************************/ 709 HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c); 710 HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c); 711 uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); 712 713 /** 714 * @} 715 */ 716 717 /** 718 * @} 719 */ 720 721 /* Private constants ---------------------------------------------------------*/ 722 /** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants 723 * @{ 724 */ 725 726 /** 727 * @} 728 */ 729 730 /* Private macros ------------------------------------------------------------*/ 731 /** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros 732 * @{ 733 */ 734 735 #define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \ 736 ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT)) 737 738 #define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \ 739 ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE)) 740 741 #define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \ 742 ((MASK) == FMPI2C_OA2_MASK01) || \ 743 ((MASK) == FMPI2C_OA2_MASK02) || \ 744 ((MASK) == FMPI2C_OA2_MASK03) || \ 745 ((MASK) == FMPI2C_OA2_MASK04) || \ 746 ((MASK) == FMPI2C_OA2_MASK05) || \ 747 ((MASK) == FMPI2C_OA2_MASK06) || \ 748 ((MASK) == FMPI2C_OA2_MASK07)) 749 750 #define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \ 751 ((CALL) == FMPI2C_GENERALCALL_ENABLE)) 752 753 #define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \ 754 ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE)) 755 756 #define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \ 757 ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT)) 758 759 #define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \ 760 ((MODE) == FMPI2C_AUTOEND_MODE) || \ 761 ((MODE) == FMPI2C_SOFTEND_MODE)) 762 763 #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPI2C_GENERATE_STOP) || \ 764 ((REQUEST) == FMPI2C_GENERATE_START_READ) || \ 765 ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \ 766 ((REQUEST) == FMPI2C_NO_STARTSTOP)) 767 768 #define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \ 769 ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ 770 ((REQUEST) == FMPI2C_NEXT_FRAME) || \ 771 ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ 772 ((REQUEST) == FMPI2C_LAST_FRAME) || \ 773 ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP) || \ 774 IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) 775 776 #define IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_OTHER_FRAME) || \ 777 ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) 778 779 #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 780 (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ 781 FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ 782 FMPI2C_CR2_RD_WRN))) 783 784 #define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ 785 >> 16U)) 786 #define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ 787 >> 16U)) 788 #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) 789 #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) 790 #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) 791 792 #define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 793 #define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 794 795 #define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ 796 (uint16_t)(0xFF00U))) >> 8U))) 797 #define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) 798 799 #define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \ 800 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ 801 (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ 802 (~FMPI2C_CR2_RD_WRN)) : \ 803 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ 804 (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \ 805 (~FMPI2C_CR2_RD_WRN))) 806 807 #define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ 808 ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) 809 #define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 810 /** 811 * @} 812 */ 813 814 /* Private Functions ---------------------------------------------------------*/ 815 /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions 816 * @{ 817 */ 818 /* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */ 819 /** 820 * @} 821 */ 822 823 /** 824 * @} 825 */ 826 827 /** 828 * @} 829 */ 830 831 #endif /* FMPI2C_CR1_PE */ 832 #ifdef __cplusplus 833 } 834 #endif 835 836 837 #endif /* STM32F4xx_HAL_FMPI2C_H */ 838
