1 /*
2  * Copyright 2017-2021 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #include "fsl_flexram.h"
10 
11 /*******************************************************************************
12  * Definitions
13  ******************************************************************************/
14 
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.flexram"
18 #endif
19 
20 /*******************************************************************************
21  * Prototypes
22  ******************************************************************************/
23 /*!
24  * @brief Gets the instance from the base address to be used to gate or ungate the module clock
25  *
26  * @param base FLEXRAM base address
27  *
28  * @return The FLEXRAM instance
29  */
30 static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
31 
32 /*******************************************************************************
33  * Variables
34  ******************************************************************************/
35 /*! @brief Pointers to FLEXRAM bases for each instance. */
36 static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS;
37 
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
39 /*! @brief Pointers to FLEXRAM clocks for each instance. */
40 static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS;
41 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
42 
43 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
44 /*! Look-up table to calculate single-bit error bit position for ITCM. */
45 static const uint8_t ItcmLookUpTable[64] = {
46     0xC1, 0x43, 0x9E, 0x83, 0x15, 0x4C, 0x4A, 0x8C, 0x31, 0x1C, 0xA2, 0xE0, 0x51, 0x2C, 0xC2, 0xD0,
47     0x19, 0x1A, 0x26, 0xEA, 0x29, 0x94, 0x16, 0x64, 0x37, 0xA4, 0x0D, 0xC4, 0x75, 0x38, 0x4F, 0x58,
48     0x46, 0x91, 0x86, 0x61, 0x49, 0x98, 0x89, 0x68, 0x32, 0x34, 0x07, 0xC8, 0x92, 0xA8, 0xA7, 0x54,
49     0xA1, 0xD9, 0x25, 0xF8, 0x0E, 0x0B, 0x8A, 0x2A, 0x52, 0x45, 0x13, 0x85, 0x62, 0x70, 0x23, 0xB0};
50 /*! Look-up table to calculate single-bit error bit position for DTCM. */
51 static const uint8_t DtcmLookUpTable[32] = {0x61, 0x51, 0x19, 0x45, 0x43, 0x31, 0x29, 0x13, 0x62, 0x52, 0x4A,
52                                             0x46, 0x32, 0x2A, 0x23, 0x1A, 0x2C, 0x64, 0x26, 0x25, 0x34, 0x16,
53                                             0x15, 0x54, 0x0B, 0x58, 0x1C, 0x4C, 0x38, 0x0E, 0x0D, 0x49};
54 #endif /* FLEXRAM_ECC_ERROR_DETAILED_INFO */
55 
56 /*******************************************************************************
57  * Code
58  ******************************************************************************/
FLEXRAM_GetInstance(FLEXRAM_Type * base)59 static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
60 {
61     uint32_t instance;
62 
63     /* Find the instance index from base address mappings. */
64     for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++)
65     {
66         if (s_flexramBases[instance] == base)
67         {
68             break;
69         }
70     }
71 
72     assert(instance < ARRAY_SIZE(s_flexramBases));
73 
74     return instance;
75 }
76 
77 /*!
78  * brief FLEXRAM module initialization function.
79  *
80  * param base FLEXRAM base address.
81  */
FLEXRAM_Init(FLEXRAM_Type * base)82 void FLEXRAM_Init(FLEXRAM_Type *base)
83 {
84 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
85     /* Ungate ENET clock. */
86     CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
87 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
88 
89     /* enable all the interrupt status */
90     base->INT_STAT_EN |= (uint32_t)kFLEXRAM_InterruptStatusAll;
91     /* clear all the interrupt status */
92     base->INT_STATUS |= (uint32_t)kFLEXRAM_InterruptStatusAll;
93     /* disable all the interrpt */
94     base->INT_SIG_EN = 0U;
95 }
96 
97 /*!
98  * brief Deinitializes the FLEXRAM.
99  *
100  */
FLEXRAM_Deinit(FLEXRAM_Type * base)101 void FLEXRAM_Deinit(FLEXRAM_Type *base)
102 {
103 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
104     /* Ungate ENET clock. */
105     CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
106 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
107 }
108 
109 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
FLEXRAM_EnableECC(FLEXRAM_Type * base,bool OcramECCEnable,bool TcmECCEnable)110 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable)
111 {
112     if (true == OcramECCEnable)
113     {
114         base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
115     }
116     else
117     {
118         base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
119     }
120 
121     if (true == TcmECCEnable)
122     {
123         base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
124     }
125     else
126     {
127         base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
128     }
129 }
130 
FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type * base,flexram_ocram_ecc_single_error_info_t * info)131 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
132 {
133     assert(NULL != info);
134 
135 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
136     info->OcramSingleErrorECCCipher =
137         (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) >>
138                   FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT);
139     info->OcramSingleErrorECCSyndrome =
140         (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) >>
141                   FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT);
142 #else
143     info->OcramSingleErrorInfo = base->OCRAM_ECC_SINGLE_ERROR_INFO;
144 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
145 
146     info->OcramSingleErrorAddr    = base->OCRAM_ECC_SINGLE_ERROR_ADDR;
147     info->OcramSingleErrorDataLSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_LSB;
148     info->OcramSingleErrorDataMSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_MSB;
149 }
150 
FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type * base,flexram_ocram_ecc_multi_error_info_t * info)151 void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info)
152 {
153     assert(NULL != info);
154 
155 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
156     info->OcramMultiErrorECCCipher =
157         (uint8_t)((base->OCRAM_ECC_MULTI_ERROR_INFO & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) >>
158                   FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT);
159 #else
160     info->OcramMultiErrorInfo  = base->OCRAM_ECC_MULTI_ERROR_INFO;
161 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
162     info->OcramMultiErrorAddr    = base->OCRAM_ECC_MULTI_ERROR_ADDR;
163     info->OcramMultiErrorDataLSB = base->OCRAM_ECC_MULTI_ERROR_DATA_LSB;
164     info->OcramMultiErrorDataMSB = base->OCRAM_ECC_MULTI_ERROR_DATA_MSB;
165 }
166 
FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type * base,flexram_itcm_ecc_single_error_info_t * info)167 void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info)
168 {
169     assert(NULL != info);
170 
171 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
172     /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
173     uint8_t singleErrorECCSyndrome = 0x00U;
174 
175     info->ItcmSingleErrorTCMWriteRead =
176         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
177                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
178     info->ItcmSingleErrorTCMAccessSize =
179         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
180                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
181     info->ItcmSingleErrorTCMMaster =
182         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
183                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
184     info->ItcmSingleErrorTCMPrivilege =
185         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
186                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
187     singleErrorECCSyndrome =
188         (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
189                   FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
190 
191     for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
192     {
193         if (singleErrorECCSyndrome == ItcmLookUpTable[i])
194         {
195             info->ItcmSingleErrorBitPostion = i;
196             break;
197         }
198     }
199 #else
200     info->ItcmSingleErrorInfo  = base->ITCM_ECC_SINGLE_ERROR_INFO;
201 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
202 
203     info->ItcmSingleErrorAddr    = base->ITCM_ECC_SINGLE_ERROR_ADDR;
204     info->ItcmSingleErrorDataLSB = base->ITCM_ECC_SINGLE_ERROR_DATA_LSB;
205     info->ItcmSingleErrorDataMSB = base->ITCM_ECC_SINGLE_ERROR_DATA_MSB;
206 }
207 
FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type * base,flexram_itcm_ecc_multi_error_info_t * info)208 void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info)
209 {
210     assert(NULL != info);
211 
212 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
213     info->ItcmMultiErrorTCMWriteRead =
214         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
215                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
216     info->ItcmMultiErrorTCMAccessSize =
217         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
218                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
219     info->ItcmMultiErrorTCMMaster =
220         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
221                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
222     info->ItcmMultiErrorTCMPrivilege =
223         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
224                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
225     info->ItcmMultiErrorECCSyndrome =
226         (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
227                   FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
228 #else
229     info->ItcmMultiErrorInfo   = base->ITCM_ECC_MULTI_ERROR_INFO;
230 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
231 
232     info->ItcmMultiErrorAddr    = base->ITCM_ECC_MULTI_ERROR_ADDR;
233     info->ItcmMultiErrorDataLSB = base->ITCM_ECC_MULTI_ERROR_DATA_LSB;
234     info->ItcmMultiErrorDataMSB = base->ITCM_ECC_MULTI_ERROR_DATA_MSB;
235 }
236 
FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type * base,flexram_dtcm_ecc_single_error_info_t * info,uint8_t bank)237 void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank)
238 {
239     assert(NULL != info);
240     assert((0x00U == bank) || (0x01U == bank));
241 
242     if (0x00U == bank)
243     {
244 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
245         /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
246         uint8_t singleErrorECCSyndrome = 0x00U;
247 
248         info->DtcmSingleErrorTCMWriteRead =
249             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
250                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
251         info->DtcmSingleErrorTCMAccessSize =
252             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
253                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
254         info->DtcmSingleErrorTCMMaster =
255             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
256                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
257         info->DtcmSingleErrorTCMPrivilege =
258             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
259                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
260         singleErrorECCSyndrome =
261             (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
262                       FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
263 
264         for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
265         {
266             if (singleErrorECCSyndrome == ItcmLookUpTable[i])
267             {
268                 info->DtcmSingleErrorBitPostion = i;
269                 break;
270             }
271         }
272 #else
273         info->DtcmSingleErrorInfo = base->D0TCM_ECC_SINGLE_ERROR_INFO;
274 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
275 
276         info->DtcmSingleErrorAddr = base->D0TCM_ECC_SINGLE_ERROR_ADDR;
277         info->DtcmSingleErrorData = base->D0TCM_ECC_SINGLE_ERROR_DATA;
278     }
279     else
280     {
281 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
282         /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
283         uint8_t singleErrorECCSyndrome = 0x00U;
284 
285         info->DtcmSingleErrorTCMWriteRead =
286             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) >>
287                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
288         info->DtcmSingleErrorTCMAccessSize =
289             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) >>
290                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
291         info->DtcmSingleErrorTCMMaster =
292             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) >>
293                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
294         info->DtcmSingleErrorTCMPrivilege =
295             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) >>
296                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
297         singleErrorECCSyndrome =
298             (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) >>
299                       FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
300 
301         for (uint8_t i = 0x00U; i < sizeof(DtcmLookUpTable) / sizeof(DtcmLookUpTable[0]); i++)
302         {
303             if (singleErrorECCSyndrome == DtcmLookUpTable[i])
304             {
305                 info->DtcmSingleErrorBitPostion = i;
306                 break;
307             }
308         }
309 #else
310         info->DtcmSingleErrorInfo = base->D1TCM_ECC_SINGLE_ERROR_INFO;
311 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
312 
313         info->DtcmSingleErrorAddr = base->D1TCM_ECC_SINGLE_ERROR_ADDR;
314         info->DtcmSingleErrorData = base->D1TCM_ECC_SINGLE_ERROR_DATA;
315     }
316 }
317 
FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type * base,flexram_dtcm_ecc_multi_error_info_t * info,uint8_t bank)318 void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank)
319 {
320     assert(NULL != info);
321     assert((0x00U == bank) || (0x01U == bank));
322 
323     if (0x00U == bank)
324     {
325 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
326         info->DtcmMultiErrorTCMWriteRead =
327             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
328                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
329         info->DtcmMultiErrorTCMAccessSize =
330             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
331                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
332         info->DtcmMultiErrorTCMMaster =
333             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
334                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
335         info->DtcmMultiErrorTCMPrivilege =
336             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
337                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
338         info->DtcmMultiErrorECCSyndrome =
339             (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
340                       FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
341 #else
342         info->DtcmMultiErrorInfo  = base->D0TCM_ECC_MULTI_ERROR_INFO;
343 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
344 
345         info->DtcmMultiErrorAddr = base->D0TCM_ECC_MULTI_ERROR_ADDR;
346         info->DtcmMultiErrorData = base->D0TCM_ECC_MULTI_ERROR_DATA;
347     }
348     else
349     {
350 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
351         info->DtcmMultiErrorTCMWriteRead =
352             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
353                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
354         info->DtcmMultiErrorTCMAccessSize =
355             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
356                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
357         info->DtcmMultiErrorTCMMaster =
358             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
359                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
360         info->DtcmMultiErrorTCMPrivilege =
361             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
362                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
363         info->DtcmMultiErrorECCSyndrome =
364             (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
365                       FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
366 #else
367         info->DtcmMultiErrorInfo  = base->D1TCM_ECC_MULTI_ERROR_INFO;
368 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
369 
370         info->DtcmMultiErrorAddr = base->D1TCM_ECC_MULTI_ERROR_ADDR;
371         info->DtcmMultiErrorData = base->D1TCM_ECC_MULTI_ERROR_DATA;
372     }
373 }
374 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
375