1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	uart_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef UART_REG_H
28 #define UART_REG_H
29 #include "../sys.h"
30 
31 /*******************************      uart0 registers: 0x140080   *******************************/
32 /*******************************      uart1 registers: 0x1400c0      ******************************/
33 #define reg_uart_data_buf_adr(i)  (0x140080+(i)*0x40)  //uart(i)
34 
35 #define reg_uart_data_buf(i,j)    REG_ADDR8(reg_uart_data_buf_adr(i)+(j)) //uart(i)_buf(j)
36 #define reg_uart_data_hword_buf(i,j)  REG_ADDR16(reg_uart_data_buf_adr(i)+(j)*2)
37 
38 #define reg_uart_data_word_buf(i)  REG_ADDR32(reg_uart_data_buf_adr(i)) //uart(i)
39 
40 #define reg_uart_clk_div(i)		REG_ADDR16(0x140084+(i)*0x40)
41 
42 enum{
43 	FLD_UART_CLK_DIV = 			BIT_RNG(0,14),
44 	FLD_UART_CLK_DIV_EN = 		BIT(15)
45 };
46 
47 #define reg_uart_ctrl0(i)			REG_ADDR8(0x140086+(i)*0x40)
48 
49 enum{
50 	FLD_UART_BPWC_O = 			BIT_RNG(0,3),
51 	FLD_UART_MASK_RX_IRQ = 		BIT(6),
52 	FLD_UART_MASK_TX_IRQ =		BIT(7)
53 };
54 
55 #define reg_uart_ctrl1(i)         		REG_ADDR8(0x140087+(i)*0x40)
56 
57 enum {
58     FLD_UART_TX_CTS_POLARITY = 	BIT(0),
59     FLD_UART_TX_CTS_ENABLE = 	BIT(1),
60     FLD_UART_PARITY_ENABLE = 	BIT(2),
61     FLD_UART_PARITY_POLARITY = 	BIT(3),       //1:odd parity   0:even parity
62     FLD_UART_STOP_SEL = 		BIT_RNG(4,5),
63     FLD_UART_TTL_ENABLE = 		BIT(6),
64     FLD_UART_LOOPBACK_O = 		BIT(7),
65 };
66 
67 
68 #define reg_uart_ctrl2(i)			REG_ADDR16(0x140088+(i)*0x40)
69 
70 enum {
71     FLD_UART_RTS_TRIQ_LEV   	= BIT_RNG(0,3),
72     FLD_UART_RTS_POLARITY 		= BIT(4),
73     FLD_UART_RTS_MANUAL_V 	 	= BIT(5),
74     FLD_UART_RTS_MANUAL_M 		= BIT(6),
75     FLD_UART_RTS_EN 			= BIT(7),
76 };
77 
78 #define reg_uart_ctrl3(i)        	REG_ADDR8(0x140089+(i)*0x40)
79 
80 enum {
81 	FLD_UART_RX_IRQ_TRIQ_LEV 	= BIT_RNG(0,3),
82 	FLD_UART_TX_IRQ_TRIQ_LEV 	= BIT_RNG(4,7),
83 };
84 ////////////////////////////////////////////////////
85 #define reg_uart_rx_timeout0(i)	REG_ADDR8(0x14008a+(i)*0x40)
86 
87 enum{
88 	FLD_UART_TIMEOUT_BW		 = 	BIT_RNG(0,7),
89 };
90 
91 #define reg_uart_rx_timeout1(i)  REG_ADDR8(0x14008b+0x40*(i))
92 
93 enum{
94 	FLD_UART_TIMEOUT_MUL	 = 	BIT_RNG(0,1),
95 	FLD_UART_MARK_RXDONE	 =  BIT(2),
96 	//rsvd BIT(4)
97 	FLD_UART_P7816_EN	 	 =  BIT(5),
98 	FLD_UART_MASK_TXDONE	 =  BIT(6),
99 	FLD_UART_MASK_ERR_IRQ 	 =  BIT(7),
100 };
101 
102 
103 
104 #define reg_uart_buf_cnt(i)       REG_ADDR8(0x14008c+(i)*0x40)
105 enum{
106 	FLD_UART_RX_BUF_CNT		=  BIT_RNG(0,3),
107 	FLD_UART_TX_BUF_CNT		=  BIT_RNG(4,7),
108 };
109 
110 #define reg_uart_status1(i)			REG_ADDR8(0x14008d+((i)*0x40))
111 enum{
112 	FLD_UART_RBCNT 	     	=  BIT_RNG(0,2),
113 	FLD_UART_IRQ_O    		=  BIT(3),
114 	FLD_UART_WBCNT 	     	=  BIT_RNG(4,6), //R
115 	FLD_UART_CLEAR_RX 		=  BIT(6),		 //Write 1 clear RX
116 	FLD_UART_RX_ERR	 		=  BIT(7),		//R
117 	FLD_UART_CLEAR_TX	 	=  BIT(7),		//Write 1 clear TX
118 };
119 
120 
121 #define reg_uart_status2(i)       REG_ADDR8((0x14008e) +(0x40*(i)))
122 enum{
123 	FLD_UART_TX_DONE   	  =  BIT(0),//only for dma default 1.
124 	FLD_UART_TX_BUF_IRQ   =  BIT(1),
125 	FLD_UART_RX_DONE   	  =  BIT(2),
126 	FLD_UART_RX_BUF_IRQ   =  BIT(3),
127 };
128 
129 //state machine use for IC debug
130 #define reg_uart_state(i)       REG_ADDR8(0x14008f+0x40*(i))
131 enum{
132 	FLD_UART_TSTATE_i   	=  BIT_RNG(0,2),//only for dma default 1.
133 	FLD_UART_RSTATE_i   	=  BIT_RNG(4,7),
134 };
135 
136 /*******************************      7816 registers: 0x1401f0     ******************************/
137 #define reg_7816_clk_div		REG_ADDR8(0x1401f0)
138 enum{
139 	FLD_7816_CLK_DIV = 			BIT_RNG(4,7),
140 };
141 #endif
142