1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	stimer_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef STIMER_REG_H_
28 #define STIMER_REG_H_
29 
30 #include "../sys.h"
31 /*******************************      sys clock registers: 0x140200       ******************************/
32 #define STIMER_BASE_ADDR			   	0x140200
33 #define reg_system_tick         		REG_ADDR32(STIMER_BASE_ADDR)
34 
35 #define reg_system_irq_level         	REG_ADDR32(STIMER_BASE_ADDR+0x4)
36 
37 #define reg_system_irq_mask				REG_ADDR8(STIMER_BASE_ADDR+0x8)
38 enum{
39 	FLD_SYSTEM_IRQ_MASK 	= 	BIT_RNG(0,2),
40 	FLD_SYSTEM_TRIG_PAST_EN = 	BIT(3),
41 };
42 
43 #define reg_system_cal_irq		REG_ADDR8(STIMER_BASE_ADDR+0x9)
44 
45 typedef enum{
46 	FLD_SYSTEM_IRQ  		= 	BIT(0),
47 	FLD_SYSTEM_32K_IRQ  	= 	BIT(1),
48 }stimer_irq_e;
49 
50 #define reg_system_ctrl		    REG_ADDR8(STIMER_BASE_ADDR+0xa)
51 enum{
52 	FLD_SYSTEM_32K_WR_EN 		= 	BIT(0),
53 	FLD_SYSTEM_TIMER_EN 	    = 	BIT(1),
54 	FLD_SYSTEM_TIMER_AUTO 	    = 	BIT(2),
55 	FLD_SYSTEM_32K_TRACK_EN 	= 	BIT(3),
56 	FLD_SYSTEM_32K_CAL_MODE 	= 	BIT_RNG(4,7),
57 
58 };
59 
60 #define reg_system_st		    REG_ADDR8(STIMER_BASE_ADDR+0xb)
61 
62 enum{
63 
64 	FLD_SYSTEM_CMD_STOP 			=   BIT(1),
65 	FLD_SYSTEM_CMD_SYNC		        =   BIT(3),
66 	FLD_SYSTEM_CLK_32K		        =   BIT(4),
67 	FLD_SYSTEM_CLR_RD_DONE			=   BIT(5),
68 	FLD_SYSTEM_RD_BUSY			    =   BIT(6),
69 	FLD_SYSTEM_CMD_SET_DLY_DONE	    =   BIT(7),
70 
71 };
72 
73 #define reg_system_timer_set_32k         	REG_ADDR32(STIMER_BASE_ADDR+0xc)
74 
75 #define reg_system_timer_read_32k         	REG_ADDR32(STIMER_BASE_ADDR+0x10)
76 
77 #define reg_system_cal_latch_32k         	REG_ADDR32(STIMER_BASE_ADDR+0x14)
78 
79 #define reg_system_up_32k					REG_ADDR32(STIMER_BASE_ADDR+0x18)
80 enum{
81 
82 	FLD_SYSTEM_UPDATE_UPON_32K 			=   BIT(0),
83 	FLD_SYSTEM_RUN_UPON_NXT_32K		    =   BIT(1),
84 };
85 
86 #endif /* STIMER_REG_H_ */
87