1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file spi_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef SPI_REG_H 28 #define SPI_REG_H 29 30 #include "../sys.h" 31 32 /******************************* hspi registers: 0x1FFFFC0 ******************************/ 33 34 35 36 #define HSPI_BASE_ADDR 0x1FFFFC0 37 #define PSPI_BASE_ADDR 0x140040 38 #define BASE_ADDR_DIFF 0x1EBFF80 39 40 #define reg_hspi_data_buf_adr 0x1FFFFC8 41 #define reg_hspi_xip_base_adr 0x1000000 42 #define reg_spi_data_buf_adr(i) 0x140048+(i)*BASE_ADDR_DIFF 43 /** 44 * BIT[0:1] the minimum time between the edge of SPI_CS and the edges of SPI_CLK.the actual duration is (SPI_CLK_OUT/2)*(cs2sclk+1).master only 45 * BIT[2] set 3line mode ,MOSI is bi-directional signal in regular mode.master only 46 * BIT[3] transfer data with least significant bit first.1: LSB 0: MSB default. master/slave 47 * BIT[4] set dual io mode.master only 48 * BIT[5:6] set spi 4 mode. master/slave 49 * * * bit5: CPHA-SPI_CLK Phase,bit6: CPOL-SPI_CLK Polarity 50 * MODE0: CPOL = 0, CPHA =0; 51 * MODE1: CPOL = 0, CPHA =1; 52 * MODE2: CPOL = 1, CPHA =0; 53 * MODE3: CPOL = 1, CPHA =1; 54 * BIT[7] set master/slave mode. 0 slave 1 master default.master/slave 55 */ 56 #define reg_spi_mode0(i) REG_ADDR8(PSPI_BASE_ADDR+(i)*BASE_ADDR_DIFF) 57 enum{ 58 FLD_SPI_CS2SCLK = BIT_RNG(0,1), 59 FLD_SPI_3LINE = BIT(2), 60 FLD_SPI_LSB = BIT(3), 61 FLD_SPI_DUAL = BIT(4), 62 FLD_SPI_MODE_WORK_MODE = BIT_RNG(5,6), 63 FLD_SPI_MASTER_MODE = BIT(7), 64 }; 65 66 /*the clock freq ratio between the source_clock and spi_clock.master only 67 * spi_clock=source_clock/((spi_clk_div+1)*2) 68 * spi_clk_div=reg_hspi_mode1[7:0]. max_value=0xff,spi_clock==source_clock 69 */ 70 //#define reg_hspi_mode1 REG_ADDR8(HSPI_BASE_ADDR+0x01) 71 #define reg_spi_mode1(i) REG_ADDR8(PSPI_BASE_ADDR+0x01+(i)*BASE_ADDR_DIFF) 72 73 /** 74 * BIT[0] set cmd format 0: single mode 1: the format of the cmd phase is the same as the data phase(Dual/Quad).master only 75 * BIT[1] set spi quad I/O mode. master only 76 * BIT[2] set the spi commnd phase enable.master only 77 * BIT[4:7] the minimum time that SPI CS should stay HIGH.the actual duration is (SPI_CLK period_out / 2)*(csht+1).default=2,master only 78 */ 79 #define reg_spi_mode2(i) REG_ADDR8(PSPI_BASE_ADDR+0x02+(i)*BASE_ADDR_DIFF) 80 81 82 enum{ 83 FLD_HSPI_CMD_FMT =BIT(0), 84 FLD_HSPI_QUAD =BIT(1), 85 FLD_SPI_CMD_EN =BIT(2), 86 FLD_SPI_HSPI_MODE2_RESERVED =BIT(3), 87 FLD_SPI_CSHT =BIT_RNG(4,7), 88 }; 89 90 /** 91 * BIT[0:7] transfer count0 for write data.master only 92 */ 93 #define reg_spi_tx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR+0x03+(i)*BASE_ADDR_DIFF) 94 95 /** 96 * BIT[0:7] transfer count1 for write data.master only 97 */ 98 99 #define reg_spi_tx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR+0x12+(i)*(BASE_ADDR_DIFF-0x12+0x20)) 100 //#define reg_hspi_tx_cnt1 REG_ADDR8(HSPI_BASE_ADDR+0x20) 101 /** 102 * BIT[0:7] transfer count2 for write data.master only 103 */ 104 105 #define reg_spi_tx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR+0x13+(i)*(BASE_ADDR_DIFF-0x13+0x21)) 106 107 /** 108 * BIT[0:7] transfer count0 for read data.master only 109 */ 110 #define reg_spi_rx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR+0x04+(i)*BASE_ADDR_DIFF) 111 112 /** 113 * BIT[0:7] transfer count1 for read data.master only 114 */ 115 116 #define reg_spi_rx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR+0x10+(i)*(BASE_ADDR_DIFF-0x10+0x1e)) 117 /** 118 * BIT[0:7] transfer count2 for read data.master only 119 */ 120 121 #define reg_spi_rx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR+0x11+(i)*(BASE_ADDR_DIFF-0x11+0x1f)) 122 123 124 125 /** 126 * BIT[0:3] dummy data cnt, dummy is always single wire mode, dummy number = dummy_cnt + 1.master only 127 * BIT[4:7] the transfer mode.master only 128 * the transfer sequence could be: 129 * 0x0:write and read at the same time(must enbale CmdEn) 130 * 0x1:write only 131 * 0x2:read only(must enbale CmdEn) 132 * 0x3:write,read 133 * 0x4:read,write 134 * 0x5:write,dummy,read 135 * 0x6:read,dummy,write(must enbale CmdEn) 136 * 0x7:None Data(must enbale CmdEn) 137 * 0x8:Dummy,write 138 * 0x9:Dummy,read 139 * 0xa~0xf:reserved 140 */ 141 #define reg_spi_trans0(i) REG_ADDR8(PSPI_BASE_ADDR+0x05+(i)*BASE_ADDR_DIFF) 142 143 enum{ 144 FLD_SPI_DUMMY_CNT = BIT_RNG(0,3), 145 FLD_SPI_TRANSMODE =BIT_RNG(4,7), 146 }; 147 148 149 150 /** 151 * BIT[0:7] SPI Command.master only 152 */ 153 154 #define reg_spi_trans1(i) REG_ADDR8(PSPI_BASE_ADDR+0x06+(i)*BASE_ADDR_DIFF) 155 enum{ 156 FLD_SPI_CMD_RESERVED =BIT(0), 157 FLD_SPI_CMD_TRANS_HWORD =BIT(1),//1 apb hword transfer 158 FLD_SPI_CMD_TRANS_WORD =BIT(2),//1 apb word transfer 159 FLD_SPI_CMD_RD_DUMMY_4CYCLE =BIT(3),// 0 8cycle 1 4cycle 160 FLD_SPI_CMD_ADDR_AUTO_INCREASE =BIT(4),// 0 AUTO incease 161 FLD_SPI_CMD_DATA_DUAL =BIT(5),// 0 Single 1 DuaL 162 FLD_SPI_CMD_ADDR_DUAL =BIT(6),// 0 Single 1 DuaL 163 FLD_SPI_CMD_RD_EN =BIT(7),// 0 write 1 read 164 }; 165 166 /** 167 * BIT[0] enable the SPI Receive FIFO Overrun interrupt . slave only 168 * BIT[1] enable the SPI Transmit FIFO Underrun interrupt. slave only 169 * BIT[2] enable the SPI Receive FIFO Threshold interrupt.master/slave 170 * BIT[3] enable the SPI Transmit FIFO Threshold interrupt.master/slave 171 * BIT[4] enable the SPI Transmit end interrupt.master/slave 172 * BIT[5] enable slvCmdint.The slave command interrupt is triggered each byte command received (starting 8 bit) .slave only 173 * BIT[6] enable RX DMA 174 * BIT[7] enable TX DMA 175 */ 176 177 #define reg_spi_trans2(i) REG_ADDR8(PSPI_BASE_ADDR+0x07+(i)*BASE_ADDR_DIFF) 178 enum{ 179 FLD_SPI_RXFIFO_OR_INT_EN =BIT(0), 180 FLD_SPI_TXFIFO_UR_INT_EN =BIT(1), 181 FLD_SPI_RXFIFO_INT_EN =BIT(2), 182 FLD_SPI_TXFIFO_INT_EN =BIT(3), 183 FLD_SPI_END_INT_EN =BIT(4), 184 FLD_SPI_SLV_CMD_EN =BIT(5), 185 FLD_SPI_RX_DMA_EN =BIT(6), 186 FLD_SPI_TX_DMA_EN =BIT(7), 187 }; 188 189 190 /** 191 * Number of data write/read registers (data0 .. data3) 192 */ 193 #define REG_SPI_WR_RD_SIZE 4 194 195 /** 196 * BIT[0:7] data0[7:0] to transmit or received. 197 */ 198 199 #define reg_spi_wr_rd_data0(i) REG_ADDR8(PSPI_BASE_ADDR+0x08+(i)*BASE_ADDR_DIFF) 200 /** 201 * BIT[0:7] data1[7:0] to transmit or received. 202 */ 203 204 #define reg_spi_wr_rd_data1(i) REG_ADDR8(PSPI_BASE_ADDR+0x09+(i)*BASE_ADDR_DIFF) 205 /** 206 * BIT[0:7] data2[7:0] to transmit or received. 207 */ 208 #define reg_spi_wr_rd_data2(i) REG_ADDR8(PSPI_BASE_ADDR+0x0a+(i)*BASE_ADDR_DIFF) 209 210 /** 211 * BIT[0:7] data3[7:0] to transmit or received. 212 */ 213 214 #define reg_spi_wr_rd_data3(i) REG_ADDR8(PSPI_BASE_ADDR+0x0b+(i)*BASE_ADDR_DIFF) 215 216 #define reg_spi_wr_rd_data(i,j) REG_ADDR8(PSPI_BASE_ADDR+0x08+(j)+(i)*BASE_ADDR_DIFF) 217 218 219 220 /** 221 * BIT[0:3] number of valid entries in the rxfifo. 222 * BIT[4:7] number of valid entries in the txfifo. 223 */ 224 #define reg_spi_fifo_num(i) REG_ADDR8(PSPI_BASE_ADDR+0x0c+(i)*BASE_ADDR_DIFF) 225 226 enum{ 227 FLD_SPI_RXF_NUM = BIT_RNG(0,3), 228 FLD_SPI_TXF_NUM = BIT_RNG(4,7), 229 }; 230 231 /** 232 * BIT[2] rxfifo reset,write 1 to reset. Spi clock must turn on. 233 * BIT[3] txfifo reset,write 1 to reset. Spi clock must turn on 234 * BIT[4] rxfifo full flag. 235 * BIT[5] rxfifo empty flag 236 * BIT[6] txfifo full flag. 237 * BIT[7] txfifo empty flag 238 */ 239 #define reg_spi_fifo_state(i) REG_ADDR8(PSPI_BASE_ADDR+0x0d+(i)*BASE_ADDR_DIFF) 240 241 enum{ 242 FLD_SPI_FIFO_STA_RESERVED = BIT_RNG(0,1), 243 FLD_SPI_RXF_CLR =BIT(2), 244 FLD_SPI_TXF_CLR =BIT(3), 245 FLD_SPI_RXF_FULL =BIT(4), 246 FLD_SPI_RXF_EMPTY =BIT(5), 247 FLD_SPI_TXF_FULL =BIT(6), 248 FLD_SPI_TXF_EMPTY =BIT(7), 249 }; 250 251 /** 252 * BIT[2] RX FIFO Overrun interrupt status. slave only 253 * BIT[3] TX FIFO Underrun interrupt status. slave only 254 * BIT[4] RX FIFO Threshold interrupt status.set 1 to clear. master/slave 255 * BIT[5] TX FIFO Threshold interrupt status.set 1 to clear. master/slave 256 * BIT[6] End of SPI Transfer interrupt status.set 1 to clear.master/slave 257 * BIT[7] Slave Command Interrupt status.set 1 to clear.slave only 258 */ 259 #define reg_spi_irq_state(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0e +(i)*BASE_ADDR_DIFF) 260 261 enum{ 262 FLD_SPI_STATE_RESERVED =BIT_RNG(0,1), 263 FLD_SPI_RXF_OR_INT =BIT(2), 264 FLD_SPI_TXF_UR_INT =BIT(3), 265 FLD_SPI_RXF_INT =BIT(4), 266 FLD_SPI_TXF_INT =BIT(5), 267 FLD_SPI_END_INT =BIT(6), 268 FLD_SPI_SLV_CMD_INT =BIT(7), 269 }; 270 271 /** 272 * BIT[0] set this bit to indicate that spi as slave is ready for data transaction 273 * BIT[1] spi soft reset.high valid. 274 * BIT[4:6] fifo threshold. 0x4 default. 275 * BIT[7] SPI transfer status .1 is busy, 0 not busy. 276 */ 277 #define reg_spi_status(i) REG_ADDR8(PSPI_BASE_ADDR + 0x0f +(i)*BASE_ADDR_DIFF) 278 enum{ 279 FLD_HSPI_SLAVE_READY =BIT(0), 280 FLD_HSPI_SOFT_RESET =BIT(1), 281 FLD_HSPI_HSPI_STATUS_RESERVED =BIT_RNG(2,3), 282 FLD_HSPI_FIFO_THRES =BIT_RNG(4,6), 283 FLD_HSPI_BUSY =BIT(7), 284 }; 285 286 /** 287 * BIT[0:7] hspi_addr0. 288 */ 289 #define reg_hspi_addr0 REG_ADDR8(HSPI_BASE_ADDR+0x10) 290 291 /** 292 * BIT[0:7] hspi_addr1. 293 */ 294 #define reg_hspi_addr1 REG_ADDR8(HSPI_BASE_ADDR+0x11) 295 296 /** 297 * BIT[0:7] hspi_addr2. 298 */ 299 #define reg_hspi_addr2 REG_ADDR8(HSPI_BASE_ADDR+0x12) 300 301 /** 302 * BIT[0:7] hspi_addr3. 303 */ 304 #define reg_hspi_addr3 REG_ADDR8(HSPI_BASE_ADDR+0x13) 305 306 #define reg_hspi_addr(i) REG_ADDR8(HSPI_BASE_ADDR+0x10+i) 307 308 /** hspi_addr0~ hspi_addr3. 309 */ 310 #define reg_hspi_addr_32 REG_ADDR32(HSPI_BASE_ADDR+0x10) 311 312 313 314 /** 315 * BIT[0] 1:enable addr phase, master only 316 * BIT[1] 0:single mode 1:the format of addr phase is the same as the data phase(Dual/Quad).master only 317 * BIT[2:3] address length.2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes.master only 318 * BIT[4] enable xip. 319 * BIT[5] stop xip. 320 * BIT[6] xip mode 0:xip normal mode 1:xip sequential mode 321 * BIT[7] 0:xip timeout ,disable 1:xip timeout enable .default 1 322 */ 323 #define reg_hspi_xip_ctrl REG_ADDR8(HSPI_BASE_ADDR+0x14) 324 enum{ 325 FLD_HSPI_ADDR_EN = BIT(0), 326 FLD_HSPI_ADDR_FMT = BIT(1), 327 FLD_HSPI_ADDR_LEN = BIT_RNG(2,3), 328 FLD_HSPI_XIP_ENABLE = BIT(4), 329 FLD_HSPI_XIP_STOP = BIT(5), 330 FLD_HSPI_XIP_MODE = BIT(6), 331 FLD_HSPI_XIP_TIMEOUT_MODE = BIT(7), 332 }; 333 334 335 /** 336 * BIT[0:7] write command used for xip 337 */ 338 #define reg_hspi_xip_wr_cmd REG_ADDR8(HSPI_BASE_ADDR+0x15) 339 340 /** 341 * BIT[0:7] read command used for xip 342 */ 343 #define reg_hspi_xip_rd_cmd REG_ADDR8(HSPI_BASE_ADDR+0x16) 344 345 /** 346 * BIT[0:7] Use this combined with xip_mode being xip sequential mode.default page boundary size is 32byte, 2^page_size. 347 */ 348 #define reg_hspi_page_size REG_ADDR8(HSPI_BASE_ADDR+0x17) 349 350 351 /** 352 * BIT[0:3] xip write mode .default 1, write trans mode is write only. 353 * BIT[4:7] xip read mode. default 2 ,read trans mode is read only. 354 */ 355 #define reg_hspi_xip_trans_mode REG_ADDR8(HSPI_BASE_ADDR+0x18) 356 enum{ 357 FLD_HSPI_XIP_WR_TRANS_MODE = BIT_RNG(0,3), 358 FLD_HSPI_XIP_RD_TRANS_MODE = BIT_RNG(4,7), 359 }; 360 361 /** 362 * BIT[0:7] xip_addr_offset0. 363 */ 364 #define reg_hspi_xip_addr_offset0 REG_ADDR8(HSPI_BASE_ADDR+0x19) 365 366 /** 367 * BIT[0:7] xip_addr_offset1. 368 */ 369 #define reg_hspi_xip_addr_offset1 REG_ADDR8(HSPI_BASE_ADDR+0x1a) 370 371 372 /** 373 * BIT[0:7] xip_addr_offset2. 374 */ 375 #define reg_hspi_xip_addr_offset2 REG_ADDR8(HSPI_BASE_ADDR+0x1b) 376 377 /** 378 * BIT[0:7] xip_addr_offset3. 379 */ 380 #define reg_hspi_xip_addr_offset3 REG_ADDR8(HSPI_BASE_ADDR+0x1c) 381 382 383 384 /** 385 * BIT[0:7] when XIP_TIMEOUT_MODE enable,timeout period=spi_clock_out_period*timeout_cnt 386 */ 387 #define reg_hspi_xip_timeout_cnt REG_ADDR8(HSPI_BASE_ADDR+0x1d) 388 /** 389 * BIT[0] 1:enable hspi 3line dcx (data/command selection), master only,for spi panel(LCD OLED ...) 390 * BIT[1] hspi 3line dcx (data/command selection). 0:command 1:data 391 * BIT[4:2] 2data_lane mode.3'b000:2data_lane close 3'b001:RGB565 3'b011:RGB666 3'b011:RGB888. 392 */ 393 #define reg_hspi_panel_ctrl REG_ADDR8(HSPI_BASE_ADDR+0x22) 394 enum{ 395 FLD_HSPI_PANEL_3LINE_DCX_EN = BIT(0), 396 FLD_HSPI_PANEL_3LINE_DCX = BIT(1), 397 FLD_HSPI_PANEL_2DATA_LANE = BIT_RNG(2,4), 398 }; 399 400 401 #endif 402
