1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file gpio_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef GPIO_REG_H_ 28 #define GPIO_REG_H_ 29 #include "../sys.h" 30 /******************************* gpio registers: 0x140300 ******************************/ 31 //PA 32 #define reg_gpio_pa_setting1 REG_ADDR32(0x140300) 33 #define reg_gpio_pa_in REG_ADDR8(0x140300) 34 #define reg_gpio_pa_ie REG_ADDR8(0x140301) 35 #define reg_gpio_pa_oen REG_ADDR8(0x140302) 36 #define reg_gpio_pa_out REG_ADDR8(0x140303) 37 38 #define reg_gpio_pa_setting2 REG_ADDR32(0x140304) 39 #define reg_gpio_pa_pol REG_ADDR8(0x140304) 40 #define reg_gpio_pa_ds REG_ADDR8(0x140305) 41 #define reg_gpio_pa_gpio REG_ADDR8(0x140306) 42 #define reg_gpio_pa_irq_en REG_ADDR8(0x140307) 43 44 #define reg_gpio_pa_fs REG_ADDR16(0x140330) 45 #define reg_gpio_pa_fuc_l REG_ADDR8(0x140330) 46 #define reg_gpio_pa_fuc_h REG_ADDR8(0x140331) 47 48 //PB 49 #define reg_gpio_pb_setting1 REG_ADDR32(0x140308) 50 #define reg_gpio_pb_in REG_ADDR8(0x140308) 51 #define reg_gpio_pb_ie REG_ADDR8(0x140309) 52 #define reg_gpio_pb_oen REG_ADDR8(0x14030a) 53 #define reg_gpio_pb_out REG_ADDR8(0x14030b) 54 55 #define reg_gpio_pb_setting2 REG_ADDR32(0x14030c) 56 #define reg_gpio_pb_pol REG_ADDR8(0x14030c) 57 #define reg_gpio_pb_ds REG_ADDR8(0x14030d) 58 #define reg_gpio_pb_gpio REG_ADDR8(0x14030e) 59 #define reg_gpio_pb_irq_en REG_ADDR8(0x14030f) 60 61 #define reg_gpio_pb_fs REG_ADDR16(0x140332) 62 #define reg_gpio_pb_fuc_l REG_ADDR8(0x140332) 63 #define reg_gpio_pb_fuc_h REG_ADDR8(0x140333) 64 65 //PC 66 #define reg_gpio_pc_setting1 REG_ADDR32(0x140310) 67 #define reg_gpio_pc_in REG_ADDR8(0x140310) 68 #define areg_gpio_pc_ie 0xbd 69 #define areg_gpio_pc_pe 0xbe 70 #define reg_gpio_pc_oen REG_ADDR8(0x140312) 71 #define reg_gpio_pc_out REG_ADDR8(0x140313) 72 73 #define reg_gpio_pc_setting2 REG_ADDR32(0x140314) 74 #define reg_gpio_pc_pol REG_ADDR8(0x140314) 75 #define areg_gpio_pc_ds 0xbf 76 #define reg_gpio_pc_gpio REG_ADDR8(0x140316) 77 #define reg_gpio_pc_irq_en REG_ADDR8(0x140317) 78 79 #define reg_gpio_pc_fs REG_ADDR16(0x140334) 80 #define reg_gpio_pc_fuc_l REG_ADDR8(0x140334) 81 #define reg_gpio_pc_fuc_h REG_ADDR8(0x140335) 82 83 //PD 84 #define reg_gpio_pd_setting1 REG_ADDR32(0x140318) 85 #define reg_gpio_pd_in REG_ADDR8(0x140318) 86 #define areg_gpio_pd_ie 0xc0 87 #define areg_gpio_pd_pe 0xc1 88 #define reg_gpio_pd_oen REG_ADDR8(0x14031a) 89 #define reg_gpio_pd_out REG_ADDR8(0x14031b) 90 91 #define reg_gpio_pd_setting2 REG_ADDR32(0x14031c) 92 #define reg_gpio_pd_pol REG_ADDR8(0x14031c) 93 #define areg_gpio_pd_ds 0xc2 94 #define reg_gpio_pd_gpio REG_ADDR8(0x14031e) 95 #define reg_gpio_pd_irq_en REG_ADDR8(0x14031f) 96 97 #define reg_gpio_pd_fs REG_ADDR16(0x140336) 98 #define reg_gpio_pd_fuc_l REG_ADDR8(0x140336)//default 0xf0 99 #define reg_gpio_pd_fuc_h REG_ADDR8(0x140337) 100 101 //PE 102 #define reg_gpio_pe_setting1 REG_ADDR32(0x140320) 103 #define reg_gpio_pe_in REG_ADDR8(0x140320) 104 #define reg_gpio_pe_ie REG_ADDR8(0x140321) 105 #define reg_gpio_pe_oen REG_ADDR8(0x140322) 106 #define reg_gpio_pe_out REG_ADDR8(0x140323) 107 108 #define reg_gpio_pe_setting2 REG_ADDR32(0x140324) 109 #define reg_gpio_pe_pol REG_ADDR8(0x140324) 110 #define reg_gpio_pe_ds REG_ADDR8(0x140325) 111 #define reg_gpio_pe_gpio REG_ADDR8(0x140326) 112 #define reg_gpio_pe_irq_en REG_ADDR8(0x140327) 113 114 #define reg_gpio_pe_fs REG_ADDR16(0x140350) 115 #define reg_gpio_pe_fuc_l REG_ADDR8(0x140350) 116 #define reg_gpio_pe_fuc_h REG_ADDR8(0x140351) 117 118 //PF 119 #define reg_gpio_pf_setting1 REG_ADDR32(0x140328) 120 #define reg_gpio_pf_in REG_ADDR8(0x140328) 121 #define reg_gpio_pf_ie REG_ADDR8(0x140329) 122 #define reg_gpio_pf_oen REG_ADDR8(0x14032a) 123 #define reg_gpio_pf_out REG_ADDR8(0x14032b) 124 125 #define reg_gpio_pf_setting2 REG_ADDR32(0x14032c) 126 #define reg_gpio_pf_ds REG_ADDR8(0x14032d) 127 #define reg_gpio_pf_gpio REG_ADDR8(0x14032e) 128 129 #define reg_gpio_pf_fs REG_ADDR16(0x140356) 130 #define reg_gpio_pf_fuc_l REG_ADDR8(0x140356) 131 #define reg_gpio_pf_fuc_h REG_ADDR8(0x140357) 132 133 #define reg_gpio_in(i) REG_ADDR8(0x140300+((i>>8)<<3)) 134 #define reg_gpio_ie(i) REG_ADDR8(0x140301+((i>>8)<<3)) 135 #define reg_gpio_oen(i) REG_ADDR8(0x140302+((i>>8)<<3)) 136 #define reg_gpio_out(i) REG_ADDR8(0x140303+((i>>8)<<3)) 137 #define reg_gpio_pol(i) REG_ADDR8(0x140304+((i>>8)<<3)) 138 #define reg_gpio_ds(i) REG_ADDR8(0x140305+((i>>8)<<3)) 139 140 141 #define reg_gpio_func(i) REG_ADDR8(0x140306+((i>>8)<<3)) 142 #define reg_gpio_irq_en(i) REG_ADDR8(0x140307+((i>>8)<<3)) // reg_irq_mask: FLD_IRQ_GPIO_EN 143 #define reg_gpio_irq_risc0_en(i) REG_ADDR8(0x140338 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC0_EN 144 #define reg_gpio_irq_risc1_en(i) REG_ADDR8(0x140340 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC1_EN 145 146 #define reg_gpio_func_mux(i) REG_ADDR8(0x140330 + (((i>>8)>3) ? 0x20 : ((i>>8)<<1) ) + ((i&0x0f0) ? 1 : 0 )) 147 148 149 #define reg_gpio_irq_risc_mask REG_ADDR8(0x140352) 150 enum{ 151 FLD_GPIO_IRQ_MASK_GPIO = BIT(0), 152 FLD_GPIO_IRQ_MASK_GPIO2RISC0 = BIT(1), 153 FLD_GPIO_IRQ_MASK_GPIO2RISC1 = BIT(2), 154 155 FLD_GPIO_IRQ_LVL_GPIO = BIT(4), 156 FLD_GPIO_IRQ_LVL_GPIO2RISC0 = BIT(5), 157 FLD_GPIO_IRQ_LVL_GPIO2RISC1 = BIT(6), 158 159 }; 160 #define reg_gpio_irq_ctrl REG_ADDR8(0x140353) 161 enum{ 162 FLD_GPIO_CORE_WAKEUP_EN = BIT(2), 163 FLD_GPIO_CORE_INTERRUPT_EN = BIT(3), 164 }; 165 #define reg_gpio_pad_mul_sel REG_ADDR8(0x140355) 166 167 #define reg_gpio_irq_clr REG_ADDR8(0x140358) 168 typedef enum{ 169 FLD_GPIO_IRQ_CLR = BIT(0), 170 FLD_GPIO_IRQ_GPIO2RISC0_CLR = BIT(1), 171 FLD_GPIO_IRQ_GPIO2RISC1_CLR = BIT(2), 172 }gpio_irq_status_e; 173 174 #endif 175
