1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file audio_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef AUDIO_REG_H 28 #define AUDIO_REG_H 29 #include "../sys.h" 30 31 #define REG_AUDIO_AHB_BASE 0x120000 32 #define REG_CODEC_BASE_ADDR 0x120200 33 #define REG_AUDIO_APB_BASE 0x140500 34 #define reg_fifo_buf_adr(i) REG_AUDIO_AHB_BASE+(i)*0x40 35 #define reg_audio_en REG_ADDR8(REG_AUDIO_APB_BASE+0x00) 36 enum 37 { 38 FLD_AUDIO_I2S_CLK_EN = BIT(0), 39 FLD_AUDIO_CLK_DIV2 = BIT(1), 40 FLD_AUDIO_MC_CLK_EN = BIT(2), 41 FLD_AUDIO_MC_CLK_INV_O = BIT(3), 42 }; 43 44 #define reg_i2s_cfg REG_ADDR8(REG_AUDIO_APB_BASE+0x01) 45 enum 46 { 47 FLD_AUDIO_I2S_FORMAT = BIT_RNG(0,1), 48 FLD_AUDIO_I2S_WL = BIT_RNG(2,3), 49 FLD_AUDIO_I2S_LRP = BIT(4), 50 FLD_AUDIO_I2S_LRSWAP = BIT(5), 51 FLD_AUDIO_I2S_ADC_DCI_MS = BIT(6), 52 FLD_AUDIO_I2S_DAC_DCI_MS = BIT(7), 53 }; 54 55 #define reg_i2s_cfg2 REG_ADDR8(REG_AUDIO_APB_BASE+0x02) 56 57 enum 58 { 59 FLD_AUDIO_FIFO1_RST = BIT(3), 60 }; 61 #define reg_audio_ctrl REG_ADDR8(REG_AUDIO_APB_BASE+0x03) 62 enum 63 { 64 FLD_AUDIO_I2S_CMODE = BIT_RNG(0,1), 65 FLD_AUDIO_CODEC_I2S_SEL = BIT(2), 66 FLD_AUDIO_I2S_OUT_BIT_SEL = BIT(3), 67 }; 68 69 #define reg_audio_tune REG_ADDR8(REG_AUDIO_APB_BASE+0x04) 70 enum 71 { 72 FLD_AUDIO_I2S_I2S_AIN0_COME = BIT_RNG(0,1), 73 FLD_AUDIO_I2S_I2S_AIN1_COME = BIT_RNG(2,3), 74 FLD_AUDIO_I2S_I2S_AOUT_COME = BIT_RNG(4,6), 75 }; 76 77 78 #define reg_audio_sel REG_ADDR8(REG_AUDIO_APB_BASE+0x05) 79 enum 80 { 81 FLD_AUDIO_AIN0_SEL = BIT_RNG(0,1), 82 FLD_AUDIO_AOUT0_SEL = BIT_RNG(2,3), 83 FLD_AUDIO_AIN1_SEL = BIT_RNG(4,5), 84 FLD_AUDIO_AOUT1_SEL = BIT_RNG(6,7), 85 }; 86 87 #define reg_audio_i2c_addr REG_ADDR8(REG_AUDIO_APB_BASE+0x08) 88 #define reg_audio_i2c_mode REG_ADDR8(REG_AUDIO_APB_BASE+0x09) 89 90 #define reg_fifo_trig0 REG_ADDR8(REG_AUDIO_APB_BASE+0x0a) 91 92 #define reg_audio_ptr_set REG_ADDR8(REG_AUDIO_APB_BASE+0x10) 93 enum 94 { 95 FLD_AUDIO_TX_PTR_SEL = BIT(0), 96 FLD_AUDIO_RX_PTR_SEL = BIT(4), 97 }; 98 99 #define reg_audio_ptr_en REG_ADDR8(REG_AUDIO_APB_BASE+0x11) 100 enum 101 { 102 FLD_AUDIO_TX_WPTR_PTR_EN = BIT(0), 103 FLD_AUDIO_TX_RPTR_PTR_EN = BIT(1), 104 FLD_AUDIO_RX_WPTR_PTR_EN = BIT(2), 105 FLD_AUDIO_RX_RPTR_PTR_EN = BIT(3), 106 107 }; 108 109 enum 110 { 111 FLD_AUDIO_FIFO_AOUT0_TRIG_NUM = BIT_RNG(0,3), 112 FLD_AUDIO_FIFO_AIN0_TRIG_NUM = BIT_RNG(4,7), 113 }; 114 115 #define fifo_trig1 REG_ADDR8(REG_AUDIO_APB_BASE+0x0b) 116 117 enum 118 { 119 FLD_AUDIO_FIFO_AOUT1_TRIG_NUM = BIT_RNG(0,3), 120 FLD_AUDIO_FIFO_AIN1_TRIG_NUM = BIT_RNG(4,7), 121 }; 122 123 #define reg_tx_wptr REG_ADDR16(REG_AUDIO_APB_BASE+0x20) 124 #define reg_tx_rptr REG_ADDR16(REG_AUDIO_APB_BASE+0x22) 125 126 #define reg_tx_max REG_ADDR16(REG_AUDIO_APB_BASE+0x26) 127 128 #define reg_rx_rptr REG_ADDR16(REG_AUDIO_APB_BASE+0x2a) 129 #define reg_rx_wptr REG_ADDR16(REG_AUDIO_APB_BASE+0x28) 130 131 #define reg_rx_max REG_ADDR16(REG_AUDIO_APB_BASE+0x2e) 132 133 #define reg_th0_h1 REG_ADDR16(REG_AUDIO_APB_BASE+0x30)//tx 134 #define reg_th0_l1 REG_ADDR16(REG_AUDIO_APB_BASE+0x32)//tx 135 136 #define reg_th0_h2 REG_ADDR16(REG_AUDIO_APB_BASE+0x38)//tx 137 #define reg_th0_l2 REG_ADDR16(REG_AUDIO_APB_BASE+0x3a)//tx 138 139 140 #define reg_th1_h1 REG_ADDR16(REG_AUDIO_APB_BASE+0x40)//rx 141 #define reg_th1_l1 REG_ADDR16(REG_AUDIO_APB_BASE+0x42)//rx 142 143 #define reg_th1_h2 REG_ADDR16(REG_AUDIO_APB_BASE+0x48)//rx 144 #define reg_th1_l2 REG_ADDR16(REG_AUDIO_APB_BASE+0x4a)//rx 145 146 147 148 #define reg_irq_fifo_state REG_ADDR8(REG_AUDIO_APB_BASE+0x5c) 149 typedef enum 150 { 151 FLD_AUDIO_IRQ_TXFIFO_L_L1 = BIT(0), 152 FLD_AUDIO_IRQ_TXFIFO_H_L1 = BIT(1), 153 FLD_AUDIO_IRQ_TXFIFO_L_L2 = BIT(2), 154 FLD_AUDIO_IRQ_TXFIFO_H_L2 = BIT(3), 155 156 FLD_AUDIO_IRQ_RXFIFO_L_L1 = BIT(4), 157 FLD_AUDIO_IRQ_RXFIFO_H_L1 = BIT(5), 158 FLD_AUDIO_IRQ_RXFIFO_L_L2 = BIT(6), 159 FLD_AUDIO_IRQ_RXFIFO_H_L2 = BIT(7), 160 161 }audio_fifo_irq_status_type_e; 162 163 #define reg_irq_fifo_mask REG_ADDR8(REG_AUDIO_APB_BASE+0x5d) 164 165 typedef enum 166 { 167 FLD_AUDIO_IRQ_TXFIFO_L_L1_EN = BIT(0), 168 FLD_AUDIO_IRQ_TXFIFO_H_L1_EN = BIT(1), 169 FLD_AUDIO_IRQ_TXFIFO_L_L2_EN = BIT(2), 170 FLD_AUDIO_IRQ_TXFIFO_H_L2_EN = BIT(3), 171 172 FLD_AUDIO_IRQ_RXFIFO_L_L1_EN = BIT(4), 173 FLD_AUDIO_IRQ_RXFIFO_H_L1_EN = BIT(5), 174 FLD_AUDIO_IRQ_RXFIFO_L_L2_EN = BIT(6), 175 FLD_AUDIO_IRQ_RXFIFO_H_L2_EN = BIT(7), 176 177 }audio_fifo_irq_mask_type_e; 178 179 180 181 #define reg_irq_manual_en REG_ADDR8(REG_AUDIO_APB_BASE+0x5e) 182 enum 183 { 184 FLD_AUDIO_IRQ_TXFIFO_L_L1_MAN_EN = BIT(0), 185 FLD_AUDIO_IRQ_TXFIFO_H_L1_MAN_EN = BIT(1), 186 FLD_AUDIO_IRQ_TXFIFO_L_L2_MAN_EN = BIT(2), 187 FLD_AUDIO_IRQ_TXFIFO_H_L2_MAN_EN = BIT(3), 188 189 FLD_AUDIO_IRQ_RXFIFO_L_L1_MAN_EN = BIT(4), 190 FLD_AUDIO_IRQ_RXFIFO_H_L1_MAN_EN = BIT(5), 191 FLD_AUDIO_IRQ_RXFIFO_L_L2_MAN_EN = BIT(6), 192 FLD_AUDIO_IRQ_RXFIFO_H_L2_MAN_EN = BIT(7) 193 194 }; 195 196 #define reg_int_pcm_num REG_ADDR16(REG_AUDIO_APB_BASE+0x50) 197 #define reg_dec_pcm_num REG_ADDR16(REG_AUDIO_APB_BASE+0x52) 198 199 #define reg_pcm_clk_num REG_ADDR8(REG_AUDIO_APB_BASE+0x54) 200 201 202 203 #define reg_audio_codec_stat_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x00<<2)) 204 #define addr_audio_codec_stat_ctr 0x00 205 enum 206 { 207 FLD_AUDIO_CODEC_ADC12_LOCKED = BIT(3), 208 FLD_AUDIO_CODEC_DAC_LOCKED = BIT(4), 209 FLD_AUDIO_CODEC_PON_ACK = BIT(7), 210 }; 211 212 213 #define reg_audio_codec_vic_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x06<<2)) 214 #define addr_audio_codec_vic_ctr 0x06 215 enum 216 { 217 FLD_AUDIO_CODEC_SB = BIT(0), 218 FLD_AUDIO_CODEC_SB_ANALOG = BIT(1), 219 FLD_AUDIO_CODEC_SLEEP_ANALOG = BIT(2), 220 }; 221 222 223 224 #define reg_audio_codec_dac_itf_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x08<<2)) 225 #define addr_audio_codec_dac_itf_ctr 0x08 226 227 #define reg_audio_codec_adc_itf_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x09<<2)) 228 #define addr_audio_codec_adc_itf_ctr 0x09 229 enum 230 { 231 FLD_AUDIO_CODEC_FORMAT = BIT_RNG(0,1), 232 FLD_AUDIO_CODEC_DAC_ITF_SB = BIT(4), 233 FLD_AUDIO_CODEC_SLAVE = BIT(5), 234 FLD_AUDIO_CODEC_WL = BIT_RNG(6,7), 235 }; 236 237 #define reg_audio_codec_adc2_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x0a<<2)) 238 #define addr_audio_codec_adc2_ctr 0x0a 239 enum 240 { 241 FLD_AUDIO_CODEC_ADC12_SB = BIT(0), 242 }; 243 244 #define reg_audio_codec_dac_freq_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x0b<<2)) 245 #define addr_audio_codec_dac_freq_ctr 0x0b 246 enum 247 { 248 FLD_AUDIO_CODEC_DAC_FREQ = BIT_RNG(0,3), 249 }; 250 251 #define reg_audio_codec_adc_wnf_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x0e<<2)) 252 #define addr_audio_codec_adc_wnf_ctr 0x0e 253 enum 254 { 255 FLD_AUDIO_CODEC_ADC12_WNF = BIT_RNG(0,1), 256 }; 257 258 259 260 #define reg_audio_codec_adc_freq_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x0f<<2)) 261 #define addr_audio_codec_adc_freq_ctr 0x0f 262 enum 263 { 264 FLD_AUDIO_CODEC_ADC_FREQ = BIT_RNG(0,3), 265 FLD_AUDIO_CODEC_ADC12_HPF_EN = BIT(4), 266 }; 267 268 269 270 #define reg_audio_dmic_12 REG_ADDR8(REG_CODEC_BASE_ADDR+(0x10<<2)) 271 #define addr_audio_dmic_12 0x10 272 enum 273 { 274 FLD_AUDIO_CODEC_ADC_DMIC_SEL2 = BIT_RNG(0,1), 275 FLD_AUDIO_CODEC_ADC_DMIC_SEL1 = BIT_RNG(2,3), 276 FLD_AUDIO_CODEC_DMIC2_SB = BIT(6), 277 FLD_AUDIO_CODEC_DMIC1_SB = BIT(7), 278 }; 279 280 281 #define reg_audio_codec_hpl_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x15<<2)) 282 #define addr_audio_codec_hpl_gain 0x15 283 284 enum 285 { 286 FLD_AUDIO_CODEC_HPL_GOL = BIT_RNG(0,4), 287 FLD_AUDIO_CODEC_HPL_LRGO = BIT(7), 288 }; 289 290 #define reg_audio_codec_hpr_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x16<<2)) 291 #define addr_audio_codec_hpr_gain 0x16 292 enum 293 { 294 FLD_AUDIO_CODEC_HPR_GOR = BIT_RNG(0,4), 295 }; 296 297 298 #define reg_audio_codec_mic1_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x17<<2)) 299 #define addr_audio_codec_mic1_ctr 0x17 300 301 enum 302 { 303 FLD_AUDIO_CODEC_MIC1_SEL = BIT(0), 304 FLD_AUDIO_CODEC_MICBIAS1_SB = BIT(5), 305 FLD_AUDIO_CODEC_MIC_DIFF1 = BIT(6), 306 FLD_AUDIO_CODEC_MICBIAS1_V = BIT(7), 307 }; 308 309 #define reg_audio_codec_mic2_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x18<<2)) 310 #define addr_audio_codec_mic2_ctr 0x18 311 enum 312 { 313 FLD_AUDIO_CODEC_MIC2_SEL = BIT(0), 314 FLD_AUDIO_CODEC_MIC_DIFF2 = BIT(6), 315 }; 316 317 318 319 #define reg_audio_codec_dacl_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x2a<<2)) 320 #define addr_audio_codec_dacl_gain 0x2a 321 enum 322 { 323 FLD_AUDIO_CODEC_DAC_GODL = BIT_RNG(0,5), 324 FLD_AUDIO_CODEC_DAC_LRGOD = BIT(7), 325 }; 326 327 #define reg_audio_codec_dacr_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x2b<<2)) 328 #define addr_audio_codec_dacr_gain 0x2b 329 enum 330 { 331 FLD_AUDIO_CODEC_DAC_GODR = BIT_RNG(0,5), 332 }; 333 334 #define reg_audio_codec_mic_l_R_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x1f<<2)) 335 #define addr_audio_codec_mic_l_R_gain 0x1f 336 enum 337 { 338 FLD_AUDIO_CODEC_AMIC_L_GAIN = BIT_RNG(0,2), 339 FLD_AUDIO_CODEC_AMIC_R_GAIN = BIT_RNG(3,5), 340 }; 341 342 343 #define reg_audio_codec_dac_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x23<<2)) 344 #define addr_audio_codec_dac_ctr 0x23 345 enum 346 { 347 FLD_AUDIO_CODEC_DAC_SB = BIT(4), 348 FLD_AUDIO_CODEC_DAC_LEFT_ONLY = BIT(5), 349 FLD_AUDIO_CODEC_DAC_SOFT_MUTE = BIT(7), 350 }; 351 352 353 354 #define reg_audio_codec_adc12_ctr REG_ADDR8(REG_CODEC_BASE_ADDR+(0x24<<2)) 355 #define addr_audio_codec_adc12_ctr 0x24 356 enum 357 { 358 FLD_AUDIO_CODEC_ADC1_SB = BIT(4), 359 FLD_AUDIO_CODEC_ADC2_SB = BIT(5), 360 FLD_AUDIO_CODEC_ADC12_SOFT_MUTE = BIT(7), 361 }; 362 363 364 #define reg_audio_adc1_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x2c<<2)) 365 #define addr_audio_adc1_gain 0x2c 366 enum 367 { 368 FLD_AUDIO_CODEC_ADC_GID1 = BIT_RNG(0,5), 369 FLD_AUDIO_CODEC_ADC_LRGID = BIT(7), 370 }; 371 372 #define reg_audio_adc2_gain REG_ADDR8(REG_CODEC_BASE_ADDR+(0x2d<<2)) 373 enum 374 { 375 FLD_AUDIO_CODEC_ADC_GID2 = BIT_RNG(0,5), 376 377 }; 378 379 380 #endif 381
