1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2017 BayLibre, SAS.
4 * Copyright (c) 2023 Google Inc
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
10 #define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
11
12 #include <zephyr/drivers/flash.h>
13
14 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
15 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
16 #include <zephyr/drivers/clock_control.h>
17 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
18 #endif
19
20 struct flash_stm32_priv {
21 FLASH_TypeDef *regs;
22 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
23 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
24 /* clock subsystem driving this peripheral */
25 struct stm32_pclken pclken;
26 #endif
27 struct k_sem sem;
28 };
29
30 #if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
31 #define FLASH_STM32_WRITE_BLOCK_SIZE \
32 DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
33 #else
34 #error Flash write block size not available
35 /* Flash Write block size is extracted from device tree */
36 /* as flash node property 'write-block-size' */
37 #endif
38
39 #if defined(CONFIG_SOC_SERIES_STM32H5X)
40 /* FLASH register names differ for this serie */
41 #define FLASH_NSSR_BSY FLASH_SR_BSY
42 #define OPTR OPTCR
43 #endif /* CONFIG_SOC_SERIES_STM32H5X */
44
45 /* Differentiate between arm trust-zone non-secure/secure, and others. */
46 #if defined(FLASH_NSSR_NSBSY) || defined(FLASH_NSSR_BSY) /* For mcu w. TZ in non-secure mode */
47 #define FLASH_SECURITY_NS
48 #define FLASH_STM32_SR NSSR
49 #elif defined(FLASH_SECSR_SECBSY) /* For mcu w. TZ in secured mode */
50 #error Flash is not supported in secure mode
51 #define FLASH_SECURITY_SEC
52 #else
53 #define FLASH_SECURITY_NA /* For series which does not have
54 * secured or non-secured mode
55 */
56 #define FLASH_STM32_SR SR
57 #endif
58
59
60 #define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
61 #define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
62
63
64 /* Redefinitions of flags and masks to harmonize stm32 series: */
65 #if defined(CONFIG_SOC_SERIES_STM32U5X)
66 #define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK
67 #define FLASH_STM32_DBANK FLASH_OPTR_DUALBANK
68 #define FLASH_STM32_NSPG FLASH_NSCR_PG
69 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_BKER_Msk
70 #define FLASH_STM32_NSBKER FLASH_NSCR_BKER
71 #define FLASH_STM32_NSPER FLASH_NSCR_PER
72 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_PNB_Msk
73 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_PNB_Pos
74 #define FLASH_STM32_NSPNB FLASH_NSCR_PNB
75 #define FLASH_STM32_NSSTRT FLASH_NSCR_STRT
76 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
77 #elif defined(CONFIG_SOC_SERIES_STM32H5X)
78 #define FLASH_OPTR_SWAP_BANK FLASH_OPTCR_SWAP_BANK
79 #define FLASH_STM32_NSLOCK FLASH_CR_LOCK
80 #define FLASH_STM32_DBANK 1
81 #define FLASH_STM32_NSPG FLASH_CR_PG
82 #define FLASH_STM32_NSBKER_MSK FLASH_CR_BKSEL_Msk
83 #define FLASH_STM32_NSBKER FLASH_CR_BKSEL
84 #define FLASH_STM32_NSPER FLASH_CR_SER
85 #define FLASH_STM32_NSPNB_MSK FLASH_CR_SNB_Msk
86 #define FLASH_STM32_NSPNB_POS FLASH_CR_SNB_Pos
87 #define FLASH_STM32_NSPNB FLASH_CR_PNB
88 #define FLASH_STM32_NSSTRT FLASH_CR_START
89 /* TODO: get values from the cmsis and stm32h5_hal_flash.h */
90 #undef FLASH_SIZE
91 /* Retrieve the FLASH SIZE from the DTS instead of cmsis as it seems erroneous */
92 #define FLASH_SIZE (CONFIG_FLASH_SIZE * 1024)
93 /* Values are redefined below from the stm32h5_hal_flash.h */
94 #define FLASH_PAGE_SIZE (FLASH_SECTOR_SIZE)
95 #define FLASH_PAGE_NB (FLASH_SECTOR_NB)
96 #define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
97 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
98 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
99 #define FLASH_STM32_NSLOCK FLASH_NSCR_NSLOCK
100 #define FLASH_STM32_NSPG FLASH_NSCR_NSPG
101 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_NSBKER_Pos
102 #define FLASH_STM32_NSBKER FLASH_NSCR_NSBKER
103 #define FLASH_STM32_NSPER FLASH_NSCR_NSPER
104 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_NSPNB_Msk
105 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_NSPNB_Pos
106 #define FLASH_STM32_NSPNB FLASH_NSCR_NSPNB
107 #define FLASH_STM32_NSSTRT FLASH_NSCR_NSSTRT
108 #elif defined(CONFIG_SOC_SERIES_STM32WBAX)
109 #define NSCR NSCR1
110 #define FLASH_STM32_NSLOCK FLASH_NSCR1_LOCK
111 #define FLASH_STM32_NSPG FLASH_NSCR1_PG
112 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR1_BKER_Msk
113 #define FLASH_STM32_NSBKER FLASH_NSCR1_BKER
114 #define FLASH_STM32_NSPER FLASH_NSCR1_PER
115 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR1_PNB_Msk
116 #define FLASH_STM32_NSPNB_POS FLASH_NSCR1_PNB_Pos
117 #define FLASH_STM32_NSPNB FLASH_NSCR1_PNB
118 #define FLASH_STM32_NSSTRT FLASH_NSCR1_STRT
119 #endif /* CONFIG_SOC_SERIES_STM32U5X */
120 #if defined(FLASH_OPTR_DBANK)
121 #define FLASH_STM32_DBANK FLASH_OPTR_DBANK
122 #endif /* FLASH_OPTR_DBANK */
123
124 #if defined(CONFIG_SOC_SERIES_STM32G0X)
125 #if defined(FLASH_FLAG_BSY2)
126 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);
127 #else
128 #define FLASH_STM32_SR_BUSY (FLASH_SR_BSY1)
129 #endif /* defined(FLASH_FLAG_BSY2) */
130 #else
131 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY)
132 #endif
133
134 #if defined(CONFIG_SOC_SERIES_STM32G0X)
135 #define FLASH_STM32_SR_CFGBSY (FLASH_SR_CFGBSY)
136 #elif defined(FLASH_FLAG_CFGBSY)
137 #define FLASH_STM32_SR_CFGBSY (FLASH_FLAG_CFGBSY)
138 #endif
139
140 #if defined(CONFIG_SOC_SERIES_STM32G0X)
141 /* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */
142 #define FLASH_STM32_SR_OPERR FLASH_SR_OPERR
143 #define FLASH_STM32_SR_PGERR 0
144 #define FLASH_STM32_SR_PROGERR FLASH_SR_PROGERR
145 #define FLASH_STM32_SR_WRPERR FLASH_SR_WRPERR
146 #define FLASH_STM32_SR_PGAERR FLASH_SR_PGAERR
147 #define FLASH_STM32_SR_SIZERR FLASH_SR_SIZERR
148 #define FLASH_STM32_SR_PGSERR FLASH_SR_PGSERR
149 #define FLASH_STM32_SR_MISERR FLASH_SR_MISERR
150 #define FLASH_STM32_SR_FASTERR FLASH_SR_FASTERR
151 #if defined(FLASH_SR_RDERR)
152 #define FLASH_STM32_SR_RDERR FLASH_SR_RDERR
153 #else
154 #define FLASH_STM32_SR_RDERR 0
155 #endif
156 #define FLASH_STM32_SR_PGPERR 0
157
158 #else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
159 #if defined(FLASH_FLAG_OPERR)
160 #define FLASH_STM32_SR_OPERR FLASH_FLAG_OPERR
161 #else
162 #define FLASH_STM32_SR_OPERR 0
163 #endif
164
165 #if defined(FLASH_FLAG_PGERR)
166 #define FLASH_STM32_SR_PGERR FLASH_FLAG_PGERR
167 #else
168 #define FLASH_STM32_SR_PGERR 0
169 #endif
170
171 #if defined(FLASH_FLAG_PROGERR)
172 #define FLASH_STM32_SR_PROGERR FLASH_FLAG_PROGERR
173 #else
174 #define FLASH_STM32_SR_PROGERR 0
175 #endif
176
177 #if defined(FLASH_FLAG_WRPERR)
178 #define FLASH_STM32_SR_WRPERR FLASH_FLAG_WRPERR
179 #else
180 #define FLASH_STM32_SR_WRPERR 0
181 #endif
182
183 #if defined(FLASH_FLAG_PGAERR)
184 #define FLASH_STM32_SR_PGAERR FLASH_FLAG_PGAERR
185 #else
186 #define FLASH_STM32_SR_PGAERR 0
187 #endif
188
189 #if defined(FLASH_FLAG_SIZERR)
190 #define FLASH_STM32_SR_SIZERR FLASH_FLAG_SIZERR
191 #else
192 #define FLASH_STM32_SR_SIZERR 0
193 #endif
194
195 #if defined(FLASH_FLAG_PGSERR)
196 #define FLASH_STM32_SR_PGSERR FLASH_FLAG_PGSERR
197 #else
198 #define FLASH_STM32_SR_PGSERR 0
199 #endif
200
201 #if defined(FLASH_FLAG_MISERR)
202 #define FLASH_STM32_SR_MISERR FLASH_FLAG_MISERR
203 #else
204 #define FLASH_STM32_SR_MISERR 0
205 #endif
206
207 #if defined(FLASH_FLAG_FASTERR)
208 #define FLASH_STM32_SR_FASTERR FLASH_FLAG_FASTERR
209 #else
210 #define FLASH_STM32_SR_FASTERR 0
211 #endif
212
213 #if defined(FLASH_FLAG_RDERR)
214 #define FLASH_STM32_SR_RDERR FLASH_FLAG_RDERR
215 #else
216 #define FLASH_STM32_SR_RDERR 0
217 #endif
218
219 #if defined(FLASH_FLAG_PGPERR)
220 #define FLASH_STM32_SR_PGPERR FLASH_FLAG_PGPERR
221 #else
222 #define FLASH_STM32_SR_PGPERR 0
223 #endif
224
225 #endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
226
227 #define FLASH_STM32_SR_ERRORS (FLASH_STM32_SR_OPERR | \
228 FLASH_STM32_SR_PGERR | \
229 FLASH_STM32_SR_PROGERR | \
230 FLASH_STM32_SR_WRPERR | \
231 FLASH_STM32_SR_PGAERR | \
232 FLASH_STM32_SR_SIZERR | \
233 FLASH_STM32_SR_PGSERR | \
234 FLASH_STM32_SR_MISERR | \
235 FLASH_STM32_SR_FASTERR | \
236 FLASH_STM32_SR_RDERR | \
237 FLASH_STM32_SR_PGPERR)
238
239 #define FLASH_STM32_RDP0 0xAA
240 #define FLASH_STM32_RDP2 0xCC
241 #define FLASH_STM32_RDP1 \
242 DT_PROP(DT_INST(0, st_stm32_flash_controller), st_rdp1_enable_byte)
243
244 #if FLASH_STM32_RDP1 == FLASH_STM32_RDP0 || FLASH_STM32_RDP1 == FLASH_STM32_RDP2
245 #error RDP1 byte has to be different than RDP0 and RDP2 byte
246 #endif
247
248 #ifdef CONFIG_FLASH_PAGE_LAYOUT
flash_stm32_range_exists(const struct device * dev,off_t offset,uint32_t len)249 static inline bool flash_stm32_range_exists(const struct device *dev,
250 off_t offset,
251 uint32_t len)
252 {
253 struct flash_pages_info info;
254
255 return !(flash_get_page_info_by_offs(dev, offset, &info) ||
256 flash_get_page_info_by_offs(dev, offset + len - 1, &info));
257 }
258 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
259
flash_stm32_valid_write(off_t offset,uint32_t len)260 static inline bool flash_stm32_valid_write(off_t offset, uint32_t len)
261 {
262 return ((offset % FLASH_STM32_WRITE_BLOCK_SIZE == 0) &&
263 (len % FLASH_STM32_WRITE_BLOCK_SIZE == 0U));
264 }
265
266 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
267 uint32_t len, bool write);
268
269 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
270 const void *data, unsigned int len);
271
272 int flash_stm32_block_erase_loop(const struct device *dev,
273 unsigned int offset,
274 unsigned int len);
275
276 int flash_stm32_wait_flash_idle(const struct device *dev);
277
278 int flash_stm32_option_bytes_lock(const struct device *dev, bool enable);
279
280 #ifdef CONFIG_SOC_SERIES_STM32WBX
281 int flash_stm32_check_status(const struct device *dev);
282 #endif /* CONFIG_SOC_SERIES_STM32WBX */
283
284 #ifdef CONFIG_FLASH_PAGE_LAYOUT
285 void flash_stm32_page_layout(const struct device *dev,
286 const struct flash_pages_layout **layout,
287 size_t *layout_size);
288 #endif
289
290 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
291
292 int flash_stm32_update_wp_sectors(const struct device *dev,
293 uint32_t changed_sectors,
294 uint32_t protected_sectors);
295
296 int flash_stm32_get_wp_sectors(const struct device *dev,
297 uint32_t *protected_sectors);
298 #endif
299 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
300
301 int flash_stm32_update_rdp(const struct device *dev, bool enable,
302 bool permanent);
303
304 int flash_stm32_get_rdp(const struct device *dev, bool *enabled,
305 bool *permanent);
306 #endif
307
308 /* Flash extended operations */
309 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
310 int flash_stm32_ex_op_sector_wp(const struct device *dev, const uintptr_t in,
311 void *out);
312 #endif
313 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
314 int flash_stm32_ex_op_rdp(const struct device *dev, const uintptr_t in,
315 void *out);
316 #endif
317
318 #endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
319
