1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _NUVOTON_NPCX_REG_DEF_H
8 #define _NUVOTON_NPCX_REG_DEF_H
9
10 #include <stdint.h>
11
12 #include <zephyr/devicetree.h>
13 #include <zephyr/sys/__assert.h>
14 #include <zephyr/sys/util_macro.h>
15 #include <zephyr/toolchain.h>
16
17 /*
18 * NPCX register structure size/offset checking macro function to mitigate
19 * the risk of unexpected compiling results. All addresses of NPCX registers
20 * must meet the alignment requirement of cortex-m4.
21 * DO NOT use 'packed' attribute if module contains different length ie.
22 * 8/16/32 bits registers.
23 */
24 #define NPCX_REG_SIZE_CHECK(reg_def, size) \
25 BUILD_ASSERT(sizeof(struct reg_def) == size, \
26 "Failed in size check of register structure!")
27 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
28 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
29 "Failed in offset check of register structure member!")
30
31 /*
32 * NPCX register access checking via structure macro function to mitigate the
33 * risk of unexpected compiling results if module contains different length
34 * registers. For example, a word register access might break into two byte
35 * register accesses by adding 'packed' attribute.
36 *
37 * For example, add this macro for word register 'PRSC' of PWM module in its
38 * device init function for checking violation. Once it occurred, core will be
39 * stalled forever and easy to find out what happens.
40 */
41 #define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
42 uint16_t placeholder = reg; \
43 reg = val; \
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
45 reg = placeholder; \
46 }
47 #define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
48 uint32_t placeholder = reg; \
49 reg = val; \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
51 reg = placeholder; \
52 }
53 /*
54 * Core Domain Clock Generator (CDCG) device registers
55 */
56 struct cdcg_reg {
57 /* High Frequency Clock Generator (HFCG) registers */
58 /* 0x000: HFCG Control */
59 volatile uint8_t HFCGCTRL;
60 volatile uint8_t reserved1;
61 /* 0x002: HFCG M Low Byte Value */
62 volatile uint8_t HFCGML;
63 volatile uint8_t reserved2;
64 /* 0x004: HFCG M High Byte Value */
65 volatile uint8_t HFCGMH;
66 volatile uint8_t reserved3;
67 /* 0x006: HFCG N Value */
68 volatile uint8_t HFCGN;
69 volatile uint8_t reserved4;
70 /* 0x008: HFCG Prescaler */
71 volatile uint8_t HFCGP;
72 volatile uint8_t reserved5[7];
73 /* 0x010: HFCG Bus Clock Dividers */
74 volatile uint8_t HFCBCD;
75 volatile uint8_t reserved6;
76 /* 0x012: HFCG Bus Clock Dividers */
77 volatile uint8_t HFCBCD1;
78 volatile uint8_t reserved7;
79 /* 0x014: HFCG Bus Clock Dividers */
80 volatile uint8_t HFCBCD2;
81 volatile uint8_t reserved12[8];
82 /* 0x01d: HFCG Bus Clock Dividers */
83 volatile uint8_t HFCBCD3;
84 volatile uint8_t reserved8[226];
85
86 /* Low Frequency Clock Generator (LFCG) registers */
87 /* 0x100: LFCG Control */
88 volatile uint8_t LFCGCTL;
89 volatile uint8_t reserved9;
90 /* 0x102: High-Frequency Reference Divisor I */
91 volatile uint16_t HFRDI;
92 /* 0x104: High-Frequency Reference Divisor F */
93 volatile uint16_t HFRDF;
94 /* 0x106: FRCLK Clock Divisor */
95 volatile uint16_t FRCDIV;
96 /* 0x108: Divisor Correction Value 1 */
97 volatile uint16_t DIVCOR1;
98 /* 0x10A: Divisor Correction Value 2 */
99 volatile uint16_t DIVCOR2;
100 volatile uint8_t reserved10[8];
101 /* 0x114: LFCG Control 2 */
102 volatile uint8_t LFCGCTL2;
103 volatile uint8_t reserved11;
104 };
105
106 /* CDCG register fields */
107 #define NPCX_HFCGCTRL_LOAD 0
108 #define NPCX_HFCGCTRL_LOCK 2
109 #define NPCX_HFCGCTRL_CLK_CHNG 7
110
111 #define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
112
113 /*
114 * Power Management Controller (PMC) device registers
115 */
116 struct pmc_reg {
117 /* 0x000: Power Management Controller */
118 volatile uint8_t PMCSR;
119 volatile uint8_t reserved1[2];
120 /* 0x003: Enable in Sleep Control */
121 volatile uint8_t ENIDL_CTL;
122 /* 0x004: Disable in Idle Control */
123 volatile uint8_t DISIDL_CTL;
124 /* 0x005: Disable in Idle Control 1 */
125 volatile uint8_t DISIDL_CTL1;
126 volatile uint8_t reserved2[2];
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
128 volatile uint8_t PWDWN_CTL1[6];
129 volatile uint8_t reserved3[18];
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
131 volatile uint8_t RAM_PD[2];
132 volatile uint8_t reserved4[2];
133 /* 0x024: Power-Down Control 7 */
134 volatile uint8_t PWDWN_CTL7[1];
135 };
136
137 /* PMC internal inline functions for multi-registers */
npcx_pwdwn_ctl_offset(uint32_t ctl_no)138 static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
139 {
140 if (ctl_no < 6) {
141 return 0x008 + ctl_no;
142 } else {
143 return 0x024 + ctl_no - 6;
144 }
145 }
146
147 /* Macro functions for PMC multi-registers */
148 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
149 npcx_pwdwn_ctl_offset(n)))
150
151 /* PMC register fields */
152 #define NPCX_PMCSR_DI_INSTW 0
153 #define NPCX_PMCSR_DHF 1
154 #define NPCX_PMCSR_IDLE 2
155 #define NPCX_PMCSR_NWBI 3
156 #define NPCX_PMCSR_OHFC 6
157 #define NPCX_PMCSR_OLFC 7
158 #define NPCX_DISIDL_CTL_RAM_DID 5
159 #define NPCX_ENIDL_CTL_ADC_LFSL 7
160 #define NPCX_ENIDL_CTL_LP_WK_CTL 6
161 #define NPCX_ENIDL_CTL_PECI_ENI 2
162 #define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
163
164 /* Macro functions for Development and Debugger Interface (DDI) registers */
165 #define NPCX_DBGCTRL(base) (*(volatile uint8_t *)(base + 0x004))
166 #define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006))
167 #define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007))
168 #define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008))
169 #define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009))
170
171 /* DDI register fields */
172 #define NPCX_DBGCTRL_CCDEV_SEL FIELD(6, 2)
173 #define NPCX_DBGCTRL_CCDEV_DIR 5
174 #define NPCX_DBGCTRL_SEQ_WK_EN 4
175 #define NPCX_DBGCTRL_FRCLK_SEL_DIS 3
176 #define NPCX_DBGFRZEN1_SPIFEN 7
177 #define NPCX_DBGFRZEN1_HIFEN 6
178 #define NPCX_DBGFRZEN1_ESPISEN 5
179 #define NPCX_DBGFRZEN1_UART1FEN 4
180 #define NPCX_DBGFRZEN1_SMB3FEN 3
181 #define NPCX_DBGFRZEN1_SMB2FEN 2
182 #define NPCX_DBGFRZEN1_MFT2FEN 1
183 #define NPCX_DBGFRZEN1_MFT1FEN 0
184 #define NPCX_DBGFRZEN2_ITIM6FEN 7
185 #define NPCX_DBGFRZEN2_ITIM5FEN 6
186 #define NPCX_DBGFRZEN2_ITIM4FEN 5
187 #define NPCX_DBGFRZEN2_ITIM64FEN 3
188 #define NPCX_DBGFRZEN2_SMB1FEN 2
189 #define NPCX_DBGFRZEN2_SMB0FEN 1
190 #define NPCX_DBGFRZEN2_MFT3FEN 0
191 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
192 #define NPCX_DBGFRZEN3_ITIM3FEN 6
193 #define NPCX_DBGFRZEN3_ITIM2FEN 5
194 #define NPCX_DBGFRZEN3_ITIM1FEN 4
195 #define NPCX_DBGFRZEN3_I3CFEN 2
196 #define NPCX_DBGFRZEN3_SMB4FEN 1
197 #define NPCX_DBGFRZEN3_SHMFEN 0
198 #define NPCX_DBGFRZEN4_UART2FEN 6
199 #define NPCX_DBGFRZEN4_UART3FEN 5
200 #define NPCX_DBGFRZEN4_UART4FEN 4
201 #define NPCX_DBGFRZEN4_LCTFEN 3
202 #define NPCX_DBGFRZEN4_SMB7FEN 2
203 #define NPCX_DBGFRZEN4_SMB6FEN 1
204 #define NPCX_DBGFRZEN4_SMB5FEN 0
205
206 /*
207 * System Configuration (SCFG) device registers
208 */
209 struct scfg_reg {
210 /* 0x000: Device Control */
211 volatile uint8_t DEVCNT;
212 /* 0x001: Straps Status */
213 volatile uint8_t STRPST;
214 /* 0x002: Reset Control and Status */
215 volatile uint8_t RSTCTL;
216 volatile uint8_t reserved1[3];
217 /* 0x006: Device Control 4 */
218 volatile uint8_t DEV_CTL4;
219 volatile uint8_t reserved2[9];
220 /* 0x010 - 1F: Device Alternate Function 0 - F */
221 volatile uint8_t DEVALT0[16];
222 volatile uint8_t reserved3[6];
223 /* 0x026: Low-Voltage GPIO Pins Control 5 */
224 volatile uint8_t LV_GPIO_CTL5[1];
225 volatile uint8_t reserved4;
226 /* 0x028: Pull-Up/Pull-Down Enable 0 */
227 volatile uint8_t PUPD_EN0;
228 /* 0x029: Pull-Up/Pull-Down Enable 1 */
229 volatile uint8_t PUPD_EN1;
230 /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
231 volatile uint8_t LV_GPIO_CTL0[5];
232 };
233
234 /* Macro functions for SCFG multi-registers */
235 #define NPCX_DEV_CTL(base, n) \
236 (*(volatile uint8_t *)(base + n))
237 #define NPCX_DEVALT(base, n) \
238 (*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
239 #define NPCX_DEVALT_LK(base, n) \
240 (*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
241 #define NPCX_PUPD_EN(base, n) \
242 (*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
243 #define NPCX_LV_GPIO_CTL(base, n) \
244 (*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
245
246 #define NPCX_JEN_CTL1_OFFSET 0x120
247 #define NPCX_JEN_CTL1(base) (*(volatile uint8_t *)(base + (NPCX_JEN_CTL1_OFFSET)))
248
249 #define NPCX_JEN_CTL1_JEN_EN FIELD(0, 4)
250 #define NPCX_JEN_CTL1_JEN_HEN FIELD(4, 4)
251 #define NPCX_JEN_CTL1_JEN_ENABLE 0x9
252 #define NPCX_JEN_CTL1_JEN_DISABLE 0x6
253
254 /* SCFG register fields */
255 #define NPCX_DEVCNT_F_SPI_TRIS 6
256 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
257 #define NPCX_DEVCNT_JEN1_HEN 5
258 #define NPCX_DEVCNT_JEN0_HEN 4
259 #define NPCX_STRPST_TRIST 1
260 #define NPCX_STRPST_TEST 2
261 #define NPCX_STRPST_JEN1 4
262 #define NPCX_STRPST_JEN0 5
263 #define NPCX_STRPST_SPI_COMP 7
264 #define NPCX_RSTCTL_VCC1_RST_STS 0
265 #define NPCX_RSTCTL_DBGRST_STS 1
266 #define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
267 #define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
268 #define NPCX_RSTCTL_HIPRST_MODE 6
269 #define NPCX_DEV_CTL4_F_SPI_SLLK 2
270 #define NPCX_DEV_CTL4_SPI_SP_SEL 4
271 #define NPCX_DEV_CTL4_WP_IF 5
272 #define NPCX_DEV_CTL4_VCC1_RST_LK 6
273 #define NPCX_DEVPU0_I2C0_0_PUE 0
274 #define NPCX_DEVPU0_I2C0_1_PUE 1
275 #define NPCX_DEVPU0_I2C1_0_PUE 2
276 #define NPCX_DEVPU0_I2C2_0_PUE 4
277 #define NPCX_DEVPU0_I2C3_0_PUE 6
278 #define NPCX_DEVPU1_F_SPI_PUD_EN 7
279
280 /* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
281 enum npcx_hif_type {
282 NPCX_HIF_TYPE_NONE,
283 NPCX_HIF_TYPE_LPC,
284 NPCX_HIF_TYPE_ESPI_SHI,
285 };
286
287 /*
288 * System Glue (GLUE) device registers
289 */
290 struct glue_reg {
291 volatile uint8_t reserved1[2];
292 /* 0x002: SMBus Start Bit Detection */
293 volatile uint8_t SMB_SBD;
294 /* 0x003: SMBus Event Enable */
295 volatile uint8_t SMB_EEN;
296 volatile uint8_t reserved2[12];
297 /* 0x010: Simple Debug Port Data 0 */
298 volatile uint8_t SDPD0;
299 volatile uint8_t reserved3;
300 /* 0x012: Simple Debug Port Data 1 */
301 volatile uint8_t SDPD1;
302 volatile uint8_t reserved4;
303 /* 0x014: Simple Debug Port Control and Status */
304 volatile uint8_t SDP_CTS;
305 volatile uint8_t reserved5[12];
306 /* 0x021: SMBus Bus Select */
307 volatile uint8_t SMB_SEL;
308 volatile uint8_t reserved6[5];
309 /* 0x027: PSL Control and Status */
310 volatile uint8_t PSL_CTS;
311 };
312
313 /* GLUE register fields */
314 /* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
315 #define NPCX_PSL_CTS_MODE_BIT(bit) BIT(bit + 4)
316 /* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
317 #define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
318
319 /*
320 * Universal Asynchronous Receiver-Transmitter (UART) device registers
321 */
322 struct uart_reg {
323 /* 0x000: Transmit Data Buffer */
324 volatile uint8_t UTBUF;
325 volatile uint8_t reserved1;
326 /* 0x002: Receive Data Buffer */
327 volatile uint8_t URBUF;
328 volatile uint8_t reserved2;
329 /* 0x004: Interrupt Control */
330 volatile uint8_t UICTRL;
331 volatile uint8_t reserved3;
332 /* 0x006: Status */
333 volatile uint8_t USTAT;
334 volatile uint8_t reserved4;
335 /* 0x008: Frame Select */
336 volatile uint8_t UFRS;
337 volatile uint8_t reserved5;
338 /* 0x00A: Mode Select */
339 volatile uint8_t UMDSL;
340 volatile uint8_t reserved6;
341 /* 0x00C: Baud Rate Divisor */
342 volatile uint8_t UBAUD;
343 volatile uint8_t reserved7;
344 /* 0x00E: Baud Rate Prescaler */
345 volatile uint8_t UPSR;
346 volatile uint8_t reserved8[17];
347 /* 0x020: FIFO Mode Transmit Status */
348 volatile uint8_t UFTSTS;
349 volatile uint8_t reserved9;
350 /* 0x022: FIFO Mode Receive Status */
351 volatile uint8_t UFRSTS;
352 volatile uint8_t reserved10;
353 /* 0x024: FIFO Mode Transmit Control */
354 volatile uint8_t UFTCTL;
355 volatile uint8_t reserved11;
356 /* 0x026: FIFO Mode Receive Control */
357 volatile uint8_t UFRCTL;
358 };
359
360 /* UART register fields */
361 #define NPCX_UICTRL_TBE 0
362 #define NPCX_UICTRL_RBF 1
363 #define NPCX_UICTRL_ETI 5
364 #define NPCX_UICTRL_ERI 6
365 #define NPCX_UICTRL_EEI 7
366 #define NPCX_USTAT_PE 0
367 #define NPCX_USTAT_FE 1
368 #define NPCX_USTAT_DOE 2
369 #define NPCX_USTAT_ERR 3
370 #define NPCX_USTAT_BKD 4
371 #define NPCX_USTAT_RB9 5
372 #define NPCX_USTAT_XMIP 6
373 #define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
374 #define NPCX_UFRS_STP 2
375 #define NPCX_UFRS_XB9 3
376 #define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
377 #define NPCX_UFRS_PEN 6
378 #define NPCX_UMDSL_FIFO_MD 0
379 #define NPCX_UMDSL_ETD 4
380 #define NPCX_UMDSL_ERD 5
381
382 #define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
383 #define NPCX_UFTSTS_TEMPTY_LVL_STS 5
384 #define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
385 #define NPCX_UFTSTS_NXMIP 7
386 #define NPCX_UFRSTS_RFULL_LVL_STS 5
387 #define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
388 #define NPCX_UFRSTS_ERR 7
389 #define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
390 #define NPCX_UFTCTL_TEMPTY_LVL_EN 5
391 #define NPCX_UFTCTL_TEMPTY_EN 6
392 #define NPCX_UFTCTL_NXMIP_EN 7
393 #define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
394 #define NPCX_UFRCTL_RFULL_LVL_EN 5
395 #define NPCX_UFRCTL_RNEMPTY_EN 6
396 #define NPCX_UFRCTL_ERR_EN 7
397
398 /* Macro functions for MIWU multi-registers */
399 #define NPCX_WKEDG(base, group) \
400 (*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
401 #define NPCX_WKAEDG(base, group) \
402 (*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
403 #define NPCX_WKPND(base, group) \
404 (*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
405 #define NPCX_WKPCL(base, group) \
406 (*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
407 #define NPCX_WKEN(base, group) \
408 (*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
409 #define NPCX_WKINEN(base, group) \
410 (*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
411 #define NPCX_WKMOD(base, group) \
412 (*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
413 #define NPCX_WKST(base, group) \
414 (*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group)))
415
416 /*
417 * General-Purpose I/O (GPIO) device registers
418 */
419 struct gpio_reg {
420 /* 0x000: Port GPIOx Data Out */
421 volatile uint8_t PDOUT;
422 /* 0x001: Port GPIOx Data In */
423 volatile uint8_t PDIN;
424 /* 0x002: Port GPIOx Direction */
425 volatile uint8_t PDIR;
426 /* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
427 volatile uint8_t PPULL;
428 /* 0x004: Port GPIOx Pull-Up/Down Selection */
429 volatile uint8_t PPUD;
430 /* 0x005: Port GPIOx Drive Enable by VDD Present */
431 volatile uint8_t PENVDD;
432 /* 0x006: Port GPIOx Output Type */
433 volatile uint8_t PTYPE;
434 /* 0x007: Port GPIOx Lock Control */
435 volatile uint8_t PLOCK_CTL;
436 };
437
438 /*
439 * Pulse Width Modulator (PWM) device registers
440 */
441 struct pwm_reg {
442 /* 0x000: Clock Prescaler */
443 volatile uint16_t PRSC;
444 /* 0x002: Cycle Time */
445 volatile uint16_t CTR;
446 /* 0x004: PWM Control */
447 volatile uint8_t PWMCTL;
448 volatile uint8_t reserved1;
449 /* 0x006: Duty Cycle */
450 volatile uint16_t DCR;
451 volatile uint8_t reserved2[4];
452 /* 0x00C: PWM Control Extended */
453 volatile uint8_t PWMCTLEX;
454 volatile uint8_t reserved3;
455 };
456
457 /* PWM register fields */
458 #define NPCX_PWMCTL_INVP 0
459 #define NPCX_PWMCTL_CKSEL 1
460 #define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
461 #define NPCX_PWMCTL_PWR 7
462 #define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
463 #define NPCX_PWMCTLEX_OD_OUT 7
464
465 /*
466 * Analog-To-Digital Converter (ADC) device registers
467 */
468 struct adc_reg {
469 /* 0x000: ADC Status */
470 volatile uint16_t ADCSTS;
471 /* 0x002: ADC Configuration */
472 volatile uint16_t ADCCNF;
473 /* 0x004: ADC Timing Control */
474 volatile uint16_t ATCTL;
475 /* 0x006: ADC Single Channel Address */
476 volatile uint16_t ASCADD;
477 /* 0x008: ADC Scan Channels Select */
478 volatile uint16_t ADCCS;
479 /* 0x00A: ADC Scan Channels Select 2 */
480 volatile uint16_t ADCCS2;
481 volatile uint8_t reserved1[14];
482 /* 0x01A: Threshold Status */
483 volatile uint16_t THRCTS;
484 volatile uint8_t reserved2[4];
485 /* 0x020: Internal register 1 for ADC Speed */
486 volatile uint16_t ADCCNF2;
487 /* 0x022: Internal register 2 for ADC Speed */
488 volatile uint16_t GENDLY;
489 volatile uint8_t reserved3[2];
490 /* 0x026: Internal register 3 for ADC Speed */
491 volatile uint16_t MEAST;
492 };
493
494 /* ADC internal inline functions for multi-registers */
495 #define CHNDAT(base, ch) \
496 (*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
497 #define THRCTL(base, ctrl) \
498 (*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
499
500 /* ADC register fields */
501 #define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
502 #define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
503 #define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
504 #define NPCX_ADCSTS_EOCEV 0
505 #define NPCX_ADCSTS_EOCCEV 1
506 #define NPCX_ADCCNF_ADCEN 0
507 #define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
508 #define NPCX_ADCCNF_ADCRPTC 3
509 #define NPCX_ADCCNF_START 4
510 #define NPCX_ADCCNF_ADCTTE 5
511 #define NPCX_ADCCNF_INTECEN 6
512 #define NPCX_ADCCNF_INTECCEN 7
513 #define NPCX_ADCCNF_INTETCEN 8
514 #define NPCX_ADCCNF_INTOVFEN 9
515 #define NPCX_ADCCNF_STOP 11
516 #define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
517 #define NPCX_CHNDAT_NEW 15
518 #define NPCX_THRCTS_ADC_WKEN 15
519 #define NPCX_THRCTS_THR3_IEN 10
520 #define NPCX_THRCTS_THR2_IEN 9
521 #define NPCX_THRCTS_THR1_IEN 8
522 #define NPCX_THRCTS_ADC_EVENT 7
523 #define NPCX_THRCTS_THR3_STS 2
524 #define NPCX_THRCTS_THR2_STS 1
525 #define NPCX_THRCTS_THR1_STS 0
526 #define NPCX_THR_DCTL_THRD_EN 15
527 #define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
528
529 /*
530 * Timer Watchdog (TWD) device registers
531 */
532 struct twd_reg {
533 /* 0x000: Timer and Watchdog Configuration */
534 volatile uint8_t TWCFG;
535 volatile uint8_t reserved1;
536 /* 0x002: Timer and Watchdog Clock Prescaler */
537 volatile uint8_t TWCP;
538 volatile uint8_t reserved2;
539 /* 0x004: TWD Timer 0 */
540 volatile uint16_t TWDT0;
541 /* 0x006: TWDT0 Control and Status */
542 volatile uint8_t T0CSR;
543 volatile uint8_t reserved3;
544 /* 0x008: Watchdog Count */
545 volatile uint8_t WDCNT;
546 volatile uint8_t reserved4;
547 /* 0x00A: Watchdog Service Data Match */
548 volatile uint8_t WDSDM;
549 volatile uint8_t reserved5;
550 /* 0x00C: TWD Timer 0 Counter */
551 volatile uint16_t TWMT0;
552 /* 0x00E: Watchdog Counter */
553 volatile uint8_t TWMWD;
554 volatile uint8_t reserved6;
555 /* 0x010: Watchdog Clock Prescaler */
556 volatile uint8_t WDCP;
557 volatile uint8_t reserved7;
558 };
559
560 /* TWD register fields */
561 #define NPCX_TWCFG_LTWCFG 0
562 #define NPCX_TWCFG_LTWCP 1
563 #define NPCX_TWCFG_LTWDT0 2
564 #define NPCX_TWCFG_LWDCNT 3
565 #define NPCX_TWCFG_WDCT0I 4
566 #define NPCX_TWCFG_WDSDME 5
567 #define NPCX_T0CSR_RST 0
568 #define NPCX_T0CSR_TC 1
569 #define NPCX_T0CSR_WDLTD 3
570 #define NPCX_T0CSR_WDRST_STS 4
571 #define NPCX_T0CSR_WD_RUN 5
572 #define NPCX_T0CSR_TESDIS 7
573
574 /*
575 * Enhanced Serial Peripheral Interface (eSPI) device registers
576 */
577 struct espi_reg {
578 /* 0x000: eSPI Identification */
579 volatile uint32_t ESPIID;
580 /* 0x004: eSPI Configuration */
581 volatile uint32_t ESPICFG;
582 /* 0x008: eSPI Status */
583 volatile uint32_t ESPISTS;
584 /* 0x00C: eSPI Interrupt Enable */
585 volatile uint32_t ESPIIE;
586 /* 0x010: eSPI Wake-Up Enable */
587 volatile uint32_t ESPIWE;
588 /* 0x014: Virtual Wire Register Index */
589 volatile uint32_t VWREGIDX;
590 /* 0x018: Virtual Wire Register Data */
591 volatile uint32_t VWREGDATA;
592 /* 0x01C: OOB Receive Buffer Read Head */
593 volatile uint32_t OOBRXRDHEAD;
594 /* 0x020: OOB Transmit Buffer Write Head */
595 volatile uint32_t OOBTXWRHEAD;
596 /* 0x024: OOB Channel Control */
597 volatile uint32_t OOBCTL;
598 /* 0x028: Flash Receive Buffer Read Head */
599 volatile uint32_t FLASHRXRDHEAD;
600 /* 0x02C: Flash Transmit Buffer Write Head */
601 volatile uint32_t FLASHTXWRHEAD;
602 volatile uint32_t reserved1;
603 /* 0x034: Flash Channel Configuration */
604 volatile uint32_t FLASHCFG;
605 /* 0x038: Flash Channel Control */
606 volatile uint32_t FLASHCTL;
607 /* 0x03C: eSPI Error Status */
608 volatile uint32_t ESPIERR;
609 /* 0x040: Peripheral Bus Master Receive Buffer Read Head */
610 volatile uint32_t PBMRXRDHEAD;
611 /* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
612 volatile uint32_t PBMTXWRHEAD;
613 /* 0x048: Peripheral Channel Configuration */
614 volatile uint32_t PERCFG;
615 /* 0x04C: Peripheral Channel Control */
616 volatile uint32_t PERCTL;
617 /* 0x050: Status Image Register */
618 volatile uint16_t STATUS_IMG;
619 volatile uint16_t reserved2[79];
620 /* 0x0F0: NPCX specific eSPI Register1 */
621 volatile uint8_t NPCX_ONLY_ESPI_REG1;
622 /* 0x0F1: NPCX specific eSPI Register2 */
623 volatile uint8_t NPCX_ONLY_ESPI_REG2;
624 volatile uint16_t reserved3[7];
625 /* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
626 volatile uint32_t VWEVSM[10];
627 volatile uint32_t reserved4[6];
628 /* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
629 volatile uint32_t VWEVMS[12];
630 volatile uint32_t reserved5[4];
631 /* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
632 volatile uint32_t VWGPSM[16];
633 volatile uint32_t reserved6[79];
634 /* 0x2FC: Virtual Wire Channel Control */
635 volatile uint32_t VWCTL;
636 /* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
637 volatile uint32_t OOBRXBUF[20];
638 volatile uint32_t reserved7[12];
639 /* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
640 volatile uint32_t OOBTXBUF[20];
641 volatile uint32_t reserved8[11];
642 /* 0x3FC: OOB Channel Control used in 'direct' mode */
643 volatile uint32_t OOBCTL_DIRECT;
644 /* 0x400 - 443: Flash Receive Buffer 0-17 */
645 volatile uint32_t FLASHRXBUF[18];
646 volatile uint32_t reserved9[14];
647 /* 0x480 - 497: Flash Transmit Buffer 0-16 */
648 volatile uint32_t FLASHTXBUF[17];
649 volatile uint32_t reserved10[14];
650 /* 0x4FC: Flash Channel Control used in 'direct' mode */
651 volatile uint32_t FLASHCTL_DIRECT;
652 volatile uint32_t reserved12[64];
653 /* 0x600 - 63F */
654 volatile uint32_t FLASH_PRTR_BADDR[16];
655 /* 0x640 - 67F */
656 volatile uint32_t FLASH_PRTR_HADDR[16];
657 /* 0x680 - 6BF */
658 volatile uint32_t FLASH_RGN_TAG_OVR[16];
659 volatile uint32_t reserved13[80];
660 /* 0x800 */
661 volatile uint32_t FLASH_RPMC_CFG_1;
662 /* 0x804 */
663 volatile uint32_t FLASH_RPMC_CFG_2;
664 /* 0x808 */
665 volatile uint32_t RMAP_FLASH_OFFS;
666 /* 0x80C */
667 volatile uint32_t RMAP_DST_BASE;
668 /* 0x810 */
669 volatile uint32_t RMAP_WIN_SIZE;
670 /* 0x814 */
671 volatile uint32_t FLASHBASE;
672 volatile uint32_t reserved14[58];
673 };
674
675 /* eSPI register fields */
676 #define NPCX_ESPICFG_PCHANEN 0
677 #define NPCX_ESPICFG_VWCHANEN 1
678 #define NPCX_ESPICFG_OOBCHANEN 2
679 #define NPCX_ESPICFG_FLASHCHANEN 3
680 #define NPCX_ESPICFG_HPCHANEN 4
681 #define NPCX_ESPICFG_HVWCHANEN 5
682 #define NPCX_ESPICFG_HOOBCHANEN 6
683 #define NPCX_ESPICFG_HFLASHCHANEN 7
684 #define NPCX_ESPICFG_CHANS_FIELD FIELD(0, 4)
685 #define NPCX_ESPICFG_HCHANS_FIELD FIELD(4, 4)
686 #define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
687 #define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
688 #define NPCX_ESPICFG_FLCHANMODE 16
689 #define NPCX_ESPICFG_PCCHN_SUPP 24
690 #define NPCX_ESPICFG_VWCHN_SUPP 25
691 #define NPCX_ESPICFG_OOBCHN_SUPP 26
692 #define NPCX_ESPICFG_FLASHCHN_SUPP 27
693 #define NPCX_ESPIIE_IBRSTIE 0
694 #define NPCX_ESPIIE_CFGUPDIE 1
695 #define NPCX_ESPIIE_BERRIE 2
696 #define NPCX_ESPIIE_OOBRXIE 3
697 #define NPCX_ESPIIE_FLASHRXIE 4
698 #define NPCX_ESPIIE_FLNACSIE 5
699 #define NPCX_ESPIIE_PERACCIE 6
700 #define NPCX_ESPIIE_DFRDIE 7
701 #define NPCX_ESPIIE_VWUPDIE 8
702 #define NPCX_ESPIIE_ESPIRSTIE 9
703 #define NPCX_ESPIIE_PLTRSTIE 10
704 #define NPCX_ESPIIE_AMERRIE 15
705 #define NPCX_ESPIIE_AMDONEIE 16
706 #define NPCX_ESPIIE_BMTXDONEIE 19
707 #define NPCX_ESPIIE_PBMRXIE 20
708 #define NPCX_ESPIIE_PMSGRXIE 21
709 #define NPCX_ESPIIE_BMBURSTERRIE 22
710 #define NPCX_ESPIIE_BMBURSTDONEIE 23
711 #define NPCX_ESPIWE_IBRSTWE 0
712 #define NPCX_ESPIWE_CFGUPDWE 1
713 #define NPCX_ESPIWE_BERRWE 2
714 #define NPCX_ESPIWE_OOBRXWE 3
715 #define NPCX_ESPIWE_FLASHRXWE 4
716 #define NPCX_ESPIWE_FLNACSWE 5
717 #define NPCX_ESPIWE_PERACCWE 6
718 #define NPCX_ESPIWE_DFRDWE 7
719 #define NPCX_ESPIWE_VWUPDWE 8
720 #define NPCX_ESPIWE_ESPIRSTWE 9
721 #define NPCX_ESPIWE_PBMRXWE 20
722 #define NPCX_ESPIWE_PMSGRXWE 21
723 #define NPCX_ESPISTS_IBRST 0
724 #define NPCX_ESPISTS_CFGUPD 1
725 #define NPCX_ESPISTS_BERR 2
726 #define NPCX_ESPISTS_OOBRX 3
727 #define NPCX_ESPISTS_FLASHRX 4
728 #define NPCX_ESPISTS_FLNACS 5
729 #define NPCX_ESPISTS_PERACC 6
730 #define NPCX_ESPISTS_DFRD 7
731 #define NPCX_ESPISTS_VWUPD 8
732 #define NPCX_ESPISTS_ESPIRST 9
733 #define NPCX_ESPISTS_PLTRST 10
734 #define NPCX_ESPISTS_AMERR 15
735 #define NPCX_ESPISTS_AMDONE 16
736 #define NPCX_ESPISTS_VWUPDW 17
737 #define NPCX_ESPISTS_BMTXDONE 19
738 #define NPCX_ESPISTS_PBMRX 20
739 #define NPCX_ESPISTS_PMSGRX 21
740 #define NPCX_ESPISTS_BMBURSTERR 22
741 #define NPCX_ESPISTS_BMBURSTDONE 23
742 #define NPCX_ESPISTS_ESPIRST_LVL 24
743 #define NPCX_VWSWIRQ_IRQ_NUM FIELD(0, 7)
744 #define NPCX_VWSWIRQ_IRQ_LVL 7
745 #define NPCX_VWSWIRQ_INDEX FIELD(8, 7)
746 #define NPCX_VWSWIRQ_INDEX_EN 15
747 #define NPCX_VWSWIRQ_DIRTY 16
748 #define NPCX_VWSWIRQ_ENPLTRST 17
749 #define NPCX_VWSWIRQ_ENCDRST 19
750 #define NPCX_VWSWIRQ_EDGE_IRQ 28
751 #define NPCX_VWEVMS_WIRE FIELD(0, 4)
752 #define NPCX_VWEVMS_VALID FIELD(4, 4)
753 #define NPCX_VWEVMS_IE 18
754 #define NPCX_VWEVMS_WE 20
755 #define NPCX_VWEVSM_WIRE FIELD(0, 4)
756 #define NPCX_VWEVSM_VALID FIELD(4, 4)
757 #define NPCX_VWEVSM_BIT_VALID(n) (4+n)
758 #define NPCX_VWEVSM_HW_WIRE FIELD(24, 4)
759 #define NPCX_VWGPSM_INDEX_EN 15
760 #define NPCX_OOBCTL_OOB_FREE 0
761 #define NPCX_OOBCTL_OOB_AVAIL 1
762 #define NPCX_OOBCTL_RSTBUFHEADS 2
763 #define NPCX_OOBCTL_OOBPLSIZE FIELD(10, 3)
764 #define NPCX_FLASHCFG_FLASHBLERSSIZE FIELD(7, 3)
765 #define NPCX_FLASHCFG_FLASHPLSIZE FIELD(10, 3)
766 #define NPCX_FLASHCFG_FLASHREQSIZE FIELD(13, 3)
767 #define NPCX_FLASHCFG_FLCAPA FIELD(24, 2)
768 #define NPCX_FLASHCFG_TRGFLEBLKSIZE FIELD(16, 8)
769 #define NPCX_FLASHCFG_FLREQSUP FIELD(0, 3)
770 #define NPCX_FLASHCTL_FLASH_NP_FREE 0
771 #define NPCX_FLASHCTL_FLASH_TX_AVAIL 1
772 #define NPCX_FLASHCTL_STRPHDR 2
773 #define NPCX_FLASHCTL_DMATHRESH FIELD(3, 2)
774 #define NPCX_FLASHCTL_AMTSIZE FIELD(5, 8)
775 #define NPCX_FLASHCTL_RSTBUFHEADS 13
776 #define NPCX_FLASHCTL_CRCEN 14
777 #define NPCX_FLASHCTL_CHKSUMSEL 15
778 #define NPCX_FLASHCTL_AMTEN 16
779 #define NPCX_FLASHCTL_SAF_AUTO_READ 18
780 #define NPCX_FLASHCTL_AUTO_RD_DIS_CTL 19
781 #define NPCX_FLASHCTL_BLK_FLASH_NP_FREE 20
782 #define NPCX_FLASHBASE_FLBASE_ADDR FIELD(12, 15)
783 #define NPCX_FLASH_PRTR_BADDR FIELD(12, 15)
784 #define NPCX_FRGN_WPR 29
785 #define SAF_PROT_LCK 31
786 #define NPCX_FRGN_RPR 30
787 #define NPCX_FLASH_PRTR_HADDR FIELD(12, 15)
788 #define NPCX_FLASH_TAG_OVR_RPR FIELD(16, 16)
789 #define NPCX_FLASH_TAG_OVR_WPR FIELD(0, 16)
790 #define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
791 #define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
792 #define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
793
794 /*
795 * Mobile System Wake-Up Control (MSWC) device registers
796 */
797 struct mswc_reg {
798 /* 0x000: MSWC Control Status 1 */
799 volatile uint8_t MSWCTL1;
800 volatile uint8_t reserved1;
801 /* 0x002: MSWC Control Status 2 */
802 volatile uint8_t MSWCTL2;
803 volatile uint8_t reserved2[5];
804 /* 0x008: Host Configuration Base Address Low */
805 volatile uint8_t HCBAL;
806 volatile uint8_t reserved3;
807 /* 0x00A: Host Configuration Base Address High */
808 volatile uint8_t HCBAH;
809 volatile uint8_t reserved4;
810 /* 0X00C: MSWC INTERRUPT ENABLE 2 */
811 volatile uint8_t MSIEN2;
812 volatile uint8_t reserved5;
813 /* 0x00E: MSWC Host Event Status 0 */
814 volatile uint8_t MSHES0;
815 volatile uint8_t reserved6;
816 /* 0x010: MSWC Host Event Interrupt Enable */
817 volatile uint8_t MSHEIE0;
818 volatile uint8_t reserved7;
819 /* 0x012: Host Control */
820 volatile uint8_t HOST_CTL;
821 volatile uint8_t reserved8;
822 /* 0x014: SMI Pulse Length */
823 volatile uint8_t SMIP_LEN;
824 volatile uint8_t reserved9;
825 /* 0x016: SCI Pulse Length */
826 volatile uint8_t SCIP_LEN;
827 volatile uint8_t reserved10[5];
828 /* 0x01C: SRID Core Access */
829 volatile uint8_t SRID_CR;
830 volatile uint8_t reserved11[3];
831 /* 0x020: SID Core Access */
832 volatile uint8_t SID_CR;
833 volatile uint8_t reserved12;
834 /* 0x022: DEVICE_ID Core Access */
835 volatile uint8_t DEVICE_ID_CR;
836 volatile uint8_t reserved13[5];
837 /* 0x028: Chip Revision Core Access */
838 volatile uint8_t CHPREV_CR;
839 volatile uint8_t reserved14[5];
840 /* 0x02E: Virtual Wire Sleep States */
841 volatile uint8_t VW_SLPST1;
842 volatile uint8_t reserved15;
843 };
844
845 /* MSWC register fields */
846 #define NPCX_MSWCTL1_HRSTOB 0
847 #define NPCS_MSWCTL1_HWPRON 1
848 #define NPCX_MSWCTL1_PLTRST_ACT 2
849 #define NPCX_MSWCTL1_VHCFGA 3
850 #define NPCX_MSWCTL1_HCFGLK 4
851 #define NPCX_MSWCTL1_PWROFFB 6
852 #define NPCX_MSWCTL1_A20MB 7
853
854 /*
855 * Shared Memory (SHM) device registers
856 */
857 struct shm_reg {
858 /* 0x000: Shared Memory Core Status */
859 volatile uint8_t SMC_STS;
860 /* 0x001: Shared Memory Core Control */
861 volatile uint8_t SMC_CTL;
862 /* 0x002: Shared Memory Host Control */
863 volatile uint8_t SHM_CTL;
864 volatile uint8_t reserved1[2];
865 /* 0x005: Indirect Memory Access Window Size */
866 volatile uint8_t IMA_WIN_SIZE;
867 volatile uint8_t reserved2;
868 /* 0x007: Shared Access Windows Size */
869 volatile uint8_t WIN_SIZE;
870 /* 0x008: Shared Access Window 1, Semaphore */
871 volatile uint8_t SHAW1_SEM;
872 /* 0x009: Shared Access Window 2, Semaphore */
873 volatile uint8_t SHAW2_SEM;
874 volatile uint8_t reserved3;
875 /* 0x00B: Indirect Memory Access, Semaphore */
876 volatile uint8_t IMA_SEM;
877 volatile uint8_t reserved4[2];
878 /* 0x00E: Shared Memory Configuration */
879 volatile uint16_t SHCFG;
880 /* 0x010: Shared Access Window 1 Write Protect */
881 volatile uint8_t WIN1_WR_PROT;
882 /* 0x011: Shared Access Window 1 Read Protect */
883 volatile uint8_t WIN1_RD_PROT;
884 /* 0x012: Shared Access Window 2 Write Protect */
885 volatile uint8_t WIN2_WR_PROT;
886 /* 0x013: Shared Access Window 2 Read Protect */
887 volatile uint8_t WIN2_RD_PROT;
888 volatile uint8_t reserved5[2];
889 /* 0x016: Indirect Memory Access Write Protect */
890 volatile uint8_t IMA_WR_PROT;
891 /* 0x017: Indirect Memory Access Read Protect */
892 volatile uint8_t IMA_RD_PROT;
893 volatile uint8_t reserved6[8];
894 /* 0x020: Shared Access Window 1 Base */
895 volatile uint32_t WIN_BASE1;
896 /* 0x024: Shared Access Window 2 Base */
897 volatile uint32_t WIN_BASE2;
898 volatile uint32_t reserved7;
899 /* 0x02C: Indirect Memory Access Base */
900 volatile uint32_t IMA_BASE;
901 volatile uint8_t reserved8[10];
902 /* 0x03A: Reset Configuration */
903 volatile uint8_t RST_CFG;
904 volatile uint8_t reserved9[5];
905 /* 0x040: Debug Port 80 Buffered Data */
906 volatile uint16_t DP80BUF;
907 /* 0x042: Debug Port 80 Status */
908 volatile uint8_t DP80STS;
909 volatile uint8_t reserved10;
910 /* 0x044: Debug Port 80 Control */
911 volatile uint8_t DP80CTL;
912 volatile uint8_t reserved11[3];
913 /* 0x048: Host_Offset in Windows 1, 2 Status */
914 volatile uint8_t HOFS_STS;
915 /* 0x049: Host_Offset in Windows 1, 2 Control */
916 volatile uint8_t HOFS_CTL;
917 /* 0x04A: Core_Offset in Window 2 Address */
918 volatile uint16_t COFS2;
919 /* 0x04C: Core_Offset in Window 1 Address */
920 volatile uint16_t COFS1;
921 volatile uint16_t reserved12;
922 };
923
924 /* SHM register fields */
925 #define NPCX_SMC_STS_HRERR 0
926 #define NPCX_SMC_STS_HWERR 1
927 #define NPCX_SMC_STS_HSEM1W 4
928 #define NPCX_SMC_STS_HSEM2W 5
929 #define NPCX_SMC_STS_SHM_ACC 6
930 #define NPCX_SMC_CTL_HERR_IE 2
931 #define NPCX_SMC_CTL_HSEM1_IE 3
932 #define NPCX_SMC_CTL_HSEM2_IE 4
933 #define NPCX_SMC_CTL_ACC_IE 5
934 #define NPCX_SMC_CTL_PREF_EN 6
935 #define NPCX_SMC_CTL_HOSTWAIT 7
936 #define NPCX_FLASH_SIZE_STALL_HOST 6
937 #define NPCX_FLASH_SIZE_RD_BURST 7
938 #define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD FIELD(0, 4)
939 #define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD FIELD(4, 4)
940 #define NPCX_WIN_PROT_RW1L_RP 0
941 #define NPCX_WIN_PROT_RW1L_WP 1
942 #define NPCX_WIN_PROT_RW1H_RP 2
943 #define NPCX_WIN_PROT_RW1H_WP 3
944 #define NPCX_WIN_PROT_RW2L_RP 4
945 #define NPCX_WIN_PROT_RW2L_WP 5
946 #define NPCX_WIN_PROT_RW2H_RP 6
947 #define NPCX_WIN_PROT_RW2H_WP 7
948 #define NPCX_PWIN_SIZEI_RPROT 13
949 #define NPCX_PWIN_SIZEI_WPROT 14
950 #define NPCX_CSEM2 6
951 #define NPCX_CSEM3 7
952 #define NPCX_DP80STS_FWR 5
953 #define NPCX_DP80STS_FNE 6
954 #define NPCX_DP80STS_FOR 7
955 #define NPCX_DP80CTL_DP80EN 0
956 #define NPCX_DP80CTL_SYNCEN 1
957 #define NPCX_DP80CTL_ADV 2
958 #define NPCX_DP80CTL_RAA 3
959 #define NPCX_DP80CTL_RFIFO 4
960 #define NPCX_DP80CTL_CIEN 5
961 #define NPCX_DP80CTL_DP80_HF_CFG 7
962 #define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
963
964 /*
965 * Keyboard and Mouse Controller (KBC) device registers
966 */
967 struct kbc_reg {
968 /* 0x000h: Host Interface Control */
969 volatile uint8_t HICTRL;
970 volatile uint8_t reserved1;
971 /* 0x002h: Host Interface IRQ Control */
972 volatile uint8_t HIIRQC;
973 volatile uint8_t reserved2;
974 /* 0x004h: Host Interface Keyboard/Mouse Status */
975 volatile uint8_t HIKMST;
976 volatile uint8_t reserved3;
977 /* 0x006h: Host Interface Keyboard Data Out Buffer */
978 volatile uint8_t HIKDO;
979 volatile uint8_t reserved4;
980 /* 0x008h: Host Interface Mouse Data Out Buffer */
981 volatile uint8_t HIMDO;
982 volatile uint8_t reserved5;
983 /* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
984 volatile uint8_t HIKMDI;
985 /* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
986 volatile uint8_t SHIKMDI;
987 };
988
989 /* KBC register field */
990 #define NPCX_HICTRL_OBFKIE 0
991 #define NPCX_HICTRL_OBFMIE 1
992 #define NPCX_HICTRL_OBECIE 2
993 #define NPCX_HICTRL_IBFCIE 3
994 #define NPCX_HICTRL_PMIHIE 4
995 #define NPCX_HICTRL_PMIOCIE 5
996 #define NPCX_HICTRL_PMICIE 6
997 #define NPCX_HICTRL_FW_OBF 7
998 #define NPCX_HIKMST_OBF 0
999 #define NPCX_HIKMST_IBF 1
1000 #define NPCX_HIKMST_F0 2
1001 #define NPCX_HIKMST_A2 3
1002 #define NPCX_HIKMST_ST0 4
1003 #define NPCX_HIKMST_ST1 5
1004 #define NPCX_HIKMST_ST2 6
1005 #define NPCX_HIKMST_ST3 7
1006
1007 /*
1008 * Power Management Channel (PMCH) device registers
1009 */
1010
1011 struct pmch_reg {
1012 /* 0x000: Host Interface PM Status */
1013 volatile uint8_t HIPMST;
1014 volatile uint8_t reserved1;
1015 /* 0x002: Host Interface PM Data Out Buffer */
1016 volatile uint8_t HIPMDO;
1017 volatile uint8_t reserved2;
1018 /* 0x004: Host Interface PM Data In Buffer */
1019 volatile uint8_t HIPMDI;
1020 /* 0x005: Host Interface PM Shadow Data In Buffer */
1021 volatile uint8_t SHIPMDI;
1022 /* 0x006: Host Interface PM Data Out Buffer with SCI */
1023 volatile uint8_t HIPMDOC;
1024 volatile uint8_t reserved3;
1025 /* 0x008: Host Interface PM Data Out Buffer with SMI */
1026 volatile uint8_t HIPMDOM;
1027 volatile uint8_t reserved4;
1028 /* 0x00A: Host Interface PM Data In Buffer with SCI */
1029 volatile uint8_t HIPMDIC;
1030 volatile uint8_t reserved5;
1031 /* 0x00C: Host Interface PM Control */
1032 volatile uint8_t HIPMCTL;
1033 /* 0x00D: Host Interface PM Control 2 */
1034 volatile uint8_t HIPMCTL2;
1035 /* 0x00E: Host Interface PM Interrupt Control */
1036 volatile uint8_t HIPMIC;
1037 volatile uint8_t reserved6;
1038 /* 0x010: Host Interface PM Interrupt Enable */
1039 volatile uint8_t HIPMIE;
1040 volatile uint8_t reserved7;
1041 };
1042
1043 /* PMCH register field */
1044 #define NPCX_HIPMIE_SCIE 1
1045 #define NPCX_HIPMIE_SMIE 2
1046 #define NPCX_HIPMCTL_IBFIE 0
1047 #define NPCX_HIPMCTL_OBEIE 1
1048 #define NPCX_HIPMCTL_SCIPOL 6
1049 #define NPCX_HIPMST_OBF 0
1050 #define NPCX_HIPMST_IBF 1
1051 #define NPCX_HIPMST_F0 2
1052 #define NPCX_HIPMST_CMD 3
1053 #define NPCX_HIPMST_ST0 4
1054 #define NPCX_HIPMST_ST1 5
1055 #define NPCX_HIPMST_ST2 6
1056 #define NPCX_HIPMIC_SMIB 1
1057 #define NPCX_HIPMIC_SCIB 2
1058 #define NPCX_HIPMIC_SMIPOL 6
1059
1060 /*
1061 * Core Access to Host (C2H) device registers
1062 */
1063 struct c2h_reg {
1064 /* 0x000: Indirect Host I/O Address */
1065 volatile uint16_t IHIOA;
1066 /* 0x002: Indirect Host Data */
1067 volatile uint8_t IHD;
1068 volatile uint8_t reserved1;
1069 /* 0x004: Lock Host Access */
1070 volatile uint16_t LKSIOHA;
1071 /* 0x006: Access Lock Violation */
1072 volatile uint16_t SIOLV;
1073 /* 0x008: Core-to-Host Modules Access Enable */
1074 volatile uint16_t CRSMAE;
1075 /* 0x00A: Module Control */
1076 volatile uint8_t SIBCTRL;
1077 volatile uint8_t reserved3;
1078 };
1079
1080 /* C2H register fields */
1081 #define NPCX_LKSIOHA_LKCFG 0
1082 #define NPCX_LKSIOHA_LKSPHA 2
1083 #define NPCX_LKSIOHA_LKHIKBD 11
1084 #define NPCX_CRSMAE_CFGAE 0
1085 #define NPCX_CRSMAE_HIKBDAE 11
1086 #define NPCX_SIOLV_SPLV 2
1087 #define NPCX_SIBCTRL_CSAE 0
1088 #define NPCX_SIBCTRL_CSRD 1
1089 #define NPCX_SIBCTRL_CSWR 2
1090
1091 /*
1092 * SMBUS (SMB) device registers
1093 */
1094 struct smb_reg {
1095 /* 0x000: SMB Serial Data */
1096 volatile uint8_t SMBSDA;
1097 volatile uint8_t reserved1;
1098 /* 0x002: SMB Status */
1099 volatile uint8_t SMBST;
1100 volatile uint8_t reserved2;
1101 /* 0x004: SMB Control Status */
1102 volatile uint8_t SMBCST;
1103 volatile uint8_t reserved3;
1104 /* 0x006: SMB Control 1 */
1105 volatile uint8_t SMBCTL1;
1106 volatile uint8_t reserved4;
1107 /* 0x008: SMB Own Address */
1108 volatile uint8_t SMBADDR1;
1109 volatile uint8_t reserved5;
1110 /* 0x00A: SMB Control 2 */
1111 volatile uint8_t SMBCTL2;
1112 volatile uint8_t reserved6;
1113 /* 0x00C: SMB Own Address */
1114 volatile uint8_t SMBADDR2;
1115 volatile uint8_t reserved7;
1116 /* 0x00E: SMB Control 3 */
1117 volatile uint8_t SMBCTL3;
1118 /* 0x00F: SMB Bus Timeout */
1119 volatile uint8_t SMBT_OUT;
1120 union {
1121 /* Bank 0 */
1122 struct {
1123 /* 0x010: SMB Own Address 3 */
1124 volatile uint8_t SMBADDR3;
1125 /* 0x011: SMB Own Address 7 */
1126 volatile uint8_t SMBADDR7;
1127 /* 0x012: SMB Own Address 4 */
1128 volatile uint8_t SMBADDR4;
1129 /* 0x013: SMB Own Address 8 */
1130 volatile uint8_t SMBADDR8;
1131 /* 0x014: SMB Own Address 5 */
1132 volatile uint8_t SMBADDR5;
1133 volatile uint8_t reserved8;
1134 /* 0x016: SMB Own Address 6 */
1135 volatile uint8_t SMBADDR6;
1136 volatile uint8_t reserved9;
1137 /* 0x018: SMB Control Status 2 */
1138 volatile uint8_t SMBCST2;
1139 /* 0x019: SMB Control Status 3 */
1140 volatile uint8_t SMBCST3;
1141 /* 0x01A: SMB Control 4 */
1142 volatile uint8_t SMBCTL4;
1143 volatile uint8_t reserved10;
1144 /* 0x01C: SMB SCL Low Time */
1145 volatile uint8_t SMBSCLLT;
1146 /* 0x01D: SMB FIFO Control */
1147 volatile uint8_t SMBFIF_CTL;
1148 /* 0x01E: SMB SCL High Time */
1149 volatile uint8_t SMBSCLHT;
1150 volatile uint8_t reserved11;
1151 };
1152 /* Bank 1 */
1153 struct {
1154 /* 0x010: SMB FIFO Control */
1155 volatile uint8_t SMBFIF_CTS;
1156 volatile uint8_t reserved12;
1157 /* 0x012: SMB Tx-FIFO Control */
1158 volatile uint8_t SMBTXF_CTL;
1159 volatile uint8_t reserved13;
1160 /* 0x014: SMB Bus Timeout */
1161 volatile uint8_t SMB_T_OUT;
1162 volatile uint8_t reserved14[3];
1163 /* 0x018: SMB Control Status 2 (FIFO) */
1164 volatile uint8_t SMBCST2_FIFO;
1165 /* 0x019: SMB Control Status 3 (FIFO) */
1166 volatile uint8_t SMBCST3_FIFO;
1167 /* 0x01A: SMB Tx-FIFO Status */
1168 volatile uint8_t SMBTXF_STS;
1169 volatile uint8_t reserved15;
1170 /* 0x01C: SMB Rx-FIFO Status */
1171 volatile uint8_t SMBRXF_STS;
1172 volatile uint8_t reserved16;
1173 /* 0x01E: SMB Rx-FIFO Control */
1174 volatile uint8_t SMBRXF_CTL;
1175 volatile uint8_t reserved17[1];
1176 };
1177 };
1178 };
1179
1180 /* SMB register fields */
1181 #define NPCX_SMBST_XMIT 0
1182 #define NPCX_SMBST_MASTER 1
1183 #define NPCX_SMBST_NMATCH 2
1184 #define NPCX_SMBST_STASTR 3
1185 #define NPCX_SMBST_NEGACK 4
1186 #define NPCX_SMBST_BER 5
1187 #define NPCX_SMBST_SDAST 6
1188 #define NPCX_SMBST_SLVSTP 7
1189 #define NPCX_SMBCST_BUSY 0
1190 #define NPCX_SMBCST_BB 1
1191 #define NPCX_SMBCST_MATCH 2
1192 #define NPCX_SMBCST_GCMATCH 3
1193 #define NPCX_SMBCST_TSDA 4
1194 #define NPCX_SMBCST_TGSCL 5
1195 #define NPCX_SMBCST_MATCHAF 6
1196 #define NPCX_SMBCST_ARPMATCH 7
1197 #define NPCX_SMBCST2_MATCHA1F 0
1198 #define NPCX_SMBCST2_MATCHA2F 1
1199 #define NPCX_SMBCST2_MATCHA3F 2
1200 #define NPCX_SMBCST2_MATCHA4F 3
1201 #define NPCX_SMBCST2_MATCHA5F 4
1202 #define NPCX_SMBCST2_MATCHA6F 5
1203 #define NPCX_SMBCST2_MATCHA7F 6
1204 #define NPCX_SMBCST2_INTSTS 7
1205 #define NPCX_SMBCST3_MATCHA8F 0
1206 #define NPCX_SMBCST3_MATCHA9F 1
1207 #define NPCX_SMBCST3_MATCHA10F 2
1208 #define NPCX_SMBCTL1_START 0
1209 #define NPCX_SMBCTL1_STOP 1
1210 #define NPCX_SMBCTL1_INTEN 2
1211 #define NPCX_SMBCTL1_ACK 4
1212 #define NPCX_SMBCTL1_GCMEN 5
1213 #define NPCX_SMBCTL1_NMINTE 6
1214 #define NPCX_SMBCTL1_STASTRE 7
1215 #define NPCX_SMBCTL2_ENABLE 0
1216 #define NPCX_SMBCTL2_SCLFRQ0_6_FIELD FIELD(1, 7)
1217 #define NPCX_SMBCTL3_ARPMEN 2
1218 #define NPCX_SMBCTL3_SCLFRQ7_8_FIELD FIELD(0, 2)
1219 #define NPCX_SMBCTL3_IDL_START 3
1220 #define NPCX_SMBCTL3_400K 4
1221 #define NPCX_SMBCTL3_BNK_SEL 5
1222 #define NPCX_SMBCTL3_SDA_LVL 6
1223 #define NPCX_SMBCTL3_SCL_LVL 7
1224 #define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
1225 #define NPCX_SMBCTL4_LVL_WE 7
1226 #define NPCX_SMBADDR1_SAEN 7
1227 #define NPCX_SMBADDR2_SAEN 7
1228 #define NPCX_SMBADDR3_SAEN 7
1229 #define NPCX_SMBADDR4_SAEN 7
1230 #define NPCX_SMBADDR5_SAEN 7
1231 #define NPCX_SMBADDR6_SAEN 7
1232 #define NPCX_SMBADDR7_SAEN 7
1233 #define NPCX_SMBADDR8_SAEN 7
1234 #define NPCX_SMBSEL_SMB4SEL 4
1235 #define NPCX_SMBSEL_SMB5SEL 5
1236 #define NPCX_SMBSEL_SMB6SEL 6
1237 #define NPCX_SMBFIF_CTS_RXF_TXE 1
1238 #define NPCX_SMBFIF_CTS_CLR_FIFO 6
1239 #define NPCX_SMBFIF_CTL_FIFO_EN 4
1240 #define NPCX_SMBRXF_STS_RX_THST 6
1241
1242 /* RX FIFO threshold */
1243 #define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
1244 #define NPCX_SMBRXF_CTL_LAST 7
1245
1246 /*
1247 * Internal 32-bit Timer (ITIM32) device registers
1248 */
1249 struct itim32_reg {
1250 volatile uint8_t reserved1;
1251 /* 0x001: Internal 32-bit Timer Prescaler */
1252 volatile uint8_t ITPRE32;
1253 volatile uint8_t reserved2[2];
1254 /* 0x004: Internal 32-bit Timer Control and Status */
1255 volatile uint8_t ITCTS32;
1256 volatile uint8_t reserved3[3];
1257 /* 0x008: Internal 32-Bit Timer Counter */
1258 volatile uint32_t ITCNT32;
1259 };
1260
1261 /*
1262 * Internal 64-bit Timer (ITIM54) device registers
1263 */
1264 struct itim64_reg {
1265 volatile uint8_t reserved1;
1266 /* 0x001: Internal 64-bit Timer Prescaler */
1267 volatile uint8_t ITPRE64;
1268 volatile uint8_t reserved2[2];
1269 /* 0x004: Internal 64-bit Timer Control and Status */
1270 volatile uint8_t ITCTS64;
1271 volatile uint8_t reserved3[3];
1272 /* 0x008: Internal 32-Bit Timer Counter */
1273 volatile uint32_t ITCNT64L;
1274 /* 0x00C: Internal 32-Bit Timer Counter */
1275 volatile uint32_t ITCNT64H;
1276 };
1277
1278 /* ITIM register fields */
1279 #define NPCX_ITCTSXX_TO_STS 0
1280 #define NPCX_ITCTSXX_TO_IE 2
1281 #define NPCX_ITCTSXX_TO_WUE 3
1282 #define NPCX_ITCTSXX_CKSEL 4
1283 #define NPCX_ITCTSXX_ITEN 7
1284
1285 /*
1286 * Tachometer (TACH) Sensor device registers
1287 */
1288 struct tach_reg {
1289 /* 0x000: Timer/Counter 1 */
1290 volatile uint16_t TCNT1;
1291 /* 0x002: Reload/Capture A */
1292 volatile uint16_t TCRA;
1293 /* 0x004: Reload/Capture B */
1294 volatile uint16_t TCRB;
1295 /* 0x006: Timer/Counter 2 */
1296 volatile uint16_t TCNT2;
1297 /* 0x008: Clock Prescaler */
1298 volatile uint8_t TPRSC;
1299 volatile uint8_t reserved1;
1300 /* 0x00A: Clock Unit Control */
1301 volatile uint8_t TCKC;
1302 volatile uint8_t reserved2;
1303 /* 0x00C: Timer Mode Control */
1304 volatile uint8_t TMCTRL;
1305 volatile uint8_t reserved3;
1306 /* 0x00E: Timer Event Control */
1307 volatile uint8_t TECTRL;
1308 volatile uint8_t reserved4;
1309 /* 0x010: Timer Event Clear */
1310 volatile uint8_t TECLR;
1311 volatile uint8_t reserved5;
1312 /* 0x012: Timer Interrupt Enable */
1313 volatile uint8_t TIEN;
1314 volatile uint8_t reserved6;
1315 /* 0x014: Compare A */
1316 volatile uint16_t TCPA;
1317 /* 0x016: Compare B */
1318 volatile uint16_t TCPB;
1319 /* 0x018: Compare Configuration */
1320 volatile uint8_t TCPCFG;
1321 volatile uint8_t reserved7;
1322 /* 0x01A: Timer Wake-Up Enable */
1323 volatile uint8_t TWUEN;
1324 volatile uint8_t reserved8;
1325 /* 0x01C: Timer Configuration */
1326 volatile uint8_t TCFG;
1327 volatile uint8_t reserved9;
1328 };
1329
1330 /* TACH register fields */
1331 #define NPCX_TCKC_LOW_PWR 7
1332 #define NPCX_TCKC_PLS_ACC_CLK 6
1333 #define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
1334 #define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
1335 #define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
1336 #define NPCX_TMCTRL_TAEN 5
1337 #define NPCX_TMCTRL_TBEN 6
1338 #define NPCX_TMCTRL_TAEDG 3
1339 #define NPCX_TMCTRL_TBEDG 4
1340 #define NPCX_TCFG_TADBEN 6
1341 #define NPCX_TCFG_TBDBEN 7
1342 #define NPCX_TECTRL_TAPND 0
1343 #define NPCX_TECTRL_TBPND 1
1344 #define NPCX_TECTRL_TCPND 2
1345 #define NPCX_TECTRL_TDPND 3
1346 #define NPCX_TECLR_TACLR 0
1347 #define NPCX_TECLR_TBCLR 1
1348 #define NPCX_TECLR_TCCLR 2
1349 #define NPCX_TECLR_TDCLR 3
1350 #define NPCX_TIEN_TAIEN 0
1351 #define NPCX_TIEN_TBIEN 1
1352 #define NPCX_TIEN_TCIEN 2
1353 #define NPCX_TIEN_TDIEN 3
1354 #define NPCX_TWUEN_TAWEN 0
1355 #define NPCX_TWUEN_TBWEN 1
1356 #define NPCX_TWUEN_TCWEN 2
1357 #define NPCX_TWUEN_TDWEN 3
1358
1359 /* Debug Interface registers */
1360 struct dbg_reg {
1361 /* 0x000: Debug Control */
1362 volatile uint8_t DBGCTRL;
1363 volatile uint8_t reserved1;
1364 /* 0x002: Debug Freeze Enable 1 */
1365 volatile uint8_t DBGFRZEN1;
1366 /* 0x003: Debug Freeze Enable 2 */
1367 volatile uint8_t DBGFRZEN2;
1368 /* 0x004: Debug Freeze Enable 3 */
1369 volatile uint8_t DBGFRZEN3;
1370 /* 0x005: Debug Freeze Enable 4 */
1371 volatile uint8_t DBGFRZEN4;
1372 };
1373 /* Debug Interface registers fields */
1374 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
1375
1376 /* PS/2 Interface registers */
1377 struct ps2_reg {
1378 /* 0x000: PS/2 Data */
1379 volatile uint8_t PSDAT;
1380 volatile uint8_t reserved1;
1381 /* 0x002: PS/2 Status */
1382 volatile uint8_t PSTAT;
1383 volatile uint8_t reserved2;
1384 /* 0x004: PS/2 Control */
1385 volatile uint8_t PSCON;
1386 volatile uint8_t reserved3;
1387 /* 0x006: PS/2 Output Signal */
1388 volatile uint8_t PSOSIG;
1389 volatile uint8_t reserved4;
1390 /* 0x008: PS/2 Input Signal */
1391 volatile uint8_t PSISIG;
1392 volatile uint8_t reserved5;
1393 /* 0x00A: PS/2 Interrupt Enable */
1394 volatile uint8_t PSIEN;
1395 volatile uint8_t reserved6;
1396 };
1397
1398 /* PS/2 Interface registers fields */
1399 #define NPCX_PSTAT_SOT 0
1400 #define NPCX_PSTAT_EOT 1
1401 #define NPCX_PSTAT_PERR 2
1402 #define NPCX_PSTAT_ACH FIELD(3, 3)
1403 #define NPCX_PSTAT_RFERR 6
1404
1405 #define NPCX_PSCON_EN 0
1406 #define NPCX_PSCON_XMT 1
1407 #define NPCX_PSCON_HDRV FIELD(2, 2)
1408 #define NPCX_PSCON_IDB FIELD(4, 3)
1409 #define NPCX_PSCON_WPUED 7
1410
1411 #define NPCX_PSOSIG_WDAT0 0
1412 #define NPCX_PSOSIG_WDAT1 1
1413 #define NPCX_PSOSIG_WDAT2 2
1414 #define NPCX_PSOSIG_CLK0 3
1415 #define NPCX_PSOSIG_CLK1 4
1416 #define NPCX_PSOSIG_CLK2 5
1417 #define NPCX_PSOSIG_WDAT3 6
1418 #define NPCX_PSOSIG_CLK3 7
1419 #define NPCX_PSOSIG_CLK(n) (((n) < 3) ? ((n) + 3) : 7)
1420 #define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
1421 #define NPCX_PSOSIG_CLK_MASK_ALL \
1422 (BIT(NPCX_PSOSIG_CLK0) | \
1423 BIT(NPCX_PSOSIG_CLK1) | \
1424 BIT(NPCX_PSOSIG_CLK2) | \
1425 BIT(NPCX_PSOSIG_CLK3))
1426
1427 #define NPCX_PSIEN_SOTIE 0
1428 #define NPCX_PSIEN_EOTIE 1
1429 #define NPCX_PSIEN_PS2_WUE 4
1430 #define NPCX_PSIEN_PS2_CLK_SEL 7
1431
1432 /* Flash Interface Unit (FIU) device registers */
1433 struct fiu_reg {
1434 volatile uint8_t reserved1;
1435 /* 0x001: Burst Configuration */
1436 volatile uint8_t BURST_CFG;
1437 /* 0x002: FIU Response Configuration */
1438 volatile uint8_t RESP_CFG;
1439 volatile uint8_t reserved2[17];
1440 /* 0x014: SPI Flash Configuration */
1441 volatile uint8_t SPI_FL_CFG;
1442 volatile uint8_t reserved3;
1443 /* 0x016: UMA Code Byte */
1444 volatile uint8_t UMA_CODE;
1445 /* 0x017: UMA Address Byte 0 */
1446 volatile uint8_t UMA_AB0;
1447 /* 0x018: UMA Address Byte 1 */
1448 volatile uint8_t UMA_AB1;
1449 /* 0x019: UMA Address Byte 2 */
1450 volatile uint8_t UMA_AB2;
1451 /* 0x01A: UMA Data Byte 0 */
1452 volatile uint8_t UMA_DB0;
1453 /* 0x01B: UMA Data Byte 1 */
1454 volatile uint8_t UMA_DB1;
1455 /* 0x01C: UMA Data Byte 2 */
1456 volatile uint8_t UMA_DB2;
1457 /* 0x01D: UMA Data Byte 3 */
1458 volatile uint8_t UMA_DB3;
1459 /* 0x01E: UMA Control and Status */
1460 volatile uint8_t UMA_CTS;
1461 /* 0x01F: UMA Extended Control and Status */
1462 volatile uint8_t UMA_ECTS;
1463 /* 0x020: UMA Data Bytes 0-3 */
1464 volatile uint32_t UMA_DB0_3;
1465 volatile uint8_t reserved4[2];
1466 /* 0x026: CRC Control Register */
1467 volatile uint8_t CRCCON;
1468 /* 0x027: CRC Entry Register */
1469 volatile uint8_t CRCENT;
1470 /* 0x028: CRC Initialization and Result Register */
1471 volatile uint32_t CRCRSLT;
1472 volatile uint8_t reserved5[4];
1473 /* 0x030: FIU Read Command */
1474 volatile uint8_t FIU_RD_CMD;
1475 volatile uint8_t reserved6;
1476 /* 0x032: FIU Dummy Cycles */
1477 volatile uint8_t FIU_DMM_CYC;
1478 /* 0x033: FIU Extended Configuration */
1479 volatile uint8_t FIU_EXT_CFG;
1480 #if defined(CONFIG_SOC_SERIES_NPCX9)
1481 /* 0x034: UMA address byte 0-3 */
1482 volatile uint32_t UMA_AB0_3;
1483 /* 0x038-0x3C */
1484 volatile uint8_t reserved8[5];
1485 /* 0x03D: SPI Device */
1486 volatile uint8_t SPI1_DEV;
1487 /* 0x03E-0x3F */
1488 volatile uint8_t reserved9[2];
1489 #elif defined(CONFIG_SOC_SERIES_NPCX4)
1490 /* 0x034: UMA address byte 0-3 */
1491 volatile uint32_t UMA_AB0_3;
1492 /* 0x038-0x3B */
1493 volatile uint8_t reserved8[4];
1494 /* 0x03C: SPI Device */
1495 volatile uint8_t SPI_DEV;
1496 /* 0x03D */
1497 volatile uint8_t reserved9;
1498 /* 0x03E */
1499 volatile uint8_t SPI_DEV_SIZE;
1500 /* 0x03F */
1501 volatile uint8_t reserved10;
1502 #endif
1503 };
1504
1505 /* FIU register fields */
1506 #define NPCX_BURST_CFG_SPI_DEV_SEL FIELD(4, 2)
1507 #define NPCX_RESP_CFG_IAD_EN 0
1508 #define NPCX_RESP_CFG_DEV_SIZE_EX 2
1509 #define NPCX_RESP_CFG_QUAD_EN 3
1510 #define NPCX_SPI_FL_CFG_RD_MODE FIELD(6, 2)
1511 #define NPCX_UMA_CTS_A_SIZE 3
1512 #define NPCX_UMA_CTS_C_SIZE 4
1513 #define NPCX_UMA_CTS_RD_WR 5
1514 #define NPCX_UMA_CTS_DEV_NUM 6
1515 #define NPCX_UMA_CTS_EXEC_DONE 7
1516 #define NPCX_UMA_ECTS_SW_CS0 0
1517 #define NPCX_UMA_ECTS_SW_CS1 1
1518 #define NPCX_UMA_ECTS_SEC_CS 2
1519 #define NPCX_UMA_ECTS_UMA_LOCK 3
1520 #define NPCX_UMA_ECTS_UMA_ADDR_SIZE FIELD(4, 3)
1521 #define NPCX_SPI1_DEV_FOUR_BADDR_CS10 6
1522 #define NPCX_SPI1_DEV_FOUR_BADDR_CS11 7
1523 #define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
1524 #define NPCX_FIU_EXT_CFG_SET_DMM_EN 2
1525 #define NPCX_FIU_EXT_CFG_SET_CMD_EN 1
1526 #define NPCX_SPI_DEV_NADDRB FIELD(5, 3)
1527
1528 #define NPCX_MSR_IE_CFG_UMA_BLOCK 3
1529
1530 /* UMA fields selections */
1531 #define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
1532 #define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE) /* No 1-Byte CMD field */
1533 #define UMA_FLD_WRITE BIT(NPCX_UMA_CTS_RD_WR) /* Write transaction */
1534 #define UMA_FLD_SHD_SL BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
1535 #define UMA_FLD_EXEC BIT(NPCX_UMA_CTS_EXEC_DONE)
1536
1537 #define UMA_FIELD_DATA_1 0x01
1538 #define UMA_FIELD_DATA_2 0x02
1539 #define UMA_FIELD_DATA_3 0x03
1540 #define UMA_FIELD_DATA_4 0x04
1541
1542 /* UMA code for transaction */
1543 #define UMA_CODE_CMD_ONLY (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
1544 #define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | \
1545 UMA_FLD_SHD_SL)
1546 #define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
1547 UMA_FLD_SHD_SL)
1548 #define UMA_CODE_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
1549 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1550 #define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1551 UMA_FLD_SHD_SL)
1552 #define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1553 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1554 #define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
1555 UMA_FLD_SHD_SL)
1556
1557 #define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1558 UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
1559 UMA_FLD_SHD_SL)
1560
1561 /* Platform Environment Control Interface (PECI) device registers */
1562 struct peci_reg {
1563 /* 0x000: PECI Control Status */
1564 volatile uint8_t PECI_CTL_STS;
1565 /* 0x001: PECI Read Length */
1566 volatile uint8_t PECI_RD_LENGTH;
1567 /* 0x002: PECI Address */
1568 volatile uint8_t PECI_ADDR;
1569 /* 0x003: PECI Command */
1570 volatile uint8_t PECI_CMD;
1571 /* 0x004: PECI Control 2 */
1572 volatile uint8_t PECI_CTL2;
1573 /* 0x005: PECI Index */
1574 volatile uint8_t PECI_INDEX;
1575 /* 0x006: PECI Index Data */
1576 volatile uint8_t PECI_IDATA;
1577 /* 0x007: PECI Write Length */
1578 volatile uint8_t PECI_WR_LENGTH;
1579 volatile uint8_t reserved1[3];
1580 /* 0x00B: PECI Write FCS */
1581 volatile uint8_t PECI_WR_FCS;
1582 /* 0x00C: PECI Read FCS */
1583 volatile uint8_t PECI_RD_FCS;
1584 /* 0x00D: PECI Assured Write FCS */
1585 volatile uint8_t PECI_AW_FCS;
1586 volatile uint8_t reserved2;
1587 /* 0x00F: PECI Transfer Rate */
1588 volatile uint8_t PECI_RATE;
1589 /* 0x010 - 0x04F: PECI Data In/Out */
1590 union {
1591 volatile uint8_t PECI_DATA_IN[64];
1592 volatile uint8_t PECI_DATA_OUT[64];
1593 };
1594 };
1595
1596 /* PECI register fields */
1597 #define NPCX_PECI_CTL_STS_START_BUSY 0
1598 #define NPCX_PECI_CTL_STS_DONE 1
1599 #define NPCX_PECI_CTL_STS_CRC_ERR 3
1600 #define NPCX_PECI_CTL_STS_ABRT_ERR 4
1601 #define NPCX_PECI_CTL_STS_AWFCS_EB 5
1602 #define NPCX_PECI_CTL_STS_DONE_EN 6
1603 #define NPCX_PECI_RATE_MAX_BIT_RATE FIELD(0, 5)
1604 #define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
1605 /* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
1606 #define PECI_MAX_BIT_RATE_VALID_MIN 0x05
1607 #define PECI_HIGH_SPEED_MIN_VAL 0x07
1608
1609 #define NPCX_PECI_RATE_EHSP 6
1610
1611 /* KBS (Keyboard Scan) device registers */
1612 struct kbs_reg {
1613 volatile uint8_t reserved1[4];
1614 /* 0x004: Keyboard Scan In */
1615 volatile uint8_t KBSIN;
1616 /* 0x005: Keyboard Scan In Pull-Up Enable */
1617 volatile uint8_t KBSINPU;
1618 /* 0x006: Keyboard Scan Out 0 */
1619 volatile uint16_t KBSOUT0;
1620 /* 0x008: Keyboard Scan Out 1 */
1621 volatile uint16_t KBSOUT1;
1622 /* 0x00A: Keyboard Scan Buffer Index */
1623 volatile uint8_t KBS_BUF_INDX;
1624 /* 0x00B: Keyboard Scan Buffer Data */
1625 volatile uint8_t KBS_BUF_DATA;
1626 /* 0x00C: Keyboard Scan Event */
1627 volatile uint8_t KBSEVT;
1628 /* 0x00D: Keyboard Scan Control */
1629 volatile uint8_t KBSCTL;
1630 /* 0x00E: Keyboard Scan Configuration Index */
1631 volatile uint8_t KBS_CFG_INDX;
1632 /* 0x00F: Keyboard Scan Configuration Data */
1633 volatile uint8_t KBS_CFG_DATA;
1634 };
1635
1636 /* KBS register fields */
1637 #define NPCX_KBSBUFINDX 0
1638 #define NPCX_KBSEVT_KBSDONE 0
1639 #define NPCX_KBSEVT_KBSERR 1
1640 #define NPCX_KBSCTL_START 0
1641 #define NPCX_KBSCTL_KBSMODE 1
1642 #define NPCX_KBSCTL_KBSIEN 2
1643 #define NPCX_KBSCTL_KBSINC 3
1644 #define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
1645 #define NPCX_KBSCFGINDX 0
1646 /* Index of 'Automatic Scan' configuration register */
1647 #define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */
1648 #define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */
1649 #define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */
1650 #define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */
1651 #define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */
1652
1653 /* SHI (Serial Host Interface) registers */
1654 struct shi_reg {
1655 volatile uint8_t reserved1;
1656 /* 0x001: SHI Configuration 1 */
1657 volatile uint8_t SHICFG1;
1658 /* 0x002: SHI Configuration 2 */
1659 volatile uint8_t SHICFG2;
1660 volatile uint8_t reserved2[2];
1661 /* 0x005: Event Enable */
1662 volatile uint8_t EVENABLE;
1663 /* 0x006: Event Status */
1664 volatile uint8_t EVSTAT;
1665 /* 0x007: SHI Capabilities */
1666 volatile uint8_t CAPABILITY;
1667 /* 0x008: Status */
1668 volatile uint8_t STATUS;
1669 volatile uint8_t reserved3;
1670 /* 0x00A: Input Buffer Status */
1671 volatile uint8_t IBUFSTAT;
1672 /* 0x00B: Output Buffer Status */
1673 volatile uint8_t OBUFSTAT;
1674 /* 0x00C: SHI Configuration 3 */
1675 volatile uint8_t SHICFG3;
1676 /* 0x00D: SHI Configuration 4 */
1677 volatile uint8_t SHICFG4;
1678 /* 0x00E: SHI Configuration 5 */
1679 volatile uint8_t SHICFG5;
1680 /* 0x00F: Event Status 2 */
1681 volatile uint8_t EVSTAT2;
1682 /* 0x010: Event Enable 2 */
1683 volatile uint8_t EVENABLE2;
1684 /* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
1685 volatile uint8_t SHICFG6;
1686 /* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */
1687 volatile uint8_t SBOBUF;
1688 volatile uint8_t reserved4[13];
1689 /* 0x20~0x9F: Output Buffer */
1690 volatile uint8_t OBUF[128];
1691 /* 0xA0~0x11F: Input Buffer */
1692 volatile uint8_t IBUF[128];
1693 };
1694
1695 /* SHI register fields */
1696 #define NPCX_SHICFG1_EN 0
1697 #define NPCX_SHICFG1_MODE 1
1698 #define NPCX_SHICFG1_WEN 2
1699 #define NPCX_SHICFG1_AUTIBF 3
1700 #define NPCX_SHICFG1_AUTOBE 4
1701 #define NPCX_SHICFG1_DAS 5
1702 #define NPCX_SHICFG1_CPOL 6
1703 #define NPCX_SHICFG1_IWRAP 7
1704 #define NPCX_SHICFG2_SIMUL 0
1705 #define NPCX_SHICFG2_BUSY 1
1706 #define NPCX_SHICFG2_ONESHOT 2
1707 #define NPCX_SHICFG2_SLWU 3
1708 #define NPCX_SHICFG2_REEN 4
1709 #define NPCX_SHICFG2_RESTART 5
1710 #define NPCX_SHICFG2_REEVEN 6
1711 #define NPCX_EVENABLE_OBEEN 0
1712 #define NPCX_EVENABLE_OBHEEN 1
1713 #define NPCX_EVENABLE_IBFEN 2
1714 #define NPCX_EVENABLE_IBHFEN 3
1715 #define NPCX_EVENABLE_EOREN 4
1716 #define NPCX_EVENABLE_EOWEN 5
1717 #define NPCX_EVENABLE_STSREN 6
1718 #define NPCX_EVENABLE_IBOREN 7
1719 #define NPCX_EVSTAT_OBE 0
1720 #define NPCX_EVSTAT_OBHE 1
1721 #define NPCX_EVSTAT_IBF 2
1722 #define NPCX_EVSTAT_IBHF 3
1723 #define NPCX_EVSTAT_EOR 4
1724 #define NPCX_EVSTAT_EOW 5
1725 #define NPCX_EVSTAT_STSR 6
1726 #define NPCX_EVSTAT_IBOR 7
1727 #define NPCX_STATUS_OBES 6
1728 #define NPCX_STATUS_IBFS 7
1729 #define NPCX_SHICFG3_OBUFLVLDIS 7
1730 #define NPCX_SHICFG4_IBUFLVLDIS 7
1731 #define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
1732 #define NPCX_SHICFG5_IBUFLVL2DIS 7
1733 #define NPCX_EVSTAT2_IBHF2 0
1734 #define NPCX_EVSTAT2_CSNRE 1
1735 #define NPCX_EVSTAT2_CSNFE 2
1736 #define NPCX_EVENABLE2_IBHF2EN 0
1737 #define NPCX_EVENABLE2_CSNREEN 1
1738 #define NPCX_EVENABLE2_CSNFEEN 2
1739 #define NPCX_SHICFG6_EBUFMD 0
1740 #define NPCX_SHICFG6_OBUF_SL 1
1741
1742 #define IBF_IBHF_EN_MASK (BIT(NPCX_EVENABLE_IBFEN) | BIT(NPCX_EVENABLE_IBHFEN))
1743
1744 /* SPIP (SPI Peripheral Interface) registers */
1745 struct spip_reg {
1746 /* 0x000: SPIP Data In/Out */
1747 volatile uint16_t SPIP_DATA;
1748 /* 0x002: SPIP Control 1 */
1749 volatile uint16_t SPIP_CTL1;
1750 /* 0x004: SPIP Status */
1751 volatile uint8_t SPIP_STAT;
1752 volatile uint8_t reserved1;
1753 };
1754
1755 #define NPCX_SPIP_CTL1_SPIEN 0
1756 #define NPCX_SPIP_CTL1_MOD 2
1757 #define NPCX_SPIP_CTL1_EIR 5
1758 #define NPCX_SPIP_CTL1_EIW 6
1759 #define NPCX_SPIP_CTL1_SCM 7
1760 #define NPCX_SPIP_CTL1_SCIDL 8
1761 #define NPCX_SPIP_CTL1_SCDV FIELD(9, 7)
1762 #define NPCX_SPIP_STAT_BSY 0
1763 #define NPCX_SPIP_STAT_RBF 1
1764
1765 /* Software-triggered Pheripheral Reset Controller Register */
1766 struct swrst_reg {
1767 /* 0x000: Software Reset Trigger */
1768 volatile uint16_t SWRST_TRG;
1769 volatile uint8_t reserved1[2];
1770 volatile uint32_t SWRST_CTL[4];
1771 };
1772
1773 /* Improved Inter Integrated Circuit (I3C) device registers */
1774 struct i3c_reg {
1775 /* 0x000: Controller Configuration */
1776 volatile uint32_t MCONFIG;
1777 /* 0x004: Target Configuration */
1778 volatile uint32_t CONFIG;
1779 volatile uint32_t reserved1[31];
1780 /* 0x084: Controller Control */
1781 volatile uint32_t MCTRL;
1782 /* 0x088: Controller Status */
1783 volatile uint32_t MSTATUS;
1784 /* 0x08C: IBI Registry and Rules */
1785 volatile uint32_t IBIRULES;
1786 /* 0x090: Controller Interrupt Enable Set */
1787 volatile uint32_t MINTSET;
1788 /* 0x094: Controller Interrupt Enable Clear */
1789 volatile uint32_t MINTCLR;
1790 /* 0x098: Controller Interrupt Masked */
1791 volatile uint32_t MINTMASKED;
1792 /* 0x09C: Controller Error and Warning */
1793 volatile uint32_t MERRWARN;
1794 /* 0x0A0: Controller DMA Control */
1795 volatile uint32_t MDMACTRL;
1796 volatile uint32_t reserved2[2];
1797 /* 0x0AC: Controller Data Control */
1798 volatile uint32_t MDATACTRL;
1799 /* 0x0B0: Controller Write Byte Data */
1800 volatile uint32_t MWDATAB;
1801 /* 0x0B4: Controller Write Byte Data as End */
1802 volatile uint32_t MWDATABE;
1803 /* 0x0B8: Controller Write Half-Word Data */
1804 volatile uint32_t MWDATAH;
1805 /* 0x0BC: Controller Write Half-Word Data as End */
1806 volatile uint32_t MWDATAHE;
1807 /* 0x0C0: Controller Read Byte Data */
1808 volatile uint32_t MRDATAB;
1809 volatile uint32_t reserved3;
1810 /* 0x0C8: Controller Read Half-Word Data */
1811 volatile uint32_t MRDATAH;
1812 volatile uint32_t reserved4[3];
1813 /* 0x0D8: Start or Continue DDR Message */
1814 volatile uint32_t MWMSG_DDR;
1815 /* 0x0DC: Read DDR Message Data */
1816 volatile uint32_t MRMSG_DDR;
1817 volatile uint32_t reserved5;
1818 /* 0x0E4: Controller Dynamic Address */
1819 volatile uint32_t MDYNADDR;
1820 };
1821
1822 /* I3C register fields */
1823 #define NPCX_I3C_CONFIG_BAMATCH FIELD(16, 7)
1824 #define NPCX_I3C_MCONFIG_CTRENA FIELD(0, 2)
1825 #define NPCX_I3C_MCONFIG_DISTO 3
1826 #define NPCX_I3C_MCONFIG_HKEEP FIELD(4, 2) /* Must be '11' */
1827 #define NPCX_I3C_MCONFIG_ODSTOP 6
1828 #define NPCX_I3C_MCONFIG_PPBAUD FIELD(8, 4)
1829 #define NPCX_I3C_MCONFIG_PPLOW FIELD(12, 4)
1830 #define NPCX_I3C_MCONFIG_ODBAUD FIELD(16, 8)
1831 #define NPCX_I3C_MCONFIG_ODHPP 24
1832 #define NPCX_I3C_MCONFIG_SKEW FIELD(25, 3)
1833 #define NPCX_I3C_MCONFIG_I2CBAUD FIELD(28, 4)
1834 #define NPCX_I3C_MCTRL_REQUEST FIELD(0, 3)
1835 #define NPCX_I3C_MCTRL_TYPE FIELD(4, 2)
1836 #define NPCX_I3C_MCTRL_IBIRESP FIELD(6, 2)
1837 #define NPCX_I3C_MCTRL_DIR 8
1838 #define NPCX_I3C_MCTRL_ADDR FIELD(9, 7)
1839 #define NPCX_I3C_MCTRL_RDTERM FIELD(16, 8)
1840 #define NPCX_I3C_MSTATUS_STATE FIELD(0, 3)
1841 #define NPCX_I3C_MSTATUS_BETWEEN 4
1842 #define NPCX_I3C_MSTATUS_NACKED 5
1843 #define NPCX_I3C_MSTATUS_IBITYPE FIELD(6, 2)
1844 #define NPCX_I3C_MSTATUS_TGTSTART 8
1845 #define NPCX_I3C_MSTATUS_MCTRLDONE 9
1846 #define NPCX_I3C_MSTATUS_COMPLETE 10
1847 #define NPCX_I3C_MSTATUS_RXPEND 11
1848 #define NPCX_I3C_MSTATUS_TXNOTFULL 12
1849 #define NPCX_I3C_MSTATUS_IBIWON 13
1850 #define NPCX_I3C_MSTATUS_ERRWARN 15
1851 #define NPCX_I3C_MSTATUS_NOWCNTLR 19
1852 #define NPCX_I3C_MSTATUS_IBIADDR FIELD(24, 7)
1853 #define NPCX_I3C_IBIRULES_MSB0 30
1854 #define NPCX_I3C_IBIRULES_NOBYTE 31
1855 #define NPCX_I3C_MINTSET_TGTSTART 8
1856 #define NPCX_I3C_MINTSET_MCTRLDONE 9
1857 #define NPCX_I3C_MINTSET_COMPLETE 10
1858 #define NPCX_I3C_MINTSET_RXPEND 11
1859 #define NPCX_I3C_MINTSET_TXNOTFULL 12
1860 #define NPCX_I3C_MINTSET_IBIWON 13
1861 #define NPCX_I3C_MINTSET_ERRWARN 15
1862 #define NPCX_I3C_MINTSET_NOWCNTLR 19
1863 #define NPCX_I3C_MINTCLR_TGTSTART 8
1864 #define NPCX_I3C_MINTCLR_MCTRLDONE 9
1865 #define NPCX_I3C_MINTCLR_COMPLETE 10
1866 #define NPCX_I3C_MINTCLR_RXPEND 11
1867 #define NPCX_I3C_MINTCLR_TXNOTFULL 12
1868 #define NPCX_I3C_MINTCLR_IBIWON 13
1869 #define NPCX_I3C_MINTCLR_ERRWARN 15
1870 #define NPCX_I3C_MINTCLR_NOWCNTLR 19
1871 #define NPCX_I3C_MDATACTRL_FLUSHTB 0
1872 #define NPCX_I3C_MDATACTRL_FLUSHFB 1
1873 #define NPCX_I3C_MDATACTRL_UNLOCK 3
1874 #define NPCX_I3C_MDATACTRL_TXTRIG FIELD(4, 2)
1875 #define NPCX_I3C_MDATACTRL_RXTRIG FIELD(6, 2)
1876 #define NPCX_I3C_MDATACTRL_TXCOUNT FIELD(16, 5)
1877 #define NPCX_I3C_MDATACTRL_RXCOUNT FIELD(24, 5)
1878 #define NPCX_I3C_MDATACTRL_TXFULL 30
1879 #define NPCX_I3C_MDATACTRL_RXEMPTY 31
1880 #define NPCX_I3C_MERRWARN_NACK 2
1881 #define NPCX_I3C_MERRWARN_WRABT 3
1882 #define NPCX_I3C_MERRWARN_TERM 4
1883 #define NPCX_I3C_MERRWARN_HPAR 9
1884 #define NPCX_I3C_MERRWARN_HCRC 10
1885 #define NPCX_I3C_MERRWARN_OREAD 16
1886 #define NPCX_I3C_MERRWARN_OWRITE 17
1887 #define NPCX_I3C_MERRWARN_MSGERR 18
1888 #define NPCX_I3C_MERRWARN_INVERQ 19
1889 #define NPCX_I3C_MERRWARN_TIMEOUT 20
1890 #define NPCX_I3C_MDMACTRL_DMAFB FIELD(0, 2)
1891 #define NPCX_I3C_MDMACTRL_DMATB FIELD(2, 2)
1892
1893
1894 /* MCONFIG options */
1895 #define MCONFIG_CTRENA_OFF 0x0
1896 #define MCONFIG_CTRENA_ON 0x1
1897 #define MCONFIG_CTRENA_CAPABLE 0x2
1898 #define MCONFIG_HKEEP_EXT_SDA_SCL 0x3
1899
1900 /* MCTRL options */
1901 #define MCTRL_REQUEST_NONE 0 /* None */
1902 #define MCTRL_REQUEST_EMITSTARTADDR 1 /* Emit a START */
1903 #define MCTRL_REQUEST_EMITSTOP 2 /* Emit a STOP */
1904 #define MCTRL_REQUEST_IBIACKNACK 3 /* Manually ACK or NACK an IBI */
1905 #define MCTRL_REQUEST_PROCESSDAA 4 /* Starts the DAA process */
1906 #define MCTRL_REQUEST_FORCEEXIT 6 /* Emit HDR Exit Pattern */
1907 /* Emits a START with address 7Eh when a slave pulls I3C_SDA low to request an IBI */
1908 #define MCTRL_REQUEST_AUTOIBI 7
1909
1910 /* ACK with mandatory byte determined by IBIRULES or ACK with no mandatory byte */
1911 #define MCTRL_IBIRESP_ACK 0
1912 #define MCTRL_IBIRESP_NACK 1 /* NACK */
1913 #define MCTRL_IBIRESP_ACK_MANDATORY 2 /* ACK with mandatory byte */
1914 #define MCTRL_IBIRESP_MANUAL 3
1915
1916 /* For REQUEST = EmitStartAddr */
1917 enum npcx_i3c_mctrl_type {
1918 NPCX_I3C_MCTRL_TYPE_I3C,
1919 NPCX_I3C_MCTRL_TYPE_I2C,
1920 NPCX_I3C_MCTRL_TYPE_I3C_HDR_DDR,
1921 };
1922
1923 /* For REQUEST = ForceExit/Target Reset */
1924 #define MCTRL_TYPE_HDR_EXIT 0
1925 #define MCTRL_TYPE_TGT_RESTART 2
1926
1927 /* MSTATUS options */
1928 #define MSTATUS_STATE_IDLE 0x0
1929 #define MSTATUS_STATE_TGTREQ 0x1
1930 #define MSTATUS_STATE_NORMACT 0x3 /* SDR message mode */
1931 #define MSTATUS_STATE_MSGDDR 0x4
1932 #define MSTATUS_STATE_DAA 0x5
1933 #define MSTATUS_STATE_IBIACK 0x6
1934 #define MSTATUS_STATE_IBIRCV 0x7
1935 #define MSTATUS_IBITYPE_NONE 0x0
1936 #define MSTATUS_IBITYPE_IBI 0x1
1937 #define MSTATUS_IBITYPE_CR 0x2
1938 #define MSTATUS_IBITYPE_HJ 0x3
1939
1940 /* IBIRULES */
1941 #define IBIRULES_ADDR_MSK 0x3F
1942 #define IBIRULES_ADDR_SHIFT 0x6
1943
1944 /* MDMACTRL options */
1945 #define MDMA_DMAFB_DISABLE 0x0
1946 #define MDMA_DMAFB_EN_ONE_FRAME 0x1
1947 #define MDMA_DMAFB_EN_MANUAL 0x2
1948 #define MDMA_DMATB_DISABLE 0x0
1949 #define MDMA_DMATB_EN_ONE_FRAME 0x1
1950 #define MDMA_DMATB_EN_MANUAL 0x2
1951
1952 /* MDMA Controller registers */
1953 struct mdma_reg {
1954 /* Channel 0 */
1955 /* 0x000: Channel 0 Control */
1956 volatile uint32_t MDMA_CTL0;
1957 /* 0x004: Channel 0 Source Base Address */
1958 volatile uint32_t MDMA_SRCB0;
1959 /* 0x008: Channel 0 Destination Base Address */
1960 volatile uint32_t MDMA_DSTB0;
1961 /* 0x00C: Channel 0 Transfer Count */
1962 volatile uint32_t MDMA_TCNT0;
1963 /* 0x010: reserved1 */
1964 volatile uint32_t reserved1;
1965 /* 0x014: Channel 0 Current Destination */
1966 volatile uint32_t MDMA_CDST0;
1967 /* 0x018: Channel 0 Current Transfer Count */
1968 volatile uint32_t MDMA_CTCNT0;
1969 /* 0x01C: reserved2 */
1970 volatile uint32_t reserved2;
1971
1972 /* Channel 1 */
1973 /* 0x020: Channel 1 Control */
1974 volatile uint32_t MDMA_CTL1;
1975 /* 0x024: Channel 1 Source Base Address */
1976 volatile uint32_t MDMA_SRCB1;
1977 /* 0x028: Channel 1 Destination Base Address */
1978 volatile uint32_t MDMA_DSTB1;
1979 /* 0x02C: Channel 1 Transfer Count */
1980 volatile uint32_t MDMA_TCNT1;
1981 /* 0x030: Channel 1 Current Source */
1982 volatile uint32_t MDMA_CSRC1;
1983 /* 0x034: reserved3 */
1984 volatile uint32_t reserved3;
1985 /* 0x038: Channel 1 Current Transfer Count */
1986 volatile uint32_t MDMA_CTCNT1;
1987 };
1988
1989 /* MDMA register fields */
1990 #define NPCX_MDMA_CTL_MDMAEN 0
1991 #define NPCX_MDMA_CTL_MPD 1
1992 #define NPCX_MDMA_CTL_SIEN 8
1993 #define NPCX_MDMA_CTL_MPS 14
1994 #define NPCX_MDMA_CTL_TC 18
1995 #define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 12)
1996
1997 #endif /* _NUVOTON_NPCX_REG_DEF_H */
1998
