1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2017 BayLibre, SAS.
4 * Copyright (c) 2023 Google Inc
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
10 #define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
11
12 #include <zephyr/drivers/flash.h>
13
14 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
15 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
16 #include <zephyr/drivers/clock_control.h>
17 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
18 #endif
19
20 /* Get the base address of the flash from the DTS node */
21 #define FLASH_STM32_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_nv_flash))
22
23 struct flash_stm32_priv {
24 FLASH_TypeDef *regs;
25 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
26 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
27 /* clock subsystem driving this peripheral */
28 struct stm32_pclken pclken;
29 #endif
30 struct k_sem sem;
31 };
32
33 #if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
34 #define FLASH_STM32_WRITE_BLOCK_SIZE \
35 DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
36 #else
37 #error Flash write block size not available
38 /* Flash Write block size is extracted from device tree */
39 /* as flash node property 'write-block-size' */
40 #endif
41
42 #if defined(CONFIG_SOC_SERIES_STM32H5X)
43 /* FLASH register names differ for this serie */
44 #define FLASH_NSSR_BSY FLASH_SR_BSY
45 #define OPTR OPTCR
46 #endif /* CONFIG_SOC_SERIES_STM32H5X */
47
48 /* Differentiate between arm trust-zone non-secure/secure, and others. */
49 #if defined(FLASH_NSSR_NSBSY) || defined(FLASH_NSSR_BSY) /* For mcu w. TZ in non-secure mode */
50 #define FLASH_SECURITY_NS
51 #define FLASH_STM32_SR NSSR
52 #elif defined(FLASH_SECSR_SECBSY) /* For mcu w. TZ in secured mode */
53 #error Flash is not supported in secure mode
54 #define FLASH_SECURITY_SEC
55 #else
56 #define FLASH_SECURITY_NA /* For series which does not have
57 * secured or non-secured mode
58 */
59 #define FLASH_STM32_SR SR
60 #endif
61
62
63 #define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
64 #define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
65
66
67 /* Redefinitions of flags and masks to harmonize stm32 series: */
68 #if defined(CONFIG_SOC_SERIES_STM32U5X)
69 #define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK
70 #define FLASH_STM32_DBANK FLASH_OPTR_DUALBANK
71 #define FLASH_STM32_NSPG FLASH_NSCR_PG
72 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_BKER_Msk
73 #define FLASH_STM32_NSBKER FLASH_NSCR_BKER
74 #define FLASH_STM32_NSPER FLASH_NSCR_PER
75 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_PNB_Msk
76 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_PNB_Pos
77 #define FLASH_STM32_NSPNB FLASH_NSCR_PNB
78 #define FLASH_STM32_NSSTRT FLASH_NSCR_STRT
79 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
80 #elif defined(CONFIG_SOC_SERIES_STM32H5X)
81 #define FLASH_OPTR_SWAP_BANK FLASH_OPTCR_SWAP_BANK
82 #define FLASH_STM32_NSLOCK FLASH_CR_LOCK
83 #define FLASH_STM32_DBANK 1
84 #define FLASH_STM32_NSPG FLASH_CR_PG
85 #define FLASH_STM32_NSBKER_MSK FLASH_CR_BKSEL_Msk
86 #define FLASH_STM32_NSBKER FLASH_CR_BKSEL
87 #define FLASH_STM32_NSPER FLASH_CR_SER
88 #define FLASH_STM32_NSPNB_MSK FLASH_CR_SNB_Msk
89 #define FLASH_STM32_NSPNB_POS FLASH_CR_SNB_Pos
90 #define FLASH_STM32_NSPNB FLASH_CR_PNB
91 #define FLASH_STM32_NSSTRT FLASH_CR_START
92 /* TODO: get values from the cmsis and stm32h5_hal_flash.h */
93 #undef FLASH_SIZE
94 /* Retrieve the FLASH SIZE from the DTS instead of cmsis as it seems erroneous */
95 #define FLASH_SIZE (CONFIG_FLASH_SIZE * 1024)
96 /* Values are redefined below from the stm32h5_hal_flash.h */
97 #define FLASH_PAGE_SIZE (FLASH_SECTOR_SIZE)
98 #define FLASH_PAGE_NB (FLASH_SECTOR_NB)
99 #define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
100 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
101 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
102 #define FLASH_STM32_NSLOCK FLASH_NSCR_NSLOCK
103 #define FLASH_STM32_NSPG FLASH_NSCR_NSPG
104 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_NSBKER_Pos
105 #define FLASH_STM32_NSBKER FLASH_NSCR_NSBKER
106 #define FLASH_STM32_NSPER FLASH_NSCR_NSPER
107 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_NSPNB_Msk
108 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_NSPNB_Pos
109 #define FLASH_STM32_NSPNB FLASH_NSCR_NSPNB
110 #define FLASH_STM32_NSSTRT FLASH_NSCR_NSSTRT
111 #elif defined(CONFIG_SOC_SERIES_STM32WBAX)
112 #define NSCR NSCR1
113 #define FLASH_STM32_NSLOCK FLASH_NSCR1_LOCK
114 #define FLASH_STM32_NSPG FLASH_NSCR1_PG
115 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR1_BKER_Msk
116 #define FLASH_STM32_NSBKER FLASH_NSCR1_BKER
117 #define FLASH_STM32_NSPER FLASH_NSCR1_PER
118 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR1_PNB_Msk
119 #define FLASH_STM32_NSPNB_POS FLASH_NSCR1_PNB_Pos
120 #define FLASH_STM32_NSPNB FLASH_NSCR1_PNB
121 #define FLASH_STM32_NSSTRT FLASH_NSCR1_STRT
122 #endif /* CONFIG_SOC_SERIES_STM32U5X */
123 #if defined(FLASH_OPTR_DBANK)
124 #define FLASH_STM32_DBANK FLASH_OPTR_DBANK
125 #endif /* FLASH_OPTR_DBANK */
126
127 #if defined(CONFIG_SOC_SERIES_STM32G0X)
128 #if defined(FLASH_FLAG_BSY2)
129 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);
130 #else
131 #define FLASH_STM32_SR_BUSY (FLASH_SR_BSY1)
132 #endif /* defined(FLASH_FLAG_BSY2) */
133 #else
134 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY)
135 #endif
136
137 #if defined(CONFIG_SOC_SERIES_STM32G0X)
138 #define FLASH_STM32_SR_CFGBSY (FLASH_SR_CFGBSY)
139 #elif defined(FLASH_FLAG_CFGBSY)
140 #define FLASH_STM32_SR_CFGBSY (FLASH_FLAG_CFGBSY)
141 #endif
142
143 #if defined(CONFIG_SOC_SERIES_STM32G0X)
144 /* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */
145 #define FLASH_STM32_SR_OPERR FLASH_SR_OPERR
146 #define FLASH_STM32_SR_PGERR 0
147 #define FLASH_STM32_SR_PROGERR FLASH_SR_PROGERR
148 #define FLASH_STM32_SR_WRPERR FLASH_SR_WRPERR
149 #define FLASH_STM32_SR_PGAERR FLASH_SR_PGAERR
150 #define FLASH_STM32_SR_SIZERR FLASH_SR_SIZERR
151 #define FLASH_STM32_SR_PGSERR FLASH_SR_PGSERR
152 #define FLASH_STM32_SR_MISERR FLASH_SR_MISERR
153 #define FLASH_STM32_SR_FASTERR FLASH_SR_FASTERR
154 #if defined(FLASH_SR_RDERR)
155 #define FLASH_STM32_SR_RDERR FLASH_SR_RDERR
156 #else
157 #define FLASH_STM32_SR_RDERR 0
158 #endif
159 #define FLASH_STM32_SR_PGPERR 0
160
161 #else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
162 #if defined(FLASH_FLAG_OPERR)
163 #define FLASH_STM32_SR_OPERR FLASH_FLAG_OPERR
164 #else
165 #define FLASH_STM32_SR_OPERR 0
166 #endif
167
168 #if defined(FLASH_FLAG_PGERR)
169 #define FLASH_STM32_SR_PGERR FLASH_FLAG_PGERR
170 #else
171 #define FLASH_STM32_SR_PGERR 0
172 #endif
173
174 #if defined(FLASH_FLAG_PROGERR)
175 #define FLASH_STM32_SR_PROGERR FLASH_FLAG_PROGERR
176 #else
177 #define FLASH_STM32_SR_PROGERR 0
178 #endif
179
180 #if defined(FLASH_FLAG_WRPERR)
181 #define FLASH_STM32_SR_WRPERR FLASH_FLAG_WRPERR
182 #else
183 #define FLASH_STM32_SR_WRPERR 0
184 #endif
185
186 #if defined(FLASH_FLAG_PGAERR)
187 #define FLASH_STM32_SR_PGAERR FLASH_FLAG_PGAERR
188 #else
189 #define FLASH_STM32_SR_PGAERR 0
190 #endif
191
192 #if defined(FLASH_FLAG_SIZERR)
193 #define FLASH_STM32_SR_SIZERR FLASH_FLAG_SIZERR
194 #else
195 #define FLASH_STM32_SR_SIZERR 0
196 #endif
197
198 #if defined(FLASH_FLAG_PGSERR)
199 #define FLASH_STM32_SR_PGSERR FLASH_FLAG_PGSERR
200 #else
201 #define FLASH_STM32_SR_PGSERR 0
202 #endif
203
204 #if defined(FLASH_FLAG_MISERR)
205 #define FLASH_STM32_SR_MISERR FLASH_FLAG_MISERR
206 #else
207 #define FLASH_STM32_SR_MISERR 0
208 #endif
209
210 #if defined(FLASH_FLAG_FASTERR)
211 #define FLASH_STM32_SR_FASTERR FLASH_FLAG_FASTERR
212 #else
213 #define FLASH_STM32_SR_FASTERR 0
214 #endif
215
216 #if defined(FLASH_FLAG_RDERR)
217 #define FLASH_STM32_SR_RDERR FLASH_FLAG_RDERR
218 #else
219 #define FLASH_STM32_SR_RDERR 0
220 #endif
221
222 #if defined(FLASH_FLAG_PGPERR)
223 #define FLASH_STM32_SR_PGPERR FLASH_FLAG_PGPERR
224 #else
225 #define FLASH_STM32_SR_PGPERR 0
226 #endif
227
228 #endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
229
230 #define FLASH_STM32_SR_ERRORS (FLASH_STM32_SR_OPERR | \
231 FLASH_STM32_SR_PGERR | \
232 FLASH_STM32_SR_PROGERR | \
233 FLASH_STM32_SR_WRPERR | \
234 FLASH_STM32_SR_PGAERR | \
235 FLASH_STM32_SR_SIZERR | \
236 FLASH_STM32_SR_PGSERR | \
237 FLASH_STM32_SR_MISERR | \
238 FLASH_STM32_SR_FASTERR | \
239 FLASH_STM32_SR_RDERR | \
240 FLASH_STM32_SR_PGPERR)
241
242 #define FLASH_STM32_RDP0 0xAA
243 #define FLASH_STM32_RDP2 0xCC
244 #define FLASH_STM32_RDP1 \
245 DT_PROP(DT_INST(0, st_stm32_flash_controller), st_rdp1_enable_byte)
246
247 #if FLASH_STM32_RDP1 == FLASH_STM32_RDP0 || FLASH_STM32_RDP1 == FLASH_STM32_RDP2
248 #error RDP1 byte has to be different than RDP0 and RDP2 byte
249 #endif
250
251 #ifdef CONFIG_FLASH_PAGE_LAYOUT
flash_stm32_range_exists(const struct device * dev,off_t offset,uint32_t len)252 static inline bool flash_stm32_range_exists(const struct device *dev,
253 off_t offset,
254 uint32_t len)
255 {
256 struct flash_pages_info info;
257
258 return !(flash_get_page_info_by_offs(dev, offset, &info) ||
259 flash_get_page_info_by_offs(dev, offset + len - 1, &info));
260 }
261 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
262
flash_stm32_valid_write(off_t offset,uint32_t len)263 static inline bool flash_stm32_valid_write(off_t offset, uint32_t len)
264 {
265 return ((offset % FLASH_STM32_WRITE_BLOCK_SIZE == 0) &&
266 (len % FLASH_STM32_WRITE_BLOCK_SIZE == 0U));
267 }
268
269 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
270 uint32_t len, bool write);
271
272 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
273 const void *data, unsigned int len);
274
275 int flash_stm32_block_erase_loop(const struct device *dev,
276 unsigned int offset,
277 unsigned int len);
278
279 int flash_stm32_wait_flash_idle(const struct device *dev);
280
281 int flash_stm32_option_bytes_lock(const struct device *dev, bool enable);
282
283 #ifdef CONFIG_SOC_SERIES_STM32WBX
284 int flash_stm32_check_status(const struct device *dev);
285 #endif /* CONFIG_SOC_SERIES_STM32WBX */
286
287 #ifdef CONFIG_FLASH_PAGE_LAYOUT
288 void flash_stm32_page_layout(const struct device *dev,
289 const struct flash_pages_layout **layout,
290 size_t *layout_size);
291 #endif
292
293 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
294
295 int flash_stm32_update_wp_sectors(const struct device *dev,
296 uint32_t changed_sectors,
297 uint32_t protected_sectors);
298
299 int flash_stm32_get_wp_sectors(const struct device *dev,
300 uint32_t *protected_sectors);
301 #endif
302 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
303
304 int flash_stm32_update_rdp(const struct device *dev, bool enable,
305 bool permanent);
306
307 int flash_stm32_get_rdp(const struct device *dev, bool *enabled,
308 bool *permanent);
309 #endif
310
311 /* Flash extended operations */
312 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
313 int flash_stm32_ex_op_sector_wp(const struct device *dev, const uintptr_t in,
314 void *out);
315 #endif
316 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
317 int flash_stm32_ex_op_rdp(const struct device *dev, const uintptr_t in,
318 void *out);
319 #endif
320
321 #endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
322
