1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_FLASH.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_FLASH 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_FLASH_H_) /* Check if memory map has not been already included */ 58 #define S32K344_FLASH_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLASH Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLASH - Size of Registers Arrays */ 72 #define FLASH_UM_COUNT 9u 73 #define FLASH_DATA_COUNT 32u 74 75 /** FLASH - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ 78 __IO uint32_t MCRS; /**< Module Configuration Status, offset: 0x4 */ 79 __I uint32_t MCRE; /**< Extended Module Configuration, offset: 0x8 */ 80 __IO uint32_t CTL; /**< Module Control, offset: 0xC */ 81 __IO uint32_t ADR; /**< Address, offset: 0x10 */ 82 __I uint32_t PEADR; /**< Program and Erase Address, offset: 0x14 */ 83 uint8_t RESERVED_0[56]; 84 __I uint32_t SPELOCK; /**< Sector Program and Erase Hardware Lock, offset: 0x50 */ 85 __I uint32_t SSPELOCK; /**< Super Sector Program and Erase Hardware Lock, offset: 0x54 */ 86 uint8_t RESERVED_1[24]; 87 __I uint32_t XSPELOCK; /**< Express Sector Program and Erase Hardware Lock, offset: 0x70 */ 88 __I uint32_t XSSPELOCK; /**< Express Super Sector Program and Erase Hardware Lock, offset: 0x74 */ 89 uint8_t RESERVED_2[24]; 90 __IO uint32_t TMD; /**< Test Mode Disable Password Check, offset: 0x90 */ 91 __IO uint32_t UT0; /**< UTest 0, offset: 0x94 */ 92 __IO uint32_t UM[FLASH_UM_COUNT]; /**< UMISRn, array offset: 0x98, array step: 0x4 */ 93 __IO uint32_t UM9; /**< UMISR9, offset: 0xBC */ 94 uint8_t RESERVED_3[16]; 95 __IO uint32_t UD0; /**< UTest Data 0, offset: 0xD0 */ 96 __IO uint32_t UD1; /**< UTest Data 1, offset: 0xD4 */ 97 __IO uint32_t UD2; /**< UTest Data 2, offset: 0xD8 */ 98 __IO uint32_t UD3; /**< UTest Data 3, offset: 0xDC */ 99 __IO uint32_t UD4; /**< UTest Data 4, offset: 0xE0 */ 100 __IO uint32_t UD5; /**< UTest Data 5, offset: 0xE4 */ 101 __IO uint32_t UA0; /**< UTest Address 0, offset: 0xE8 */ 102 __IO uint32_t UA1; /**< UTest Address 1, offset: 0xEC */ 103 __IO uint32_t XMCR; /**< Express Module Configuration, offset: 0xF0 */ 104 __I uint32_t XPEADR; /**< Express Program Address, offset: 0xF4 */ 105 uint8_t RESERVED_4[8]; 106 __IO uint32_t DATA[FLASH_DATA_COUNT]; /**< Program Data, array offset: 0x100, array step: 0x4 */ 107 } FLASH_Type, *FLASH_MemMapPtr; 108 109 /** Number of instances of the FLASH module. */ 110 #define FLASH_INSTANCE_COUNT (1u) 111 112 /* FLASH - Peripheral instance base addresses */ 113 /** Peripheral FLASH base address */ 114 #define IP_FLASH_BASE (0x402EC000u) 115 /** Peripheral FLASH base pointer */ 116 #define IP_FLASH ((FLASH_Type *)IP_FLASH_BASE) 117 /** Array initializer of FLASH peripheral base addresses */ 118 #define IP_FLASH_BASE_ADDRS { IP_FLASH_BASE } 119 /** Array initializer of FLASH peripheral base pointers */ 120 #define IP_FLASH_BASE_PTRS { IP_FLASH } 121 122 /* ---------------------------------------------------------------------------- 123 -- FLASH Register Masks 124 ---------------------------------------------------------------------------- */ 125 126 /*! 127 * @addtogroup FLASH_Register_Masks FLASH Register Masks 128 * @{ 129 */ 130 131 /*! @name MCR - Module Configuration */ 132 /*! @{ */ 133 134 #define FLASH_MCR_EHV_MASK (0x1U) 135 #define FLASH_MCR_EHV_SHIFT (0U) 136 #define FLASH_MCR_EHV_WIDTH (1U) 137 #define FLASH_MCR_EHV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_EHV_SHIFT)) & FLASH_MCR_EHV_MASK) 138 139 #define FLASH_MCR_ERS_MASK (0x10U) 140 #define FLASH_MCR_ERS_SHIFT (4U) 141 #define FLASH_MCR_ERS_WIDTH (1U) 142 #define FLASH_MCR_ERS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_ERS_SHIFT)) & FLASH_MCR_ERS_MASK) 143 144 #define FLASH_MCR_ESS_MASK (0x20U) 145 #define FLASH_MCR_ESS_SHIFT (5U) 146 #define FLASH_MCR_ESS_WIDTH (1U) 147 #define FLASH_MCR_ESS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_ESS_SHIFT)) & FLASH_MCR_ESS_MASK) 148 149 #define FLASH_MCR_PGM_MASK (0x100U) 150 #define FLASH_MCR_PGM_SHIFT (8U) 151 #define FLASH_MCR_PGM_WIDTH (1U) 152 #define FLASH_MCR_PGM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_PGM_SHIFT)) & FLASH_MCR_PGM_MASK) 153 154 #define FLASH_MCR_WDIE_MASK (0x1000U) 155 #define FLASH_MCR_WDIE_SHIFT (12U) 156 #define FLASH_MCR_WDIE_WIDTH (1U) 157 #define FLASH_MCR_WDIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_WDIE_SHIFT)) & FLASH_MCR_WDIE_MASK) 158 159 #define FLASH_MCR_PECIE_MASK (0x8000U) 160 #define FLASH_MCR_PECIE_SHIFT (15U) 161 #define FLASH_MCR_PECIE_WIDTH (1U) 162 #define FLASH_MCR_PECIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_PECIE_SHIFT)) & FLASH_MCR_PECIE_MASK) 163 164 #define FLASH_MCR_PEID_MASK (0xFF0000U) 165 #define FLASH_MCR_PEID_SHIFT (16U) 166 #define FLASH_MCR_PEID_WIDTH (8U) 167 #define FLASH_MCR_PEID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCR_PEID_SHIFT)) & FLASH_MCR_PEID_MASK) 168 /*! @} */ 169 170 /*! @name MCRS - Module Configuration Status */ 171 /*! @{ */ 172 173 #define FLASH_MCRS_RE_MASK (0x1U) 174 #define FLASH_MCRS_RE_SHIFT (0U) 175 #define FLASH_MCRS_RE_WIDTH (1U) 176 #define FLASH_MCRS_RE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_RE_SHIFT)) & FLASH_MCRS_RE_MASK) 177 178 #define FLASH_MCRS_TSPELOCK_MASK (0x100U) 179 #define FLASH_MCRS_TSPELOCK_SHIFT (8U) 180 #define FLASH_MCRS_TSPELOCK_WIDTH (1U) 181 #define FLASH_MCRS_TSPELOCK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_TSPELOCK_SHIFT)) & FLASH_MCRS_TSPELOCK_MASK) 182 183 #define FLASH_MCRS_EPEG_MASK (0x200U) 184 #define FLASH_MCRS_EPEG_SHIFT (9U) 185 #define FLASH_MCRS_EPEG_WIDTH (1U) 186 #define FLASH_MCRS_EPEG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_EPEG_SHIFT)) & FLASH_MCRS_EPEG_MASK) 187 188 #define FLASH_MCRS_WDI_MASK (0x1000U) 189 #define FLASH_MCRS_WDI_SHIFT (12U) 190 #define FLASH_MCRS_WDI_WIDTH (1U) 191 #define FLASH_MCRS_WDI(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_WDI_SHIFT)) & FLASH_MCRS_WDI_MASK) 192 193 #define FLASH_MCRS_PEG_MASK (0x4000U) 194 #define FLASH_MCRS_PEG_SHIFT (14U) 195 #define FLASH_MCRS_PEG_WIDTH (1U) 196 #define FLASH_MCRS_PEG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_PEG_SHIFT)) & FLASH_MCRS_PEG_MASK) 197 198 #define FLASH_MCRS_DONE_MASK (0x8000U) 199 #define FLASH_MCRS_DONE_SHIFT (15U) 200 #define FLASH_MCRS_DONE_WIDTH (1U) 201 #define FLASH_MCRS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_DONE_SHIFT)) & FLASH_MCRS_DONE_MASK) 202 203 #define FLASH_MCRS_PES_MASK (0x10000U) 204 #define FLASH_MCRS_PES_SHIFT (16U) 205 #define FLASH_MCRS_PES_WIDTH (1U) 206 #define FLASH_MCRS_PES(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_PES_SHIFT)) & FLASH_MCRS_PES_MASK) 207 208 #define FLASH_MCRS_PEP_MASK (0x20000U) 209 #define FLASH_MCRS_PEP_SHIFT (17U) 210 #define FLASH_MCRS_PEP_WIDTH (1U) 211 #define FLASH_MCRS_PEP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_PEP_SHIFT)) & FLASH_MCRS_PEP_MASK) 212 213 #define FLASH_MCRS_RWE_MASK (0x100000U) 214 #define FLASH_MCRS_RWE_SHIFT (20U) 215 #define FLASH_MCRS_RWE_WIDTH (1U) 216 #define FLASH_MCRS_RWE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_RWE_SHIFT)) & FLASH_MCRS_RWE_MASK) 217 218 #define FLASH_MCRS_RRE_MASK (0x1000000U) 219 #define FLASH_MCRS_RRE_SHIFT (24U) 220 #define FLASH_MCRS_RRE_WIDTH (1U) 221 #define FLASH_MCRS_RRE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_RRE_SHIFT)) & FLASH_MCRS_RRE_MASK) 222 223 #define FLASH_MCRS_RVE_MASK (0x2000000U) 224 #define FLASH_MCRS_RVE_SHIFT (25U) 225 #define FLASH_MCRS_RVE_WIDTH (1U) 226 #define FLASH_MCRS_RVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_RVE_SHIFT)) & FLASH_MCRS_RVE_MASK) 227 228 #define FLASH_MCRS_EEE_MASK (0x10000000U) 229 #define FLASH_MCRS_EEE_SHIFT (28U) 230 #define FLASH_MCRS_EEE_WIDTH (1U) 231 #define FLASH_MCRS_EEE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_EEE_SHIFT)) & FLASH_MCRS_EEE_MASK) 232 233 #define FLASH_MCRS_AEE_MASK (0x20000000U) 234 #define FLASH_MCRS_AEE_SHIFT (29U) 235 #define FLASH_MCRS_AEE_WIDTH (1U) 236 #define FLASH_MCRS_AEE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_AEE_SHIFT)) & FLASH_MCRS_AEE_MASK) 237 238 #define FLASH_MCRS_SBC_MASK (0x40000000U) 239 #define FLASH_MCRS_SBC_SHIFT (30U) 240 #define FLASH_MCRS_SBC_WIDTH (1U) 241 #define FLASH_MCRS_SBC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_SBC_SHIFT)) & FLASH_MCRS_SBC_MASK) 242 243 #define FLASH_MCRS_EER_MASK (0x80000000U) 244 #define FLASH_MCRS_EER_SHIFT (31U) 245 #define FLASH_MCRS_EER_WIDTH (1U) 246 #define FLASH_MCRS_EER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRS_EER_SHIFT)) & FLASH_MCRS_EER_MASK) 247 /*! @} */ 248 249 /*! @name MCRE - Extended Module Configuration */ 250 /*! @{ */ 251 252 #define FLASH_MCRE_n256K_MASK (0xC0U) 253 #define FLASH_MCRE_n256K_SHIFT (6U) 254 #define FLASH_MCRE_n256K_WIDTH (2U) 255 #define FLASH_MCRE_n256K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRE_n256K_SHIFT)) & FLASH_MCRE_n256K_MASK) 256 257 #define FLASH_MCRE_n512K_MASK (0xC000U) 258 #define FLASH_MCRE_n512K_SHIFT (14U) 259 #define FLASH_MCRE_n512K_WIDTH (2U) 260 #define FLASH_MCRE_n512K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRE_n512K_SHIFT)) & FLASH_MCRE_n512K_MASK) 261 262 #define FLASH_MCRE_n1M_MASK (0xE00000U) 263 #define FLASH_MCRE_n1M_SHIFT (21U) 264 #define FLASH_MCRE_n1M_WIDTH (3U) 265 #define FLASH_MCRE_n1M(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCRE_n1M_SHIFT)) & FLASH_MCRE_n1M_MASK) 266 /*! @} */ 267 268 /*! @name CTL - Module Control */ 269 /*! @{ */ 270 271 #define FLASH_CTL_RWSC_MASK (0x1F00U) 272 #define FLASH_CTL_RWSC_SHIFT (8U) 273 #define FLASH_CTL_RWSC_WIDTH (5U) 274 #define FLASH_CTL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTL_RWSC_SHIFT)) & FLASH_CTL_RWSC_MASK) 275 276 #define FLASH_CTL_RWSL_MASK (0x8000U) 277 #define FLASH_CTL_RWSL_SHIFT (15U) 278 #define FLASH_CTL_RWSL_WIDTH (1U) 279 #define FLASH_CTL_RWSL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTL_RWSL_SHIFT)) & FLASH_CTL_RWSL_MASK) 280 /*! @} */ 281 282 /*! @name ADR - Address */ 283 /*! @{ */ 284 285 #define FLASH_ADR_ADDR_MASK (0x7FFFEU) 286 #define FLASH_ADR_ADDR_SHIFT (1U) 287 #define FLASH_ADR_ADDR_WIDTH (18U) 288 #define FLASH_ADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_ADDR_SHIFT)) & FLASH_ADR_ADDR_MASK) 289 290 #define FLASH_ADR_A0_MASK (0x80000U) 291 #define FLASH_ADR_A0_SHIFT (19U) 292 #define FLASH_ADR_A0_WIDTH (1U) 293 #define FLASH_ADR_A0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_A0_SHIFT)) & FLASH_ADR_A0_MASK) 294 295 #define FLASH_ADR_A1_MASK (0x100000U) 296 #define FLASH_ADR_A1_SHIFT (20U) 297 #define FLASH_ADR_A1_WIDTH (1U) 298 #define FLASH_ADR_A1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_A1_SHIFT)) & FLASH_ADR_A1_MASK) 299 300 #define FLASH_ADR_A2_MASK (0x200000U) 301 #define FLASH_ADR_A2_SHIFT (21U) 302 #define FLASH_ADR_A2_WIDTH (1U) 303 #define FLASH_ADR_A2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_A2_SHIFT)) & FLASH_ADR_A2_MASK) 304 305 #define FLASH_ADR_A3_MASK (0x400000U) 306 #define FLASH_ADR_A3_SHIFT (22U) 307 #define FLASH_ADR_A3_WIDTH (1U) 308 #define FLASH_ADR_A3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_A3_SHIFT)) & FLASH_ADR_A3_MASK) 309 310 #define FLASH_ADR_A4_MASK (0x800000U) 311 #define FLASH_ADR_A4_SHIFT (23U) 312 #define FLASH_ADR_A4_WIDTH (1U) 313 #define FLASH_ADR_A4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_A4_SHIFT)) & FLASH_ADR_A4_MASK) 314 315 #define FLASH_ADR_A5_MASK (0x1000000U) 316 #define FLASH_ADR_A5_SHIFT (24U) 317 #define FLASH_ADR_A5_WIDTH (1U) 318 #define FLASH_ADR_A5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_A5_SHIFT)) & FLASH_ADR_A5_MASK) 319 320 #define FLASH_ADR_SAD_MASK (0x80000000U) 321 #define FLASH_ADR_SAD_SHIFT (31U) 322 #define FLASH_ADR_SAD_WIDTH (1U) 323 #define FLASH_ADR_SAD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADR_SAD_SHIFT)) & FLASH_ADR_SAD_MASK) 324 /*! @} */ 325 326 /*! @name PEADR - Program and Erase Address */ 327 /*! @{ */ 328 329 #define FLASH_PEADR_PEADDR_MASK (0x7FFE0U) 330 #define FLASH_PEADR_PEADDR_SHIFT (5U) 331 #define FLASH_PEADR_PEADDR_WIDTH (14U) 332 #define FLASH_PEADR_PEADDR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEADDR_SHIFT)) & FLASH_PEADR_PEADDR_MASK) 333 334 #define FLASH_PEADR_PEA0_MASK (0x80000U) 335 #define FLASH_PEADR_PEA0_SHIFT (19U) 336 #define FLASH_PEADR_PEA0_WIDTH (1U) 337 #define FLASH_PEADR_PEA0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEA0_SHIFT)) & FLASH_PEADR_PEA0_MASK) 338 339 #define FLASH_PEADR_PEA1_MASK (0x100000U) 340 #define FLASH_PEADR_PEA1_SHIFT (20U) 341 #define FLASH_PEADR_PEA1_WIDTH (1U) 342 #define FLASH_PEADR_PEA1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEA1_SHIFT)) & FLASH_PEADR_PEA1_MASK) 343 344 #define FLASH_PEADR_PEA2_MASK (0x200000U) 345 #define FLASH_PEADR_PEA2_SHIFT (21U) 346 #define FLASH_PEADR_PEA2_WIDTH (1U) 347 #define FLASH_PEADR_PEA2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEA2_SHIFT)) & FLASH_PEADR_PEA2_MASK) 348 349 #define FLASH_PEADR_PEA3_MASK (0x400000U) 350 #define FLASH_PEADR_PEA3_SHIFT (22U) 351 #define FLASH_PEADR_PEA3_WIDTH (1U) 352 #define FLASH_PEADR_PEA3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEA3_SHIFT)) & FLASH_PEADR_PEA3_MASK) 353 354 #define FLASH_PEADR_PEA4_MASK (0x800000U) 355 #define FLASH_PEADR_PEA4_SHIFT (23U) 356 #define FLASH_PEADR_PEA4_WIDTH (1U) 357 #define FLASH_PEADR_PEA4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEA4_SHIFT)) & FLASH_PEADR_PEA4_MASK) 358 359 #define FLASH_PEADR_PEA5_MASK (0x1000000U) 360 #define FLASH_PEADR_PEA5_SHIFT (24U) 361 #define FLASH_PEADR_PEA5_WIDTH (1U) 362 #define FLASH_PEADR_PEA5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEA5_SHIFT)) & FLASH_PEADR_PEA5_MASK) 363 364 #define FLASH_PEADR_PEASAD_MASK (0x80000000U) 365 #define FLASH_PEADR_PEASAD_SHIFT (31U) 366 #define FLASH_PEADR_PEASAD_WIDTH (1U) 367 #define FLASH_PEADR_PEASAD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_PEADR_PEASAD_SHIFT)) & FLASH_PEADR_PEASAD_MASK) 368 /*! @} */ 369 370 /*! @name SPELOCK - Sector Program and Erase Hardware Lock */ 371 /*! @{ */ 372 373 #define FLASH_SPELOCK_SPELOCK_MASK (0xFFFFFFFFU) 374 #define FLASH_SPELOCK_SPELOCK_SHIFT (0U) 375 #define FLASH_SPELOCK_SPELOCK_WIDTH (32U) 376 #define FLASH_SPELOCK_SPELOCK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_SPELOCK_SPELOCK_SHIFT)) & FLASH_SPELOCK_SPELOCK_MASK) 377 /*! @} */ 378 379 /*! @name SSPELOCK - Super Sector Program and Erase Hardware Lock */ 380 /*! @{ */ 381 382 #define FLASH_SSPELOCK_SSPELOCK_MASK (0xFFFU) 383 #define FLASH_SSPELOCK_SSPELOCK_SHIFT (0U) 384 #define FLASH_SSPELOCK_SSPELOCK_WIDTH (12U) 385 #define FLASH_SSPELOCK_SSPELOCK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_SSPELOCK_SSPELOCK_SHIFT)) & FLASH_SSPELOCK_SSPELOCK_MASK) 386 /*! @} */ 387 388 /*! @name XSPELOCK - Express Sector Program and Erase Hardware Lock */ 389 /*! @{ */ 390 391 #define FLASH_XSPELOCK_XSPELOCK_MASK (0xFFFFFFFFU) 392 #define FLASH_XSPELOCK_XSPELOCK_SHIFT (0U) 393 #define FLASH_XSPELOCK_XSPELOCK_WIDTH (32U) 394 #define FLASH_XSPELOCK_XSPELOCK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XSPELOCK_XSPELOCK_SHIFT)) & FLASH_XSPELOCK_XSPELOCK_MASK) 395 /*! @} */ 396 397 /*! @name XSSPELOCK - Express Super Sector Program and Erase Hardware Lock */ 398 /*! @{ */ 399 400 #define FLASH_XSSPELOCK_XSSPELOCK_MASK (0xFFFU) 401 #define FLASH_XSSPELOCK_XSSPELOCK_SHIFT (0U) 402 #define FLASH_XSSPELOCK_XSSPELOCK_WIDTH (12U) 403 #define FLASH_XSSPELOCK_XSSPELOCK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XSSPELOCK_XSSPELOCK_SHIFT)) & FLASH_XSSPELOCK_XSSPELOCK_MASK) 404 /*! @} */ 405 406 /*! @name TMD - Test Mode Disable Password Check */ 407 /*! @{ */ 408 409 #define FLASH_TMD_PWD_MASK (0xFFFFFFFFU) 410 #define FLASH_TMD_PWD_SHIFT (0U) 411 #define FLASH_TMD_PWD_WIDTH (32U) 412 #define FLASH_TMD_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_TMD_PWD_SHIFT)) & FLASH_TMD_PWD_MASK) 413 /*! @} */ 414 415 /*! @name UT0 - UTest 0 */ 416 /*! @{ */ 417 418 #define FLASH_UT0_AID_MASK (0x1U) 419 #define FLASH_UT0_AID_SHIFT (0U) 420 #define FLASH_UT0_AID_WIDTH (1U) 421 #define FLASH_UT0_AID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_AID_SHIFT)) & FLASH_UT0_AID_MASK) 422 423 #define FLASH_UT0_AIE_MASK (0x2U) 424 #define FLASH_UT0_AIE_SHIFT (1U) 425 #define FLASH_UT0_AIE_WIDTH (1U) 426 #define FLASH_UT0_AIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_AIE_SHIFT)) & FLASH_UT0_AIE_MASK) 427 428 #define FLASH_UT0_AIS_MASK (0x4U) 429 #define FLASH_UT0_AIS_SHIFT (2U) 430 #define FLASH_UT0_AIS_WIDTH (1U) 431 #define FLASH_UT0_AIS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_AIS_SHIFT)) & FLASH_UT0_AIS_MASK) 432 433 #define FLASH_UT0_MRV_MASK (0x10U) 434 #define FLASH_UT0_MRV_SHIFT (4U) 435 #define FLASH_UT0_MRV_WIDTH (1U) 436 #define FLASH_UT0_MRV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_MRV_SHIFT)) & FLASH_UT0_MRV_MASK) 437 438 #define FLASH_UT0_MRE_MASK (0x20U) 439 #define FLASH_UT0_MRE_SHIFT (5U) 440 #define FLASH_UT0_MRE_WIDTH (1U) 441 #define FLASH_UT0_MRE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_MRE_SHIFT)) & FLASH_UT0_MRE_MASK) 442 443 #define FLASH_UT0_AISUS_MASK (0x40U) 444 #define FLASH_UT0_AISUS_SHIFT (6U) 445 #define FLASH_UT0_AISUS_WIDTH (1U) 446 #define FLASH_UT0_AISUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_AISUS_SHIFT)) & FLASH_UT0_AISUS_MASK) 447 448 #define FLASH_UT0_AIBPE_MASK (0x100U) 449 #define FLASH_UT0_AIBPE_SHIFT (8U) 450 #define FLASH_UT0_AIBPE_WIDTH (1U) 451 #define FLASH_UT0_AIBPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_AIBPE_SHIFT)) & FLASH_UT0_AIBPE_MASK) 452 453 #define FLASH_UT0_NAIBP_MASK (0x200U) 454 #define FLASH_UT0_NAIBP_SHIFT (9U) 455 #define FLASH_UT0_NAIBP_WIDTH (1U) 456 #define FLASH_UT0_NAIBP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_NAIBP_SHIFT)) & FLASH_UT0_NAIBP_MASK) 457 458 #define FLASH_UT0_EIE_MASK (0x1000U) 459 #define FLASH_UT0_EIE_SHIFT (12U) 460 #define FLASH_UT0_EIE_WIDTH (1U) 461 #define FLASH_UT0_EIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_EIE_SHIFT)) & FLASH_UT0_EIE_MASK) 462 463 #define FLASH_UT0_EDIE_MASK (0x2000U) 464 #define FLASH_UT0_EDIE_SHIFT (13U) 465 #define FLASH_UT0_EDIE_WIDTH (1U) 466 #define FLASH_UT0_EDIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_EDIE_SHIFT)) & FLASH_UT0_EDIE_MASK) 467 468 #define FLASH_UT0_AEIE_MASK (0x4000U) 469 #define FLASH_UT0_AEIE_SHIFT (14U) 470 #define FLASH_UT0_AEIE_WIDTH (1U) 471 #define FLASH_UT0_AEIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_AEIE_SHIFT)) & FLASH_UT0_AEIE_MASK) 472 473 #define FLASH_UT0_RRIE_MASK (0x8000U) 474 #define FLASH_UT0_RRIE_SHIFT (15U) 475 #define FLASH_UT0_RRIE_WIDTH (1U) 476 #define FLASH_UT0_RRIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_RRIE_SHIFT)) & FLASH_UT0_RRIE_MASK) 477 478 #define FLASH_UT0_SBCE_MASK (0x40000000U) 479 #define FLASH_UT0_SBCE_SHIFT (30U) 480 #define FLASH_UT0_SBCE_WIDTH (1U) 481 #define FLASH_UT0_SBCE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_SBCE_SHIFT)) & FLASH_UT0_SBCE_MASK) 482 483 #define FLASH_UT0_UTE_MASK (0x80000000U) 484 #define FLASH_UT0_UTE_SHIFT (31U) 485 #define FLASH_UT0_UTE_WIDTH (1U) 486 #define FLASH_UT0_UTE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UT0_UTE_SHIFT)) & FLASH_UT0_UTE_MASK) 487 /*! @} */ 488 489 /*! @name UM - UMISRn */ 490 /*! @{ */ 491 492 #define FLASH_UM_MISR_MASK (0xFFFFFFFFU) 493 #define FLASH_UM_MISR_SHIFT (0U) 494 #define FLASH_UM_MISR_WIDTH (32U) 495 #define FLASH_UM_MISR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UM_MISR_SHIFT)) & FLASH_UM_MISR_MASK) 496 /*! @} */ 497 498 /*! @name UM9 - UMISR9 */ 499 /*! @{ */ 500 501 #define FLASH_UM9_MISR_MASK (0x1U) 502 #define FLASH_UM9_MISR_SHIFT (0U) 503 #define FLASH_UM9_MISR_WIDTH (1U) 504 #define FLASH_UM9_MISR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UM9_MISR_SHIFT)) & FLASH_UM9_MISR_MASK) 505 /*! @} */ 506 507 /*! @name UD0 - UTest Data 0 */ 508 /*! @{ */ 509 510 #define FLASH_UD0_EDATA_MASK (0xFFFFFFFFU) 511 #define FLASH_UD0_EDATA_SHIFT (0U) 512 #define FLASH_UD0_EDATA_WIDTH (32U) 513 #define FLASH_UD0_EDATA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD0_EDATA_SHIFT)) & FLASH_UD0_EDATA_MASK) 514 /*! @} */ 515 516 /*! @name UD1 - UTest Data 1 */ 517 /*! @{ */ 518 519 #define FLASH_UD1_EDATA_MASK (0xFFFFFFFFU) 520 #define FLASH_UD1_EDATA_SHIFT (0U) 521 #define FLASH_UD1_EDATA_WIDTH (32U) 522 #define FLASH_UD1_EDATA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD1_EDATA_SHIFT)) & FLASH_UD1_EDATA_MASK) 523 /*! @} */ 524 525 /*! @name UD2 - UTest Data 2 */ 526 /*! @{ */ 527 528 #define FLASH_UD2_EDATAC_MASK (0xFFU) 529 #define FLASH_UD2_EDATAC_SHIFT (0U) 530 #define FLASH_UD2_EDATAC_WIDTH (8U) 531 #define FLASH_UD2_EDATAC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD2_EDATAC_SHIFT)) & FLASH_UD2_EDATAC_MASK) 532 533 #define FLASH_UD2_ED0_MASK (0x1000000U) 534 #define FLASH_UD2_ED0_SHIFT (24U) 535 #define FLASH_UD2_ED0_WIDTH (1U) 536 #define FLASH_UD2_ED0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD2_ED0_SHIFT)) & FLASH_UD2_ED0_MASK) 537 538 #define FLASH_UD2_ED1_MASK (0x2000000U) 539 #define FLASH_UD2_ED1_SHIFT (25U) 540 #define FLASH_UD2_ED1_WIDTH (1U) 541 #define FLASH_UD2_ED1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD2_ED1_SHIFT)) & FLASH_UD2_ED1_MASK) 542 543 #define FLASH_UD2_ED2_MASK (0x4000000U) 544 #define FLASH_UD2_ED2_SHIFT (26U) 545 #define FLASH_UD2_ED2_WIDTH (1U) 546 #define FLASH_UD2_ED2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD2_ED2_SHIFT)) & FLASH_UD2_ED2_MASK) 547 548 #define FLASH_UD2_ED3_MASK (0x8000000U) 549 #define FLASH_UD2_ED3_SHIFT (27U) 550 #define FLASH_UD2_ED3_WIDTH (1U) 551 #define FLASH_UD2_ED3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD2_ED3_SHIFT)) & FLASH_UD2_ED3_MASK) 552 /*! @} */ 553 554 /*! @name UD3 - UTest Data 3 */ 555 /*! @{ */ 556 557 #define FLASH_UD3_EDDATA_MASK (0xFFFFFFFFU) 558 #define FLASH_UD3_EDDATA_SHIFT (0U) 559 #define FLASH_UD3_EDDATA_WIDTH (32U) 560 #define FLASH_UD3_EDDATA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD3_EDDATA_SHIFT)) & FLASH_UD3_EDDATA_MASK) 561 /*! @} */ 562 563 /*! @name UD4 - UTest Data 4 */ 564 /*! @{ */ 565 566 #define FLASH_UD4_EDDATA_MASK (0xFFFFFFFFU) 567 #define FLASH_UD4_EDDATA_SHIFT (0U) 568 #define FLASH_UD4_EDDATA_WIDTH (32U) 569 #define FLASH_UD4_EDDATA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD4_EDDATA_SHIFT)) & FLASH_UD4_EDDATA_MASK) 570 /*! @} */ 571 572 /*! @name UD5 - UTest Data 5 */ 573 /*! @{ */ 574 575 #define FLASH_UD5_EDDATAC_MASK (0xFFU) 576 #define FLASH_UD5_EDDATAC_SHIFT (0U) 577 #define FLASH_UD5_EDDATAC_WIDTH (8U) 578 #define FLASH_UD5_EDDATAC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD5_EDDATAC_SHIFT)) & FLASH_UD5_EDDATAC_MASK) 579 580 #define FLASH_UD5_EDD0_MASK (0x1000000U) 581 #define FLASH_UD5_EDD0_SHIFT (24U) 582 #define FLASH_UD5_EDD0_WIDTH (1U) 583 #define FLASH_UD5_EDD0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD5_EDD0_SHIFT)) & FLASH_UD5_EDD0_MASK) 584 585 #define FLASH_UD5_EDD1_MASK (0x2000000U) 586 #define FLASH_UD5_EDD1_SHIFT (25U) 587 #define FLASH_UD5_EDD1_WIDTH (1U) 588 #define FLASH_UD5_EDD1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD5_EDD1_SHIFT)) & FLASH_UD5_EDD1_MASK) 589 590 #define FLASH_UD5_EDD2_MASK (0x4000000U) 591 #define FLASH_UD5_EDD2_SHIFT (26U) 592 #define FLASH_UD5_EDD2_WIDTH (1U) 593 #define FLASH_UD5_EDD2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD5_EDD2_SHIFT)) & FLASH_UD5_EDD2_MASK) 594 595 #define FLASH_UD5_EDD3_MASK (0x8000000U) 596 #define FLASH_UD5_EDD3_SHIFT (27U) 597 #define FLASH_UD5_EDD3_WIDTH (1U) 598 #define FLASH_UD5_EDD3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UD5_EDD3_SHIFT)) & FLASH_UD5_EDD3_MASK) 599 /*! @} */ 600 601 /*! @name UA0 - UTest Address 0 */ 602 /*! @{ */ 603 604 #define FLASH_UA0_AEI_MASK (0xFFFFFFFFU) 605 #define FLASH_UA0_AEI_SHIFT (0U) 606 #define FLASH_UA0_AEI_WIDTH (32U) 607 #define FLASH_UA0_AEI(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UA0_AEI_SHIFT)) & FLASH_UA0_AEI_MASK) 608 /*! @} */ 609 610 /*! @name UA1 - UTest Address 1 */ 611 /*! @{ */ 612 613 #define FLASH_UA1_AEI_MASK (0xFFFFFU) 614 #define FLASH_UA1_AEI_SHIFT (0U) 615 #define FLASH_UA1_AEI_WIDTH (20U) 616 #define FLASH_UA1_AEI(x) (((uint32_t)(((uint32_t)(x)) << FLASH_UA1_AEI_SHIFT)) & FLASH_UA1_AEI_MASK) 617 /*! @} */ 618 619 /*! @name XMCR - Express Module Configuration */ 620 /*! @{ */ 621 622 #define FLASH_XMCR_XEHV_MASK (0x1U) 623 #define FLASH_XMCR_XEHV_SHIFT (0U) 624 #define FLASH_XMCR_XEHV_WIDTH (1U) 625 #define FLASH_XMCR_XEHV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XEHV_SHIFT)) & FLASH_XMCR_XEHV_MASK) 626 627 #define FLASH_XMCR_XPGM_MASK (0x100U) 628 #define FLASH_XMCR_XPGM_SHIFT (8U) 629 #define FLASH_XMCR_XPGM_WIDTH (1U) 630 #define FLASH_XMCR_XPGM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XPGM_SHIFT)) & FLASH_XMCR_XPGM_MASK) 631 632 #define FLASH_XMCR_XEPEG_MASK (0x200U) 633 #define FLASH_XMCR_XEPEG_SHIFT (9U) 634 #define FLASH_XMCR_XEPEG_WIDTH (1U) 635 #define FLASH_XMCR_XEPEG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XEPEG_SHIFT)) & FLASH_XMCR_XEPEG_MASK) 636 637 #define FLASH_XMCR_XWDIE_MASK (0x800U) 638 #define FLASH_XMCR_XWDIE_SHIFT (11U) 639 #define FLASH_XMCR_XWDIE_WIDTH (1U) 640 #define FLASH_XMCR_XWDIE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XWDIE_SHIFT)) & FLASH_XMCR_XWDIE_MASK) 641 642 #define FLASH_XMCR_XWDI_MASK (0x1000U) 643 #define FLASH_XMCR_XWDI_SHIFT (12U) 644 #define FLASH_XMCR_XWDI_WIDTH (1U) 645 #define FLASH_XMCR_XWDI(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XWDI_SHIFT)) & FLASH_XMCR_XWDI_MASK) 646 647 #define FLASH_XMCR_XDOK_MASK (0x2000U) 648 #define FLASH_XMCR_XDOK_SHIFT (13U) 649 #define FLASH_XMCR_XDOK_WIDTH (1U) 650 #define FLASH_XMCR_XDOK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XDOK_SHIFT)) & FLASH_XMCR_XDOK_MASK) 651 652 #define FLASH_XMCR_XPEG_MASK (0x4000U) 653 #define FLASH_XMCR_XPEG_SHIFT (14U) 654 #define FLASH_XMCR_XPEG_WIDTH (1U) 655 #define FLASH_XMCR_XPEG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XPEG_SHIFT)) & FLASH_XMCR_XPEG_MASK) 656 657 #define FLASH_XMCR_XDONE_MASK (0x8000U) 658 #define FLASH_XMCR_XDONE_SHIFT (15U) 659 #define FLASH_XMCR_XDONE_WIDTH (1U) 660 #define FLASH_XMCR_XDONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XDONE_SHIFT)) & FLASH_XMCR_XDONE_MASK) 661 662 #define FLASH_XMCR_XPEID_MASK (0xFF0000U) 663 #define FLASH_XMCR_XPEID_SHIFT (16U) 664 #define FLASH_XMCR_XPEID_WIDTH (8U) 665 #define FLASH_XMCR_XPEID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XMCR_XPEID_SHIFT)) & FLASH_XMCR_XPEID_MASK) 666 /*! @} */ 667 668 /*! @name XPEADR - Express Program Address */ 669 /*! @{ */ 670 671 #define FLASH_XPEADR_XPEADDR_MASK (0x7FFE0U) 672 #define FLASH_XPEADR_XPEADDR_SHIFT (5U) 673 #define FLASH_XPEADR_XPEADDR_WIDTH (14U) 674 #define FLASH_XPEADR_XPEADDR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEADDR_SHIFT)) & FLASH_XPEADR_XPEADDR_MASK) 675 676 #define FLASH_XPEADR_XPEA0_MASK (0x80000U) 677 #define FLASH_XPEADR_XPEA0_SHIFT (19U) 678 #define FLASH_XPEADR_XPEA0_WIDTH (1U) 679 #define FLASH_XPEADR_XPEA0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEA0_SHIFT)) & FLASH_XPEADR_XPEA0_MASK) 680 681 #define FLASH_XPEADR_XPEA1_MASK (0x100000U) 682 #define FLASH_XPEADR_XPEA1_SHIFT (20U) 683 #define FLASH_XPEADR_XPEA1_WIDTH (1U) 684 #define FLASH_XPEADR_XPEA1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEA1_SHIFT)) & FLASH_XPEADR_XPEA1_MASK) 685 686 #define FLASH_XPEADR_XPEA2_MASK (0x200000U) 687 #define FLASH_XPEADR_XPEA2_SHIFT (21U) 688 #define FLASH_XPEADR_XPEA2_WIDTH (1U) 689 #define FLASH_XPEADR_XPEA2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEA2_SHIFT)) & FLASH_XPEADR_XPEA2_MASK) 690 691 #define FLASH_XPEADR_XPEA3_MASK (0x400000U) 692 #define FLASH_XPEADR_XPEA3_SHIFT (22U) 693 #define FLASH_XPEADR_XPEA3_WIDTH (1U) 694 #define FLASH_XPEADR_XPEA3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEA3_SHIFT)) & FLASH_XPEADR_XPEA3_MASK) 695 696 #define FLASH_XPEADR_XPEA4_MASK (0x800000U) 697 #define FLASH_XPEADR_XPEA4_SHIFT (23U) 698 #define FLASH_XPEADR_XPEA4_WIDTH (1U) 699 #define FLASH_XPEADR_XPEA4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEA4_SHIFT)) & FLASH_XPEADR_XPEA4_MASK) 700 701 #define FLASH_XPEADR_XPEA5_MASK (0x1000000U) 702 #define FLASH_XPEADR_XPEA5_SHIFT (24U) 703 #define FLASH_XPEADR_XPEA5_WIDTH (1U) 704 #define FLASH_XPEADR_XPEA5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_XPEADR_XPEA5_SHIFT)) & FLASH_XPEADR_XPEA5_MASK) 705 /*! @} */ 706 707 /*! @name DATA - Program Data */ 708 /*! @{ */ 709 710 #define FLASH_DATA_PDATA_MASK (0xFFFFFFFFU) 711 #define FLASH_DATA_PDATA_SHIFT (0U) 712 #define FLASH_DATA_PDATA_WIDTH (32U) 713 #define FLASH_DATA_PDATA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATA_PDATA_SHIFT)) & FLASH_DATA_PDATA_MASK) 714 /*! @} */ 715 716 /*! 717 * @} 718 */ /* end of group FLASH_Register_Masks */ 719 720 /*! 721 * @} 722 */ /* end of group FLASH_Peripheral_Access_Layer */ 723 724 #endif /* #if !defined(S32K344_FLASH_H_) */ 725
