1 /* 2 * Copyright (c) 2023 Andes Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* Flash opcodes */ 8 #define FLASH_ANDES_CMD_WRSR 0x01 /* Write status register */ 9 #define FLASH_ANDES_CMD_RDSR 0x05 /* Read status register */ 10 #define FLASH_ANDES_CMD_READ 0x03 /* Read data */ 11 #define FLASH_ANDES_CMD_4READ 0xEB /* Quad mode Read data*/ 12 #define FLASH_ANDES_CMD_WREN 0x06 /* Write enable */ 13 #define FLASH_ANDES_CMD_WRDI 0x04 /* Write disable */ 14 #define FLASH_ANDES_CMD_PP 0x02 /* Page program */ 15 #define FLASH_ANDES_CMD_4PP 0x38 /* Quad mode page program*/ 16 #define FLASH_ANDES_CMD_SE 0x20 /* Sector erase */ 17 #define FLASH_ANDES_CMD_BE_32K 0x52 /* Block erase 32KB */ 18 #define FLASH_ANDES_CMD_BE 0xD8 /* Block erase */ 19 #define FLASH_ANDES_CMD_CE 0xC7 /* Chip erase */ 20 #define FLASH_ANDES_CMD_RDID 0x9F /* Read JEDEC ID */ 21 #define FLASH_ANDES_CMD_ULBPR 0x98 /* Global Block Protection Unlock */ 22 #define FLASH_ANDES_CMD_DPD 0xB9 /* Deep Power Down */ 23 #define FLASH_ANDES_CMD_RDPD 0xAB /* Release from Deep Power Down */ 24 25 /* Status register bits */ 26 #define FLASH_ANDES_WIP_BIT BIT(0) /* Write in progress */ 27 #define FLASH_ANDES_WEL_BIT BIT(1) /* Write enable latch */ 28 #define FLASH_ANDES_QE_BIT BIT(6) 29 30 #define QSPI_TFMAT(base) (base + 0x10) 31 #define QSPI_TCTRL(base) (base + 0x20) 32 #define QSPI_CMD(base) (base + 0x24) 33 #define QSPI_ADDR(base) (base + 0x28) 34 #define QSPI_DATA(base) (base + 0x2c) 35 #define QSPI_CTRL(base) (base + 0x30) 36 #define QSPI_STAT(base) (base + 0x34) 37 #define QSPI_INTEN(base) (base + 0x38) 38 #define QSPI_INTST(base) (base + 0x3c) 39 #define QSPI_TIMIN(base) (base + 0x40) 40 #define QSPI_CONFIG(base) (base + 0x7c) 41 42 /* Field mask of SPI transfer format register */ 43 #define TFMAT_DATA_LEN_OFFSET (8) 44 #define TFMAT_ADDR_LEN_OFFSET (16) 45 46 #define TFMAT_SLVMODE_MSK BIT(2) 47 #define TFMAT_DATA_MERGE_MSK BIT(7) 48 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8) 49 50 /* Field mask of SPI transfer control register */ 51 #define TCTRL_RD_TCNT_OFFSET (0) 52 #define TCTRL_DUMMY_CNT_OFFSET (9) 53 #define TCTRL_WR_TCNT_OFFSET (12) 54 #define TCTRL_DUAL_MODE_OFFSET (22) 55 #define TCTRL_TRNS_MODE_OFFSET (24) 56 57 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24) 58 #define TCTRL_ADDR_FMT_MSK BIT(28) 59 #define TCTRL_ADDR_EN_MSK BIT(29) 60 #define TCTRL_CMD_EN_MSK BIT(30) 61 62 /* Transfer mode */ 63 #define TRNS_MODE_WRITE_READ (0 << TCTRL_TRNS_MODE_OFFSET) 64 #define TRNS_MODE_WRITE_ONLY (1 << TCTRL_TRNS_MODE_OFFSET) 65 #define TRNS_MODE_READ_ONLY (2 << TCTRL_TRNS_MODE_OFFSET) 66 #define TRNS_MODE_NONE_DATA (7 << TCTRL_TRNS_MODE_OFFSET) 67 #define TRNS_MODE_DUMMY_READ (9 << TCTRL_TRNS_MODE_OFFSET) 68 69 /* Dual/Qual mode */ 70 #define DUAL_IO_MODE (2 << TCTRL_DUAL_MODE_OFFSET) 71 72 /* Dummy count */ 73 /* In Qual mode, dummy count 3 implies 6 dummy cycles */ 74 #define DUMMY_CNT_3 (0x2 << TCTRL_DUMMY_CNT_OFFSET) 75 76 /* Field mask of SPI interrupt enable register */ 77 #define IEN_RX_FIFO_MSK BIT(2) 78 #define IEN_TX_FIFO_MSK BIT(3) 79 #define IEN_END_MSK BIT(4) 80 81 /* Field mask of SPI interrupt status register */ 82 #define INTST_RX_FIFO_INT_MSK BIT(2) 83 #define INTST_TX_FIFO_INT_MSK BIT(3) 84 #define INTST_END_INT_MSK BIT(4) 85 86 /* Field mask of SPI config register */ 87 #define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0) 88 #define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4) 89 90 /* Field mask of SPI status register */ 91 #define STAT_RX_NUM_MSK GENMASK(13, 8) 92 #define STAT_TX_NUM_MSK GENMASK(21, 16) 93 94 /* Field mask of SPI control register */ 95 #define CTRL_RX_THRES_OFFSET (8) 96 #define CTRL_TX_THRES_OFFSET (16) 97 98 #define CTRL_RX_THRES_MSK GENMASK(15, 8) 99 #define CTRL_TX_THRES_MSK GENMASK(23, 16) 100 101 /* Field mask of SPI status register */ 102 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0) 103 104 #define TX_FIFO_THRESHOLD (1 << CTRL_TX_THRES_OFFSET) 105 #define RX_FIFO_THRESHOLD (1 << CTRL_RX_THRES_OFFSET) 106 #define MAX_TRANSFER_CNT (512) 107 108 #define TX_FIFO_SIZE_SETTING(base) \ 109 (sys_read32(QSPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK) 110 #define TX_FIFO_SIZE(base) \ 111 (2 << (TX_FIFO_SIZE_SETTING(base) >> 4)) 112 113 #define RX_FIFO_SIZE_SETTING(base) \ 114 (sys_read32(QSPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK) 115 #define RX_FIFO_SIZE(base) \ 116 (2 << (RX_FIFO_SIZE_SETTING(base) >> 0)) 117 118 #define TX_NUM_STAT(base) (sys_read32(QSPI_STAT(base)) & STAT_TX_NUM_MSK) 119 #define RX_NUM_STAT(base) (sys_read32(QSPI_STAT(base)) & STAT_RX_NUM_MSK) 120 #define GET_TX_NUM(base) (TX_NUM_STAT(base) >> 16) 121 #define GET_RX_NUM(base) (RX_NUM_STAT(base) >> 8) 122
