1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright (c) 2023 Intel Corporation 4 * 5 * Author: Adrian Warecki <adrian.warecki@intel.com> 6 */ 7 8 #ifndef __INTEL_DAI_DRIVER_DMIC_REGS_H__ 9 #define __INTEL_DAI_DRIVER_DMIC_REGS_H__ 10 11 /* DMIC timestamping registers */ 12 #define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000 13 #define TS_DMIC_LOCAL_OFFS_OFFSET 0x004 14 #define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008 15 #define TS_DMIC_LOCAL_WALCLK_OFFSET 0x010 16 #define TS_DMIC_TSCC_OFFSET 0x018 17 18 /* Timestamping */ 19 #define TIMESTAMP_BASE 0x00071800 20 21 /* Time Stamp Control Register */ 22 #define TS_DMIC_LOCAL_TSCTRL (TIMESTAMP_BASE + TS_DMIC_LOCAL_TSCTRL_OFFSET) 23 24 /* Intersample offset Register */ 25 #define TS_DMIC_LOCAL_OFFS (TIMESTAMP_BASE + TS_DMIC_LOCAL_OFFS_OFFSET) 26 27 #define TS_DMIC_LOCAL_SAMPLE (TIMESTAMP_BASE + TS_DMIC_LOCAL_SAMPLE_OFFSET) 28 #define TS_DMIC_LOCAL_WALCLK (TIMESTAMP_BASE + TS_DMIC_LOCAL_WALCLK_OFFSET) 29 30 /* Time Stamp Counter Captured 64 bits */ 31 #define TS_DMIC_TSCC (TIMESTAMP_BASE + TS_DMIC_TSCC_OFFSET) 32 33 /* New Timestamp Taken */ 34 #define TS_LOCAL_TSCTRL_NTK BIT(31) 35 36 /* Interrupt on New Timestamp Enable */ 37 #define TS_LOCAL_TSCTRL_IONTE BIT(30) 38 39 /* DMA Type Select */ 40 #define TS_LOCAL_TSCTRL_DMATS GENMASK(13, 12) 41 42 /* Capture Link Select - select which link wall clock to time stamp. */ 43 #define TS_LOCAL_TSCTRL_CLNKS GENMASK(11, 10) 44 45 /* Hammock Harbor Time Stamp Enable */ 46 #define TS_LOCAL_TSCTRL_HHTSE BIT(7) 47 48 /* Link Wall Clock Select */ 49 #define TS_LOCAL_TSCTRL_LWCS BIT(6) 50 51 /* On Demand Time Stamp */ 52 #define TS_LOCAL_TSCTRL_ODTS BIT(5) 53 54 /* Capture DMA Select */ 55 #define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0) 56 57 /* Snapshot of Audio Wall Clock Offset counter (frame offset). */ 58 #define TS_LOCAL_OFFS_FRM GENMASK(15, 12) 59 60 /* Snapshot of Audio Wall Clock Offset counter (clock offset). */ 61 #define TS_LOCAL_OFFS_CLK GENMASK(11, 0) 62 63 64 /* DMIC register offsets */ 65 66 /* Global registers */ 67 68 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF) 69 * PDM Primary Channel 70 */ 71 72 /* Control registers for packers */ 73 #define OUTCONTROL 0x0000 74 75 /* Status Register for FIFO interface */ 76 #define OUTSTAT 0x0004 77 78 /* Data read/Write port for FIFO */ 79 #define OUTDATA 0x0008 80 81 /* (crossed out) 000Ch LOCAL_OFFS Offset Counter 82 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp 83 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count 84 * 001Ch - 00FFh Reserved space for extensions 85 */ 86 87 /* Offset to PDM Secondary Channel */ 88 #define PDM_CHANNEL_REGS_SIZE 0x100 89 90 91 #define GLOBAL_CAPABILITIES 0x200 92 93 #define PDM_COEFFICIENT_A 0x400 94 #define PDM_COEF_RAM_A_LENGTH 0x400 95 96 #define PDM_COEFFICIENT_B 0x800 97 #define PDM_COEF_RAM_B_LENGTH 0x400 98 99 #define PDM0 0x1000 100 #define PDM1 0x2000 101 #define PDM2 0x3000 102 #define PDM3 0x4000 103 104 105 /* Local registers in each PDMx */ 106 107 /* Control register for CIC configuration and decimator setting */ 108 #define CIC_CONTROL 0x000 109 110 /* Control of the CIC filter plus voice channel (B) FIR decimation factor */ 111 #define CIC_CONFIG 0x004 112 113 /* Microphone interface control register */ 114 #define MIC_CONTROL 0x00c 115 116 /* FIR config */ 117 118 /* Control for the FIR decimator */ 119 #define FIR_CONTROL 0x020 120 121 /* Configuration of FIR decimator parameters */ 122 #define FIR_CONFIG 0x024 123 124 /* DC offset for left channel */ 125 #define DC_OFFSET_LEFT 0x028 126 127 /* DC offset for right channel */ 128 #define DC_OFFSET_RIGHT 0x02c 129 130 /* Gain for left channel */ 131 #define OUT_GAIN_LEFT 0x030 132 133 /* Gain for right channel */ 134 #define OUT_GAIN_RIGHT 0x034 135 136 /* Offset to secondary FIR */ 137 #define FIR_CHANNEL_REGS_SIZE 0x20 138 139 140 /* Digital Mic Shim Registers */ 141 142 /* Digital Microphone Link Control */ 143 #define DMICLCTL 0x04 144 145 /* Digital Microphone IP Pointer */ 146 #define DMICIPPTR 0x08 147 148 149 /* OUTCONTROL0 and OUTCONTROL1 */ 150 151 /* OUTCONTROLx IPM bit fields style */ 152 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */ 153 154 /* Threshold Interrupt Enable */ 155 #define OUTCONTROL_TIE BIT(27) 156 157 /* Start Input Packer */ 158 #define OUTCONTROL_SIP BIT(26) 159 160 /* FIFO Initialize (FINIT): The software will set this bit to immediately clear FIFO pointers. */ 161 #define OUTCONTROL_FINIT BIT(25) 162 163 /* Input Format Change Indicator */ 164 #define OUTCONTROL_FCI BIT(24) 165 166 /* Burst FIFO Threshold */ 167 #define OUTCONTROL_BFTH GENMASK(23, 20) 168 169 /* Output Format */ 170 #define OUTCONTROL_OF GENMASK(19, 18) 171 172 173 /* This field decides the packer mode */ 174 #define OUTCONTROL_IPM GENMASK(17, 15) 175 176 /* Source decimator for 1st stereo/mono data placeholder. */ 177 #define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13) 178 179 /* Source decimator for 2nd stereo/mono data placeholder. */ 180 #define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11) 181 182 /* Source decimator for 3rd stereo/mono data placeholder. */ 183 #define OUTCONTROL_IPM_SOURCE_3 GENMASK(10, 9) 184 185 /* Source decimator for 4th stereo/mono data placeholder. */ 186 #define OUTCONTROL_IPM_SOURCE_4 GENMASK(8, 7) 187 188 /* Defines the mode of operation for all source decimator. */ 189 #define OUTCONTROL_IPM_SOURCE_MODE BIT(6) 190 191 /* FIFO Trigger Threshold */ 192 #define OUTCONTROL_TH GENMASK(5, 0) 193 194 195 /* OUTSTAT0 and OUTSTAT1 bits */ 196 197 /* Asynchronous FIFO is empty */ 198 #define OUTSTAT_AFE BIT(31) 199 200 /* Asynchronous FIFO Not Empty */ 201 #define OUTSTAT_ASNE BIT(29) 202 203 /* FIFO Service Request */ 204 #define OUTSTAT_RFS BIT(28) 205 206 /* Overrun */ 207 #define OUTSTAT_ROR BIT(27) 208 209 /* FIFO Level (FL): Current FIFO Level in the Asynchronous FIFO. */ 210 #define OUTSTAT_FL_MASK GENMASK(8, 0) 211 212 /* CIC_CONTROL bits */ 213 214 /* Microphone interface reset. */ 215 #define CIC_CONTROL_SOFT_RESET BIT(16) 216 217 /* When set to 1, the CIC channel B (right) is started, otherwise it is muted and idle. */ 218 #define CIC_CONTROL_CIC_START_B BIT(15) 219 220 /* When set to 1, the CIC channel A (left) is started, otherwise it is muted and idle. */ 221 #define CIC_CONTROL_CIC_START_A BIT(14) 222 223 /* Polarity of the microphone output. */ 224 #define CIC_CONTROL_MIC_B_POLARITY BIT(3) 225 226 /* Polarity of the microphone output. */ 227 #define CIC_CONTROL_MIC_A_POLARITY BIT(2) 228 229 /* Mute currently active microphones */ 230 #define CIC_CONTROL_MIC_MUTE BIT(1) 231 232 233 /* CIC_CONFIG masks */ 234 235 /* Number of bits for shift right in the output stage of the CIC filter to compensate the gain 236 * accumulated due to decimation. 237 */ 238 #define CIC_CONFIG_CIC_SHIFT GENMASK(27, 24) 239 240 /* Period of activation of comb section in the microphone clocks minus 1 */ 241 #define CIC_CONFIG_COMB_COUNT GENMASK(15, 8) 242 243 244 /* MIC_CONTROL */ 245 246 /* Clock divider used for producing the microphone clock from audio IO clock with approximately 50% 247 * duty cycle. 248 */ 249 #define MIC_CONTROL_PDM_CLKDIV GENMASK(15, 8) 250 251 /* Inverts the clock edge that will be used to sample microphone data stream. */ 252 #define MIC_CONTROL_CLK_EDGE BIT(3) 253 254 /* Indicates the PDM DMIC clock for the decimator will be sourced from external component instead 255 * of using the PDM DMIC clock generator output 256 */ 257 #define MIC_CONTROL_SLAVE_MODE BIT(2) 258 259 /* Enable clock on microphone B (Right) */ 260 #define MIC_CONTROL_PDM_EN_B BIT(1) 261 262 /* Enable clock on microphone A (left) */ 263 #define MIC_CONTROL_PDM_EN_A BIT(0) 264 265 266 /* FIR_CONTROL_A bits */ 267 268 /* Enable the power gating capability of the coefficient. */ 269 #define FIR_CONTROL_CRFPGE BIT(28) 270 271 /* Power gating capability of the left channel */ 272 #define FIR_CONTROL_LDRFPGE BIT(29) 273 274 /* Enable the power gating capability of the right channel */ 275 #define FIR_CONTROL_RDRFPGE BIT(30) 276 277 /* FIR decimation filter is started. */ 278 #define FIR_CONTROL_START BIT(7) 279 280 /* Array microphone control bit for synchronous start of multiple interfaces. */ 281 #define FIR_CONTROL_ARRAY_START_EN BIT(6) 282 283 /* Periodic synchronous start control of multiple PDM */ 284 #define FIR_CONTROL_PERIODIC_START_EN BIT(5) 285 286 /* Automatic DC compensation enable */ 287 #define FIR_CONTROL_DCCOMP BIT(4) 288 289 /* Write in the coefficient memory will mute the output for the N audio clocks */ 290 #define FIR_CONTROL_AUTO_MUTE BIT(2) 291 292 /* Mute outputs of this filter and set it to zero. */ 293 #define FIR_CONTROL_MUTE BIT(1) 294 295 /* Filter operates in stereo mode */ 296 #define FIR_CONTROL_STEREO BIT(0) 297 298 299 /* FIR_CONFIG bits */ 300 301 /* Decimation factor of the FIR filter minus 1. */ 302 #define FIR_CONFIG_FIR_DECIMATION GENMASK(20, 16) 303 304 /* Number of bits for shift right in the output stage of the CIC filter to compensate the gain 305 * accumulated due to decimation. 306 */ 307 #define FIR_CONFIG_FIR_SHIFT GENMASK(11, 8) 308 309 /* The number of active taps of the FIR filter minus 1. */ 310 #define FIR_CONFIG_FIR_LENGTH GENMASK(7, 0) 311 312 313 /* DC_OFFSET_LEFT and DC_OFFSET_RIGHT */ 314 315 /* Value added to the output of the FIR filter. */ 316 #define DC_OFFSET_DC_OFFS GENMASK(21, 0) 317 318 319 /* OUT_GAIN_LEFT and OUT_GAIN_RIGHT */ 320 321 /* Value added to the output of the FIR filter. */ 322 #define OUT_GAIN GENMASK(19, 0) 323 324 /* FIR coefficients */ 325 #define FIR_COEF GENMASK(19, 0) 326 327 328 /* GLOBAL_CAPABILITIES */ 329 330 /* Nnumber of data entries supported in the PCM XCLK FIFO per FIR output. */ 331 #define GLOBAL_CAP_PCM_XCLK_FIFO_DEPTH GENMASK(5, 0) 332 333 /* Port Count */ 334 #define GLOBAL_CAP_PORT_COUNT GENMASK(7, 6) 335 336 /* FIR Count */ 337 #define GLOBAL_CAP_FIR_COUNT BIT(8) 338 339 /* FIR max gain configuration. */ 340 #define GLOBAL_CAP_FIR_MAX_GAIN BIT(9) 341 342 /* FIR A RF Depth */ 343 #define GLOBAL_CAP_FIR_A_RF_DEPTH GENMASK(23, 16) 344 345 /* FIR B RF Depth */ 346 #define GLOBAL_CAP_FIR_B_RF_DEPTH GENMASK(31, 24) 347 348 349 /* Digital Mic Shim Registers */ 350 #ifdef CONFIG_SOC_INTEL_ACE20_LNL 351 #include <ace20_lnl/dmic_regs_ace2x.h> 352 #elif CONFIG_SOC_INTEL_ACE15_MTPM 353 #include <ace15_mtpm/dmic_regs_ace1x.h> 354 #elif CONFIG_SOC_INTEL_ACE30_PTL 355 #include <ace30_ptl/dmic_regs_ace3x.h> 356 #else 357 #error "Unknown SoC" 358 #endif 359 360 #endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_H__ */ 361
