1 /* 2 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 19 #define ARM_ROTPK_HEADER_LEN 19 20 #define ARM_ROTPK_HASH_LEN 32 21 22 /* Special value used to verify platform parameters from BL2 to BL31 */ 23 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 24 25 /* PL011 UART related constants */ 26 #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ 27 #undef V2M_IOFPGA_UART0_CLK_IN_HZ 28 #endif 29 30 #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ 31 #undef V2M_IOFPGA_UART1_CLK_IN_HZ 32 #endif 33 34 #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 35 #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 36 37 /* Core/Cluster/Thread counts for corstone1000 */ 38 #define CORSTONE1000_CLUSTER_COUNT U(1) 39 #define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4) 40 #define CORSTONE1000_MAX_PE_PER_CPU U(1) 41 #define CORSTONE1000_PRIMARY_CPU U(0) 42 43 #define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT 44 45 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 46 CORSTONE1000_MAX_CPUS_PER_CLUSTER * \ 47 CORSTONE1000_MAX_PE_PER_CPU) 48 49 /* UART related constants */ 50 #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 51 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 52 #define PLAT_ARM_RUN_UART_BASE 0x1a520000 53 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 54 #define ARM_CONSOLE_BAUDRATE 115200 55 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 56 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 57 58 /* Memory related constants */ 59 60 /* SRAM (CVM) memory layout 61 * 62 * <ARM_TRUSTED_SRAM_BASE> 63 * partition size: sizeof(meminfo_t) = 16 bytes 64 * content: memory info area used by the next BL 65 * 66 * <ARM_FW_CONFIG_BASE> 67 * partition size: 4080 bytes 68 * 69 * <ARM_BL2_MEM_DESC_BASE> 70 * partition size: 4 KB 71 * content: Area where BL2 copies the images descriptors 72 * 73 * <ARM_BL_RAM_BASE> = <BL32_BASE> 74 * partition size: 688 KB 75 * content: BL32 (optee-os) 76 * 77 * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000 78 * partition size: 8 KB 79 * content: BL32 config (TOS_FW_CONFIG) 80 * 81 * <BL31_BASE> 82 * partition size: 140 KB 83 * content: BL31 84 * 85 * <BL2_SIGNATURE_BASE> 86 * partition size: 4 KB 87 * content: MCUBOOT data needed to verify TF-A BL2 88 * 89 * <BL2_BASE> 90 * partition size: 176 KB 91 * content: BL2 92 * 93 * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB 94 * partition size: 512 KB 95 * content: BL33 (u-boot) 96 */ 97 98 /* DDR memory */ 99 #define ARM_DRAM1_BASE UL(0x80000000) 100 #define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/ 101 #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1) 102 103 /* DRAM1 and DRAM2 are the same for corstone1000 */ 104 #define ARM_DRAM2_BASE ARM_DRAM1_BASE 105 #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE 106 #define ARM_DRAM2_END ARM_DRAM1_END 107 108 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 109 #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE 110 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1) 111 112 /* The first 8 KB of Trusted SRAM are used as shared memory */ 113 #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) 114 #define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */ 115 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 116 117 /* The remaining Trusted SRAM is used to load the BL images */ 118 #define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ 119 120 /* Last 512KB of CVM is allocated for shared RAM as an example openAMP */ 121 #define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K) 122 123 #define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ 124 ARM_NS_SHARED_RAM_SIZE - \ 125 ARM_SHARED_RAM_SIZE) 126 127 #define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ 128 129 #define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */ 130 131 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) 132 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 133 ARM_SHARED_RAM_SIZE) 134 135 #define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */ 136 137 #define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE) 138 #define BL2_BASE (BL2_LIMIT - \ 139 PLAT_ARM_MAX_BL2_SIZE + \ 140 BL2_SIGNATURE_SIZE) 141 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 142 143 #define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE) 144 #define BL31_LIMIT BL2_SIGNATURE_BASE 145 146 #define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ 147 CORSTONE1000_TOS_FW_CONFIG_SIZE) 148 #define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */ 149 #define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE 150 151 #define BL32_BASE ARM_BL_RAM_BASE 152 #define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE) 153 154 #define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE) 155 156 /* SPD_spmd settings */ 157 158 #define PLAT_ARM_SPMC_BASE BL32_BASE 159 #define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE 160 161 /* NS memory */ 162 163 /* The last 512KB of the SRAM is allocated as shared memory */ 164 #define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \ 165 (PLAT_ARM_MAX_BL31_SIZE + \ 166 PLAT_ARM_MAX_BL32_SIZE)) 167 168 #define BL33_BASE ARM_DRAM1_BASE 169 #define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ 170 #define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) 171 172 /* end of the definition of SRAM memory layout */ 173 174 /* NOR Flash */ 175 176 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 177 #define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ 178 #define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ 179 #define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000) 180 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE 181 #define PLAT_ARM_FIP_OFFSET_IN_GPT (0x86000) 182 183 /* FIP Information */ 184 #define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */ 185 186 /* 187 * Some data must be aligned on the biggest cache line size in the platform. 188 * This is known only to the platform as it might have a combination of 189 * integrated and external caches. 190 */ 191 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 192 #define ARM_CACHE_WRITEBACK_SHIFT 6 193 194 /* 195 * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. 196 * FW_CONFIG is intended to host the device tree. Currently, This area is not 197 * used because corstone1000 platform doesn't use a device tree at TF-A level. 198 */ 199 #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t)) 200 #define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \ 201 (ARM_SHARED_RAM_SIZE >> 1)) 202 203 /* 204 * Boot parameters passed from BL2 to BL31/BL32 are stored here 205 */ 206 #define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT 207 #define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE 208 209 /* 210 * The max number of regions like RO(code), coherent and data required by 211 * different BL stages which need to be mapped in the MMU. 212 */ 213 #define ARM_BL_REGIONS 3 214 #define PLAT_ARM_MMAP_ENTRIES 8 215 #define MAX_XLAT_TABLES 5 216 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) 217 #define MAX_IO_DEVICES 2 218 #define MAX_IO_HANDLES 3 219 #define MAX_IO_BLOCK_DEVICES 1 220 221 /* GIC related constants */ 222 #define PLAT_ARM_GICD_BASE 0x1C010000 223 #define PLAT_ARM_GICC_BASE 0x1C02F000 224 225 /* MHUv2 Secure Channel receiver and sender */ 226 #define PLAT_SDK700_MHU0_SEND 0x1B800000 227 #define PLAT_SDK700_MHU0_RECV 0x1B810000 228 229 /* Timer/watchdog related constants */ 230 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) 231 #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) 232 #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) 233 234 #define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000 235 #define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008 236 #define SECURE_WATCHDOG_MASK_ENABLE 0x01 237 #define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000 238 239 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ 240 241 #define CORSTONE1000_IRQ_TZ_WDOG 32 242 #define CORSTONE1000_IRQ_SEC_SYS_TIMER 34 243 244 #define PLAT_MAX_PWR_LVL 2 245 /* 246 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 247 * power levels have a 1:1 mapping with the MPIDR affinity levels. 248 */ 249 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 250 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 251 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 252 253 /* 254 * Macros for local power states in ARM platforms encoded by State-ID field 255 * within the power-state parameter. 256 */ 257 /* Local power state for power domains in Run state. */ 258 #define ARM_LOCAL_STATE_RUN U(0) 259 /* Local power state for retention. Valid only for CPU power domains */ 260 #define ARM_LOCAL_STATE_RET U(1) 261 /* Local power state for OFF/power-down. Valid for CPU and cluster 262 * power domains 263 */ 264 #define ARM_LOCAL_STATE_OFF U(2) 265 266 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 267 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 268 269 #define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) 270 271 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 272 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 273 274 /* 275 * This macro defines the deepest retention state possible. A higher state 276 * ID will represent an invalid or a power down state. 277 */ 278 #define PLAT_MAX_RET_STATE 1 279 280 /* 281 * This macro defines the deepest power down states possible. Any state ID 282 * higher than this is invalid. 283 */ 284 #define PLAT_MAX_OFF_STATE 2 285 286 #define PLATFORM_STACK_SIZE UL(0x440) 287 288 #define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \ 289 PLAT_ARM_NVM_BASE, \ 290 PLAT_ARM_NVM_SIZE, \ 291 MT_DEVICE | MT_RO | MT_SECURE) 292 293 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 294 ARM_SHARED_RAM_BASE, \ 295 ARM_SHARED_RAM_SIZE, \ 296 MT_MEMORY | MT_RW | MT_SECURE) 297 298 #define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ 299 ARM_NS_SHARED_RAM_BASE, \ 300 ARM_NS_SHARED_RAM_SIZE, \ 301 MT_MEMORY | MT_RW | MT_NS) 302 303 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 304 ARM_NS_DRAM1_BASE, \ 305 ARM_NS_DRAM1_SIZE, \ 306 MT_MEMORY | MT_RW | MT_NS) 307 308 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 309 BL_CODE_BASE, \ 310 (BL_CODE_END - BL_CODE_BASE), \ 311 MT_CODE | MT_SECURE), \ 312 MAP_REGION_FLAT( \ 313 BL_RO_DATA_BASE, \ 314 (BL_RO_DATA_END - BL_RO_DATA_BASE), \ 315 MT_RO_DATA | MT_SECURE) 316 #if USE_COHERENT_MEM 317 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 318 BL_COHERENT_RAM_BASE, \ 319 (BL_COHERENT_RAM_END \ 320 - BL_COHERENT_RAM_BASE), \ 321 MT_DEVICE | MT_RW | MT_SECURE) 322 #endif 323 324 /* 325 * Map the region for the optional device tree configuration with read and 326 * write permissions 327 */ 328 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ 329 ARM_FW_CONFIG_BASE, \ 330 (ARM_FW_CONFIG_LIMIT \ 331 - ARM_FW_CONFIG_BASE), \ 332 MT_MEMORY | MT_RW | MT_SECURE) 333 334 #define CORSTONE1000_DEVICE_BASE (0x1A000000) 335 #define CORSTONE1000_DEVICE_SIZE (0x26000000) 336 #define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \ 337 CORSTONE1000_DEVICE_BASE, \ 338 CORSTONE1000_DEVICE_SIZE, \ 339 MT_DEVICE | MT_RW | MT_SECURE) 340 341 #define ARM_IRQ_SEC_PHY_TIMER 29 342 343 #define ARM_IRQ_SEC_SGI_0 8 344 #define ARM_IRQ_SEC_SGI_1 9 345 #define ARM_IRQ_SEC_SGI_2 10 346 #define ARM_IRQ_SEC_SGI_3 11 347 #define ARM_IRQ_SEC_SGI_4 12 348 #define ARM_IRQ_SEC_SGI_5 13 349 #define ARM_IRQ_SEC_SGI_6 14 350 #define ARM_IRQ_SEC_SGI_7 15 351 352 /* 353 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 354 * terminology. On a GICv2 system or mode, the lists will be merged and treated 355 * as Group 0 interrupts. 356 */ 357 #define ARM_G1S_IRQ_PROPS(grp) \ 358 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 359 (grp), GIC_INTR_CFG_LEVEL), \ 360 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 361 (grp), GIC_INTR_CFG_EDGE), \ 362 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 363 (grp), GIC_INTR_CFG_EDGE), \ 364 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 365 (grp), GIC_INTR_CFG_EDGE), \ 366 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 367 (grp), GIC_INTR_CFG_EDGE), \ 368 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 369 (grp), GIC_INTR_CFG_EDGE), \ 370 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 371 (grp), GIC_INTR_CFG_EDGE) 372 373 #define ARM_G0_IRQ_PROPS(grp) \ 374 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 375 GIC_INTR_CFG_EDGE) 376 377 /* 378 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 379 * terminology. On a GICv2 system or mode, the lists will be merged and treated 380 * as Group 0 interrupts. 381 */ 382 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 383 ARM_G1S_IRQ_PROPS(grp), \ 384 INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \ 385 GIC_HIGHEST_SEC_PRIORITY, \ 386 (grp), GIC_INTR_CFG_LEVEL), \ 387 INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \ 388 GIC_HIGHEST_SEC_PRIORITY, \ 389 (grp), GIC_INTR_CFG_LEVEL) 390 391 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 392 393 #endif /* PLATFORM_DEF_H */ 394
