1 /* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_ICM42688_REG_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_ICM42688_REG_H_ 9 10 #include <zephyr/sys/util.h> 11 12 /* Address value has a read bit */ 13 #define REG_SPI_READ_BIT BIT(7) 14 15 /* Common bank select register and values */ 16 #define REG_BANK_SEL 0x76 17 #define MASK_BANK_SEL GENMASK(2, 0) 18 #define BIT_BANK0 0x000 19 #define BIT_BANK1 0x001 20 #define BIT_BANK2 0x010 21 #define BIT_BANK3 0x011 22 #define BIT_BANK4 0x100 23 24 /* Helper macros for addressing registers in the 4 register banks 25 * registers are defined as 16 bit values with the bank in the high 26 * byte and the register address in the low byte 27 */ 28 29 #define REG_ADDRESS_MASK GENMASK(7, 0) 30 #define REG_BANK_MASK GENMASK(15, 8) 31 #define REG_BANK_OFFSET(bank) (bank << 8) 32 #define REG_BANK0_OFFSET REG_BANK_OFFSET(BIT_BANK0) 33 #define REG_BANK1_OFFSET REG_BANK_OFFSET(BIT_BANK1) 34 #define REG_BANK2_OFFSET REG_BANK_OFFSET(BIT_BANK2) 35 #define REG_BANK3_OFFSET REG_BANK_OFFSET(BIT_BANK3) 36 #define REG_BANK4_OFFSET REG_BANK_OFFSET(BIT_BANK4) 37 38 /* Bank 0 */ 39 #define REG_DEVICE_CONFIG (REG_BANK0_OFFSET | 0x11) 40 #define REG_DRIVE_CONFIG (REG_BANK0_OFFSET | 0x13) 41 #define REG_INT_CONFIG (REG_BANK0_OFFSET | 0x14) 42 #define REG_FIFO_CONFIG (REG_BANK0_OFFSET | 0x16) 43 #define REG_TEMP_DATA1 (REG_BANK0_OFFSET | 0x1D) 44 #define REG_TEMP_DATA0 (REG_BANK0_OFFSET | 0x1E) 45 #define REG_ACCEL_DATA_X1 (REG_BANK0_OFFSET | 0x1F) 46 #define REG_ACCEL_DATA_X0 (REG_BANK0_OFFSET | 0x20) 47 #define REG_ACCEL_DATA_Y1 (REG_BANK0_OFFSET | 0x21) 48 #define REG_ACCEL_DATA_Y0 (REG_BANK0_OFFSET | 0x22) 49 #define REG_ACCEL_DATA_Z1 (REG_BANK0_OFFSET | 0x23) 50 #define REG_ACCEL_DATA_Z0 (REG_BANK0_OFFSET | 0x24) 51 #define REG_GYRO_DATA_X1 (REG_BANK0_OFFSET | 0x25) 52 #define REG_GYRO_DATA_X0 (REG_BANK0_OFFSET | 0x26) 53 #define REG_GYRO_DATA_Y1 (REG_BANK0_OFFSET | 0x27) 54 #define REG_GYRO_DATA_Y0 (REG_BANK0_OFFSET | 0x28) 55 #define REG_GYRO_DATA_Z1 (REG_BANK0_OFFSET | 0x29) 56 #define REG_GYRO_DATA_Z0 (REG_BANK0_OFFSET | 0x2A) 57 #define REG_TMST_FSYNCH (REG_BANK0_OFFSET | 0x2B) 58 #define REG_TMST_FSYNCL (REG_BANK0_OFFSET | 0x2C) 59 #define REG_INT_STATUS (REG_BANK0_OFFSET | 0x2D) 60 #define REG_FIFO_COUNTH (REG_BANK0_OFFSET | 0x2E) 61 #define REG_FIFO_COUNTL (REG_BANK0_OFFSET | 0x2F) 62 #define REG_FIFO_DATA (REG_BANK0_OFFSET | 0x30) 63 #define REG_APEX_DATA0 (REG_BANK0_OFFSET | 0x31) 64 #define REG_APEX_DATA1 (REG_BANK0_OFFSET | 0x32) 65 #define REG_APEX_DATA2 (REG_BANK0_OFFSET | 0x33) 66 #define REG_APEX_DATA3 (REG_BANK0_OFFSET | 0x34) 67 #define REG_APEX_DATA4 (REG_BANK0_OFFSET | 0x35) 68 #define REG_APEX_DATA5 (REG_BANK0_OFFSET | 0x36) 69 #define REG_INT_STATUS2 (REG_BANK0_OFFSET | 0x37) 70 #define REG_INT_STATUS3 (REG_BANK0_OFFSET | 0x38) 71 #define REG_SIGNAL_PATH_RESET (REG_BANK0_OFFSET | 0x4B) 72 #define REG_INTF_CONFIG0 (REG_BANK0_OFFSET | 0x4C) 73 #define REG_INTF_CONFIG1 (REG_BANK0_OFFSET | 0x4D) 74 #define REG_PWR_MGMT0 (REG_BANK0_OFFSET | 0x4E) 75 #define REG_GYRO_CONFIG0 (REG_BANK0_OFFSET | 0x4F) 76 #define REG_ACCEL_CONFIG0 (REG_BANK0_OFFSET | 0x50) 77 #define REG_GYRO_CONFIG1 (REG_BANK0_OFFSET | 0x51) 78 #define REG_GYRO_ACCEL_CONFIG0 (REG_BANK0_OFFSET | 0x52) 79 #define REG_ACCEL_CONFIG1 (REG_BANK0_OFFSET | 0x53) 80 #define REG_TMST_CONFIG (REG_BANK0_OFFSET | 0x54) 81 #define REG_APEX_CONFIG0 (REG_BANK0_OFFSET | 0x56) 82 #define REG_SMD_CONFIG (REG_BANK0_OFFSET | 0x57) 83 #define REG_FIFO_CONFIG1 (REG_BANK0_OFFSET | 0x5F) 84 #define REG_FIFO_CONFIG2 (REG_BANK0_OFFSET | 0x60) 85 #define REG_FIFO_CONFIG3 (REG_BANK0_OFFSET | 0x61) 86 #define REG_FSYNC_CONFIG (REG_BANK0_OFFSET | 0x62) 87 #define REG_INT_CONFIG0 (REG_BANK0_OFFSET | 0x63) 88 #define REG_INT_CONFIG1 (REG_BANK0_OFFSET | 0x64) 89 #define REG_INT_SOURCE0 (REG_BANK0_OFFSET | 0x65) 90 #define REG_INT_SOURCE1 (REG_BANK0_OFFSET | 0x66) 91 #define REG_INT_SOURCE3 (REG_BANK0_OFFSET | 0x68) 92 #define REG_INT_SOURCE4 (REG_BANK0_OFFSET | 0x69) 93 #define REG_FIFO_LOST_PKT0 (REG_BANK0_OFFSET | 0x6C) 94 #define REG_FIFO_LOST_PKT1 (REG_BANK0_OFFSET | 0x6D) 95 #define REG_SELF_TEST_CONFIG (REG_BANK0_OFFSET | 0x70) 96 #define REG_WHO_AM_I (REG_BANK0_OFFSET | 0x75) 97 98 /* Bank 1 */ 99 #define SENSOR_CONFIG0 (REG_BANK1_OFFSET | 0x03) 100 #define GYRO_CONFIG_STATIC2 (REG_BANK1_OFFSET | 0x0B) 101 #define GYRO_CONFIG_STATIC3 (REG_BANK1_OFFSET | 0x0C) 102 #define GYRO_CONFIG_STATIC4 (REG_BANK1_OFFSET | 0x0D) 103 #define GYRO_CONFIG_STATIC5 (REG_BANK1_OFFSET | 0x0E) 104 #define GYRO_CONFIG_STATIC6 (REG_BANK1_OFFSET | 0x0F) 105 #define GYRO_CONFIG_STATIC7 (REG_BANK1_OFFSET | 0x10) 106 #define GYRO_CONFIG_STATIC8 (REG_BANK1_OFFSET | 0x11) 107 #define GYRO_CONFIG_STATIC9 (REG_BANK1_OFFSET | 0x12) 108 #define GYRO_CONFIG_STATIC10 (REG_BANK1_OFFSET | 0x13) 109 #define REG_XG_ST_DATA (REG_BANK1_OFFSET | 0x5F) 110 #define REG_YG_ST_DATA (REG_BANK1_OFFSET | 0x60) 111 #define REG_ZG_ST_DATA (REG_BANK1_OFFSET | 0x61) 112 #define REG_TMSTVAL0 (REG_BANK1_OFFSET | 0x62) 113 #define REG_TMSTVAL1 (REG_BANK1_OFFSET | 0x63) 114 #define REG_TMSTVAL2 (REG_BANK1_OFFSET | 0x64) 115 #define REG_INTF_CONFIG4 (REG_BANK1_OFFSET | 0x7A) 116 #define REG_INTF_CONFIG5 (REG_BANK1_OFFSET | 0x7B) 117 #define REG_INTF_CONFIG6 (REG_BANK1_OFFSET | 0x7C) 118 119 /* Bank 2 */ 120 121 /* Bank 4 */ 122 #define REG_INT_SOURCE6 (REG_BANK4_OFFSET | 0x77) 123 #define REG_INT_SOURCE7 (REG_BANK4_OFFSET | 0x78) 124 #define REG_INT_SOURCE8 (REG_BANK4_OFFSET | 0x79) 125 #define REG_INT_SOURCE9 (REG_BANK4_OFFSET | 0x80) 126 127 /* Bank0 REG_DEVICE_CONFIG */ 128 #define BIT_SOFT_RESET BIT(0) 129 #define BIT_SPI_MODE BIT(4) 130 131 /* Bank0 REG_DRIVE_CONFIG */ 132 /* Not used! */ 133 134 /* Bank0 REG_INT_CONFIG */ 135 #define BIT_INT1_POLARITY BIT(0) 136 #define BIT_INT1_DRIVE_CIRCUIT BIT(1) 137 #define BIT_INT1_MODE BIT(2) 138 #define BIT_INT2_POLARITY BIT(3) 139 #define BIT_INT2_DRIVE_CIRCUIT BIT(4) 140 #define BIT_INT2_MODE BIT(5) 141 142 /* Bank0 REG_FIFO_CONFIG */ 143 #define MASK_FIFO_MODE GENMASK(7, 6) 144 #define BIT_FIFO_MODE_BYPASS 0x00 145 #define BIT_FIFO_MODE_STREAM 0x01 146 #define BIT_FIFO_MODE_STOP_ON_FULL 0x10 147 148 /* Bank0 REG_INT_STATUS */ 149 #define BIT_INT_STATUS_AGC_RDY BIT(0) 150 #define BIT_INT_STATUS_FIFO_FULL BIT(1) 151 #define BIT_INT_STATUS_FIFO_THS BIT(2) 152 #define BIT_INT_STATUS_DATA_RDY BIT(3) 153 #define BIT_INT_STATUS_RESET_DONE BIT(4) 154 #define BIT_INT_STATUS_PLL_RDY BIT(5) 155 #define BIT_INT_STATUS_FSYNC BIT(6) 156 157 /* Bank0 REG_INT_STATUS2 */ 158 #define BIT_INT_STATUS_WOM_Z BIT(0) 159 #define BIT_INT_STATUS_WOM_Y BIT(1) 160 #define BIT_INT_STATUS_WOM_X BIT(2) 161 #define BIT_INT_STATUS_SMD BIT(3) 162 163 /* Bank0 REG_INT_STATUS3 */ 164 #define BIT_INT_STATUS_LOWG_DET BIT(1) 165 #define BIT_INT_STATUS_FF_DET BIT(2) 166 #define BIT_INT_STATUS_TILT_DET BIT(3) 167 #define BIT_INT_STATUS_STEP_CNT_OVFL BIT(4) 168 #define BIT_INT_STATUS_STEP_DET BIT(5) 169 170 /* Bank0 REG_SIGNAL_PATH_RESET */ 171 #define BIT_FIFO_FLUSH BIT(1) 172 #define BIT_TMST_STROBE BIT(2) 173 #define BIT_ABORT_AND_RESET BIT(3) 174 #define BIT_DMP_MEM_RESET_EN BIT(5) 175 #define BIT_DMP_INIT_EN BIT(6) 176 177 /* Bank0 REG_INTF_CONFIG0 */ 178 #define MASK_UI_SIFS_CFG GENMASK(1, 0) 179 #define BIT_UI_SIFS_CFG_DISABLE_SPI 0x10 180 #define BIT_UI_SIFS_CFG_DISABLE_I2C 0x11 181 #define BIT_SENSOR_DATA_ENDIAN BIT(4) 182 #define BIT_FIFO_COUNT_ENDIAN BIT(5) 183 #define BIT_FIFO_COUNT_REC BIT(6) 184 #define BIT_FIFO_HOLD_LAST_DATA_EN BIT(7) 185 186 /* Bank0 REG_INTF_CONFIG1 */ 187 #define MASK_CLKSEL GENMASK(1, 0) 188 #define BIT_CLKSEL_INT_RC 0x00 189 #define BIT_CLKSEL_PLL_OR_RC 0x01 190 #define BIT_CLKSEL_DISABLE 0x11 191 #define BIT_RTC_MODE BIT(2) 192 #define BIT_ACCEL_LP_CLK_SEL BIT(3) 193 194 /* Bank0 REG_PWR_MGMT_0 */ 195 #define MASK_ACCEL_MODE GENMASK(1, 0) 196 #define BIT_ACCEL_MODE_OFF 0x00 197 #define BIT_ACCEL_MODE_LPM 0x02 198 #define BIT_ACCEL_MODE_LNM 0x03 199 #define MASK_GYRO_MODE GENMASK(3, 2) 200 #define BIT_GYRO_MODE_OFF 0x00 201 #define BIT_GYRO_MODE_STBY 0x01 202 #define BIT_GYRO_MODE_LNM 0x03 203 #define BIT_IDLE BIT(4) 204 #define BIT_TEMP_DIS BIT(5) 205 206 /* Bank0 REG_GYRO_CONFIG0 */ 207 #define MASK_GYRO_UI_FS_SEL GENMASK(7, 5) 208 #define BIT_GYRO_UI_FS_2000 0x00 209 #define BIT_GYRO_UI_FS_1000 0x01 210 #define BIT_GYRO_UI_FS_500 0x02 211 #define BIT_GYRO_UI_FS_250 0x03 212 #define BIT_GYRO_UI_FS_125 0x04 213 #define BIT_GYRO_UI_FS_62_5 0x05 214 #define BIT_GYRO_UI_FS_31_25 0x06 215 #define BIT_GYRO_UI_FS_15_625 0x07 216 #define MASK_GYRO_ODR GENMASK(3, 0) 217 #define BIT_GYRO_ODR_32000 0x01 218 #define BIT_GYRO_ODR_16000 0x02 219 #define BIT_GYRO_ODR_8000 0x03 220 #define BIT_GYRO_ODR_4000 0x04 221 #define BIT_GYRO_ODR_2000 0x05 222 #define BIT_GYRO_ODR_1000 0x06 223 #define BIT_GYRO_ODR_200 0x07 224 #define BIT_GYRO_ODR_100 0x08 225 #define BIT_GYRO_ODR_50 0x09 226 #define BIT_GYRO_ODR_25 0x0A 227 #define BIT_GYRO_ODR_12_5 0x0B 228 #define BIT_GYRO_ODR_500 0x0F 229 230 /* Bank0 REG_ACCEL_CONFIG0 */ 231 #define MASK_ACCEL_UI_FS_SEL GENMASK(7, 5) 232 #define BIT_ACCEL_UI_FS_16 0x00 233 #define BIT_ACCEL_UI_FS_8 0x01 234 #define BIT_ACCEL_UI_FS_4 0x02 235 #define BIT_ACCEL_UI_FS_2 0x03 236 #define MASK_ACCEL_ODR GENMASK(3, 0) 237 #define BIT_ACCEL_ODR_32000 0x01 238 #define BIT_ACCEL_ODR_16000 0x02 239 #define BIT_ACCEL_ODR_8000 0x03 240 #define BIT_ACCEL_ODR_4000 0x04 241 #define BIT_ACCEL_ODR_2000 0x05 242 #define BIT_ACCEL_ODR_1000 0x06 243 #define BIT_ACCEL_ODR_200 0x07 244 #define BIT_ACCEL_ODR_100 0x08 245 #define BIT_ACCEL_ODR_50 0x09 246 #define BIT_ACCEL_ODR_25 0x0A 247 #define BIT_ACCEL_ODR_12_5 0x0B 248 #define BIT_ACCEL_ODR_6_25 0x0C 249 #define BIT_ACCEL_ODR_3_12 0x0D 250 #define BIT_ACCEL_ODR_1_5625 0x0E 251 #define BIT_ACCEL_ODR_500 0x0F 252 253 /* Bank0 FIFO_CONFIG1 */ 254 #define BIT_FIFO_WM_GT_TH BIT(5) 255 #define BIT_FIFO_HIRES_EN BIT(4) 256 #define BIT_FIFO_TMST_FSYNC_EN BIT(3) 257 #define BIT_FIFO_GYRO_EN BIT(2) 258 #define BIT_FIFO_ACCEL_EN BIT(1) 259 #define BIT_FIFO_TEMP_EN BIT(0) 260 261 /* Bank0 INT_SOURCE0 */ 262 #define BIT_UI_FSYNC_INT1_EN BIT(6) 263 #define BIT_PLL_RDY_INT1_EN BIT(5) 264 #define BIT_RESET_DONE_INT1_EN BIT(4) 265 #define BIT_UI_DRDY_INT1_EN BIT(3) 266 #define BIT_FIFO_THS_INT1_EN BIT(2) 267 #define BIT_FIFO_FULL_INT1_EN BIT(1) 268 #define BIT_FIFO_UI_AGC_RDY_INT1_EN BIT(0) 269 270 /* Bank0 REG_FSYNC_CONFIG */ 271 #define MASK_FSYNC_UI_SEL GENMASK(6, 4) 272 #define BIT_FSYNC_UI 273 274 /* Bank0 REG_INT_CONFIG1 */ 275 #define BIT_INT_TPULSE_DURATION BIT(6) 276 #define BIT_INT_TDEASSERT_DISABLE BIT(5) 277 #define BIT_INT_ASYNC_RESET BIT(4) 278 279 /* misc. defines */ 280 #define WHO_AM_I_ICM42688 0x47 281 #define MIN_ACCEL_SENS_SHIFT 11 282 #define ACCEL_DATA_SIZE 6 283 #define GYRO_DATA_SIZE 6 284 #define TEMP_DATA_SIZE 2 285 #define MCLK_POLL_INTERVAL_US 250 286 #define MCLK_POLL_ATTEMPTS 100 287 #define SOFT_RESET_TIME_MS 2 /* 1ms + elbow room */ 288 289 /* FIFO header */ 290 #define FIFO_HEADER_ACCEL BIT(6) 291 #define FIFO_HEADER_GYRO BIT(5) 292 #define FIFO_HEADER_20 BIT(4) 293 #define FIFO_HEADER_TIMESTAMP_FSYNC GENMASK(3, 2) 294 #define FIFO_HEADER_ODR_ACCEL BIT(1) 295 #define FIFO_HEADER_ODR_GYRO BIT(0) 296 297 #endif /* ZEPHYR_DRIVERS_SENSOR_ICM42688_REG_H_ */ 298
