1 /* 2 (C) Copyright 2006, 2007 3 International Business Machines Corporation, 4 Sony Computer Entertainment, Incorporated, 5 Toshiba Corporation, 6 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 * Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 * Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 * Neither the names of the copyright holders nor the names of their 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _SYS_FENV_H 34 #define _SYS_FENV_H 35 36 /* 37 * The exception macros are such that the functions to pack/unpack them 38 * will map a 32 bit fenv_t from/to the 128 bit fpscr. 39 * 40 * Suffixes: 41 * _SNGL: single precision 42 * _DBL: double precision 43 * _N: element number, no suffix for element 0. 44 */ 45 46 #define FE_OVERFLOW_SNGL 0x08000000 47 #define FE_UNDERFLOW_SNGL 0x04000000 48 #define FE_DIFF_SNGL 0x02000000 49 #define FE_DIVBYZERO_SNGL 0x00000040 50 51 #define FE_OVERFLOW_SNGL_1 0x00040000 52 #define FE_UNDERFLOW_SNGL_1 0x00020000 53 #define FE_DIFF_SNGL_1 0x00010000 54 #define FE_DIVBYZERO_SNGL_1 0x00000020 55 56 #define FE_OVERFLOW_SNGL_2 0x00000200 57 #define FE_UNDERFLOW_SNGL_2 0x00000100 58 #define FE_DIFF_SNGL_2 0x00000080 59 #define FE_DIVBYZERO_SNGL_2 0x00000010 60 61 #define FE_OVERFLOW_SNGL_3 0x00000004 62 #define FE_UNDERFLOW_SNGL_3 0x00000002 63 #define FE_DIFF_SNGL_3 0x00000001 64 #define FE_DIVBYZERO_SNGL_3 0x00000008 65 66 #define FE_ALL_EXCEPT_SNGL (FE_OVERFLOW_SNGL | FE_UNDERFLOW_SNGL \ 67 | FE_DIFF_SNGL | FE_DIVBYZERO_SNGL) 68 #define FE_ALL_EXCEPT_SNGL_1 (FE_OVERFLOW_SNGL_1 | FE_UNDERFLOW_SNGL_1 \ 69 | FE_DIFF_SNGL_1 | FE_DIVBYZERO_SNGL_1) 70 #define FE_ALL_EXCEPT_SNGL_2 (FE_OVERFLOW_SNGL_2 | FE_UNDERFLOW_SNGL_2 \ 71 | FE_DIFF_SNGL_2 | FE_DIVBYZERO_SNGL_2) 72 #define FE_ALL_EXCEPT_SNGL_3 (FE_OVERFLOW_SNGL_3 | FE_UNDERFLOW_SNGL_3 \ 73 | FE_DIFF_SNGL_3 | FE_DIVBYZERO_SNGL_3) 74 75 #define FE_OVERFLOW_DBL 0x01000000 76 #define FE_UNDERFLOW_DBL 0x00800000 77 #define FE_INEXACT_DBL 0x00400000 78 #define FE_INVALID_DBL 0x00200000 79 #define FE_NC_NAN_DBL 0x00100000 80 #define FE_NC_DENORM_DBL 0x00080000 81 82 #define FE_OVERFLOW_DBL_1 0x00008000 83 #define FE_UNDERFLOW_DBL_1 0x00004000 84 #define FE_INEXACT_DBL_1 0x00002000 85 #define FE_INVALID_DBL_1 0x00001000 86 #define FE_NC_NAN_DBL_1 0x00000800 87 #define FE_NC_DENORM_DBL_1 0x00000400 88 89 #define FE_ALL_EXCEPT_DBL (FE_OVERFLOW_DBL | FE_UNDERFLOW_DBL | \ 90 FE_INEXACT_DBL | FE_INVALID_DBL | \ 91 FE_NC_NAN_DBL | FE_NC_DENORM_DBL) 92 #define FE_ALL_EXCEPT_DBL_1 (FE_OVERFLOW_DBL_1 | FE_UNDERFLOW_DBL_1 | \ 93 FE_INEXACT_DBL_1 | FE_INVALID_DBL_1 | \ 94 FE_NC_NAN_DBL_1 | FE_NC_DENORM_DBL_1) 95 96 #define FE_ALL_EXCEPT (FE_ALL_EXCEPT_SNGL | FE_ALL_EXCEPT_SNGL_1 | \ 97 FE_ALL_EXCEPT_SNGL_2 | FE_ALL_EXCEPT_SNGL_3 | \ 98 FE_ALL_EXCEPT_DBL | FE_ALL_EXCEPT_DBL_1) 99 100 /* 101 * Warning: some of these are single and some double precision only, 102 * because of the hardware implementation. 103 */ 104 #define FE_DIVBYZERO (FE_DIVBYZERO_SNGL | FE_DIVBYZERO_SNGL_1 | \ 105 FE_DIVBYZERO_SNGL_2 | FE_DIVBYZERO_SNGL_3) 106 #define FE_INEXACT (FE_INEXACT_DBL | FE_INEXACT_DBL_1) 107 #define FE_INVALID (FE_INVALID_DBL | FE_INVALID_DBL_1) 108 #define FE_NC_NAN (FE_NC_NAN_DBL | FE_NC_NAN_DBL_1) 109 #define FE_NC_DENORM (FE_NC_DENORM_DBL | FE_NC_DENORM_DBL_1) 110 111 /* 112 * __FE_ROUND_ELE_n values are set so that they can easily be used as a 113 * mask when setting the fpscr. These tell us whether we are setting the 114 * round mode for a specific element (double precision floating point 115 * only, so there are only two elements). 116 */ 117 #define __FE_ROUND_ELE_0 0xc00 118 #define __FE_ROUND_ELE_1 0x300 119 120 /* 121 * The following map directly to round values in the fpscr. 122 */ 123 #define __FE_SPU_TONEAREST 0 124 #define __FE_SPU_TOWARDZERO 1 125 #define __FE_SPU_UPWARD 2 126 #define __FE_SPU_DOWNWARD 3 127 128 #define FE_TONEAREST (__FE_ROUND_ELE_0 | (__FE_SPU_TONEAREST << 2)) 129 #define FE_TOWARDZERO (__FE_ROUND_ELE_0 | (__FE_SPU_TOWARDZERO << 2)) 130 #define FE_UPWARD (__FE_ROUND_ELE_0 | (__FE_SPU_UPWARD << 2)) 131 #define FE_DOWNWARD (__FE_ROUND_ELE_0 | (__FE_SPU_DOWNWARD << 2)) 132 133 #define FE_TONEAREST_1 (__FE_ROUND_ELE_1 | __FE_SPU_TONEAREST) 134 #define FE_TOWARDZERO_1 (__FE_ROUND_ELE_1 | __FE_SPU_TOWARDZERO) 135 #define FE_UPWARD_1 (__FE_ROUND_ELE_1 | __FE_SPU_UPWARD) 136 #define FE_DOWNWARD_1 (__FE_ROUND_ELE_1 | __FE_SPU_DOWNWARD) 137 138 typedef unsigned int fexcept_t; 139 typedef unsigned int fenv_t; 140 141 extern fenv_t _fe_dfl_env; 142 #define FE_DFL_ENV ((const fenv_t *) &_fe_dfl_env) 143 144 #endif /* fenv.h */ 145
