1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ADC_SAR_IP_HEADERWRAPPER_S32K3_H 8 #define ADC_SAR_IP_HEADERWRAPPER_S32K3_H 9 10 /** 11 * @file 12 * 13 * @addtogroup adc_sar_ip Adc Sar IPL 14 * @{ 15 */ 16 17 #ifdef __cplusplus 18 extern "C"{ 19 #endif 20 21 /* Important Note: This file cannot be used independently. 22 * It depends on platform header files to be included before including it */ 23 24 /*================================================================================================== 25 * SOURCE FILE VERSION INFORMATION 26 ==================================================================================================*/ 27 #define ADC_SAR_IP_VENDOR_ID_HEADERWRAPPER_S32K3 43 28 #define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32K3 4 29 #define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32K3 7 30 #define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32K3 0 31 #define ADC_SAR_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32K3 3 32 #define ADC_SAR_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32K3 0 33 #define ADC_SAR_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32K3 0 34 35 /*================================================================================================== 36 * DEFINITIONS 37 ==================================================================================================*/ 38 39 #define ADC_SAR_IP_NUM_GROUP_CHAN (3U) 40 #define ADC_SAR_IP_CDR_COUNT (96U) 41 #define ADC_SAR_IP_INSTANCE_COUNT ADC_INSTANCE_COUNT 42 #define ADC_SAR_IP_THRHLR_COUNT ADC_THRHLR_COUNT 43 #define ADC_SAR_IP_CWSELR_COUNT (3U) 44 #define ADC_SAR_IP_MAX_RESOLUTION (14U) 45 #define ADC_SAR_IP_RESULT_RESOLUTION (15U) /* Resolution of the result written by the ADC module */ 46 #define ADC_SAR_IP_HAS_THRHLR_ARRAY (1U) 47 #define ADC_SAR_IP_HAS_CWSELR_UNROLLED (0U) 48 #define ADC_SAR_IP_CALIBRATION_USES_MCR (0U) 49 50 #define ADC_SAR_IP_PRESAMPLE_VREFL_EVAL (0U) 51 #define ADC_SAR_IP_PRESAMPLE_VREFH_EVAL (1U) 52 53 #define ADC_SAR_IP_HAS_ADCLKSEL (1U) 54 #define ADC_SAR_IP_MSR_ADCSTATUS_POWER_DOWN (1U) 55 #define ADC_SAR_IP_MSR_ADCSTATUS_IDLE (0U) 56 57 #define FEATURE_ADC_BAD_ACCESS_PROT_FEATURE (1U) 58 #define FEATURE_ADC_BAD_ACCESS_PROT_CHANNEL (1U) 59 #define FEATURE_ADC_HAS_CTU_TRIGGER_MODE (1U) 60 #define FEATURE_ADC_HAS_CTU (1U) 61 #define FEATURE_ADC_HAS_CLKSEL_EXTENDED (1U) 62 #define FEATURE_ADC_SAR_W1C_ABORT (1U) 63 #define FEATURE_ADC_HAS_TEMPSENSE_CHN (1U) 64 #define FEATURE_ADC_SELFTEST_FULL_CLK (0U) 65 66 #define FEATURE_ADC_HAS_SELFTEST_STCR1 (1U) 67 #define FEATURE_ADC_HAS_SELFTEST_STCR3 (1U) 68 #define FEATURE_ADC_HAS_BANDGAP_STATUS (0U) 69 #define FEATURE_ADC_HAS_SELFTEST_USE_CH32 (0U) 70 71 #define FEATURE_ADC_ABORTCHAIN_WORKAROUND (0U) 72 73 #if (ADC_SAR_IP_INSTANCE_COUNT > 3U) 74 /* 31-28 3-0 63-60 35-32 95-92 67-64 75 \_/ \_/ \_/ \_/ \_/ \_/ 76 |......| |......| |......| */ 77 #define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x004FFFFFU, 0xFFFFFFFFU}, /* 0 */ \ 78 {0x000000FFU, 0x004FFFFFU, 0xFFFFFFFFU}, /* 1 */ \ 79 {0x000000FFU, 0x000FFFFFU, 0x00000000U}, /* 2 */ \ 80 {0x000000FFU, 0x000F000FU, 0x00000000U}, /* 3 */ \ 81 {0x000000FFU, 0x000F000FU, 0x00000000U}, /* 4 */ \ 82 {0x000000FFU, 0x000F000FU, 0x00000000U}, /* 5 */ \ 83 {0x000000FFU, 0x000F000FU, 0x00000000U}, /* 6 */ \ 84 } 85 /* Adc Channels are divided into 3 Groups. */ 86 /* This array shows max number of channels of each group. */ 87 /* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */ 88 /* Should be same with ADC_CDRx_COUNT in header file (from Base) */ 89 #define FEATURE_ADC_MAX_CHN_COUNT {{8U, 26U, 32U}, /* Adc HW Unit 0 */ \ 90 {8U, 26U, 32U}, /* Adc HW Unit 1 */ \ 91 {8U, 26U, 0U}, /* Adc HW Unit 2 */ \ 92 {8U, 26U, 0U}, /* Adc HW Unit 3 */ \ 93 {8U, 26U, 0U}, /* Adc HW Unit 4 */ \ 94 {8U, 26U, 0U}, /* Adc HW Unit 5 */ \ 95 {8U, 26U, 0U}, /* Adc HW Unit 6 */ \ 96 } 97 /* Number of group channels of each unit */ 98 /* Unit 0 / 1 / 2 / 3 / 4 / 5 / 6 */ 99 #define FEATURE_ADC_MAX_GROUP_COUNT { 3U, 3U, 2U, 2U, 2U, 2U, 2U } 100 /* Bit0: DSDR is available 101 Bit1: PSCR is available 102 Bit2: CTU is available */ 103 #define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x00000007U, /* Adc HW Unit 0 */ \ 104 0x00000007U, /* Adc HW Unit 1 */ \ 105 0x00000006U, /* Adc HW Unit 2 */ \ 106 0x00000006U, /* Adc HW Unit 3 */ \ 107 0x00000006U, /* Adc HW Unit 4 */ \ 108 0x00000006U, /* Adc HW Unit 5 */ \ 109 0x00000006U, /* Adc HW Unit 6 */ \ 110 } 111 #elif (ADC_SAR_IP_INSTANCE_COUNT == 3U) 112 /* 31-28 3-0 63-60 35-32 95-92 67-64 113 \_/ \_/ \_/ \_/ \_/ \_/ 114 |......| |......| |......| */ 115 #define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00C7FFFFU, 0xFFFFFFFFU}, /* 0 */ \ 116 {0x000000FFU, 0x00C3FFFFU, 0xFFFFFFFFU}, /* 1 */ \ 117 {0x000000FFU, 0x00C3FFFFU, 0x00000000U}, /* 2 */ \ 118 } 119 /* Adc Channels are divided into 3 Groups. */ 120 /* This array shows max number of channels of each group. */ 121 /* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */ 122 /* Should be same with ADC_CDRx_COUNT in header file (from Base) */ 123 #define FEATURE_ADC_MAX_CHN_COUNT {{8U, 24U, 32U}, /* Adc HW Unit 0 */ \ 124 {8U, 24U, 32U}, /* Adc HW Unit 1 */ \ 125 {8U, 24U, 0U}, /* Adc HW Unit 2 */ \ 126 } 127 /* Number of group channels of each unit */ 128 /* Unit 0 / 1 / 2 */ 129 #define FEATURE_ADC_MAX_GROUP_COUNT { 3U, 3U, 2U } 130 /* Bit0: DSDR is available 131 Bit1: PSCR is available 132 Bit2: CTU is available */ 133 #define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x00000007U, /* Adc HW Unit 0 */ \ 134 0x00000007U, /* Adc HW Unit 1 */ \ 135 0x00000006U, /* Adc HW Unit 2 */ \ 136 } 137 #elif (ADC_SAR_IP_INSTANCE_COUNT == 2U) 138 /* 31-28 3-0 63-60 35-32 95-92 67-64 139 \_/ \_/ \_/ \_/ \_/ \_/ 140 |......| |......| |......| */ 141 #define FEATURE_ADC_CHN_AVAIL_BITMAP {{0x000000FFU, 0x00C7FFFFU, 0xFFFFFFFFU}, /* 0 */ \ 142 {0x000000FFU, 0x00C3FFFFU, 0xFFFFFFFFU}, /* 1 */ \ 143 } 144 /* Adc Channels are divided into 3 Groups. */ 145 /* This array shows max number of channels of each group. */ 146 /* There are some registers that relate to this one: CEOCFR, CIMR, DMAR, PSR, NCMR, JCMR,... */ 147 /* Should be same with ADC_CDRx_COUNT in header file (from Base) */ 148 #define FEATURE_ADC_MAX_CHN_COUNT {{8U, 24U, 32U}, /* Adc HW Unit 0 */ \ 149 {8U, 24U, 32U}, /* Adc HW Unit 1 */ \ 150 } 151 /* Number of group channels of each unit */ 152 /* Unit 0 / 1 */ 153 #define FEATURE_ADC_MAX_GROUP_COUNT { 3U, 3U } 154 /* Bit0: DSDR is available 155 Bit1: PSCR is available 156 Bit2: CTU is available 157 Bit3: CTU trigger mode is available */ 158 #define FEATURE_ADC_FEAT_AVAIL_BITMAP {0x0000000FU, /* Adc HW Unit 0 */ \ 159 0x0000000FU, /* Adc HW Unit 1 */ \ 160 } 161 #else 162 #error "Unknown platform!" 163 #endif /* (ADC_SAR_IP_INSTANCE_COUNT > 3U) */ 164 165 /* Register access defines */ 166 #define REG_ACCESS(reg, index) (*(volatile uint32*)(&(((&(reg))[(index)])))) 167 #define REG_READ(reg, index) (*(volatile const uint32*)(&(((&(reg))[(index)])))) 168 169 #define CEOCFR(base, regIndex) REG_ACCESS((base)->CEOCFR0, (regIndex)) 170 #define CIMR(base, regIndex) REG_ACCESS((base)->CIMR0, (regIndex)) 171 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex)) 172 #define PSR(base, regIndex) REG_ACCESS((base)->PSR0, (regIndex)) 173 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex)) 174 #define NCMR(base, regIndex) REG_ACCESS((base)->NCMR0, (regIndex)) 175 #define JCMR(base, regIndex) REG_ACCESS((base)->JCMR0, (regIndex)) 176 #define CWSELR(base, regIndex) REG_ACCESS((base)->CWSELRPI[0U], (regIndex)) 177 #define CWENR(base, regIndex) REG_ACCESS((base)->CWENR0, (regIndex)) 178 #define AWORR(base, regIndex) REG_ACCESS((base)->AWORR0, (regIndex)) 179 #define CDR(base, chanIndex) REG_READ((base)->PCDR[0U], (chanIndex)) 180 181 /* MCR */ 182 #define ADC_MCR_CTU_MODE_MASK ADC_MCR_BCTU_MODE_MASK 183 #define ADC_MCR_CTU_MODE(x) ADC_MCR_BCTU_MODE(x) 184 #define ADC_MCR_CTUEN_MASK ADC_MCR_BCTUEN_MASK 185 #define ADC_MCR_CTUEN(x) ADC_MCR_BCTUEN(x) 186 187 /* MSR */ 188 #define ADC_MSR_CTUSTART_MASK ADC_MSR_BCTUSTART_MASK 189 190 /* ISR */ 191 #define ADC_ISR_EOCTU_MASK ADC_ISR_EOBCTU_MASK 192 #define ADC_ISR_EOCTU(x) ADC_ISR_EOBCTU(x) 193 194 /* IMR */ 195 #define ADC_IMR_MSKEOCTU_MASK ADC_IMR_MSKEOBCTU_MASK 196 #define ADC_IMR_MSKEOCTU(x) ADC_IMR_MSKEOBCTU(x) 197 198 /* CTR */ 199 #define ADC_CTR_INPSAMP(x) ADC_CTR0_INPSAMP(x) 200 201 /* NCMR */ 202 #define ADC_NCMR_CH0(x) ADC_NCMR0_CH0(x) 203 204 /* CDR */ 205 #if defined(ADC_PCDR_CDATA_MASK) 206 #define ADC_CDR_CDATA_MASK ADC_PCDR_CDATA_MASK 207 #define ADC_CDR_CDATA_SHIFT ADC_PCDR_CDATA_SHIFT 208 #define ADC_CDR_RESULT_MASK ADC_PCDR_RESULT_MASK 209 #define ADC_CDR_RESULT(x) ADC_PCDR_RESULT(x) 210 #define ADC_CDR_OVERW_MASK ADC_PCDR_OVERW_MASK 211 #define ADC_CDR_OVERW_SHIFT ADC_PCDR_OVERW_SHIFT 212 #define ADC_CDR_VALID_MASK ADC_PCDR_VALID_MASK 213 #elif defined(ADC_PCDR0_CDATA_MASK) 214 #define ADC_CDR_CDATA_MASK ADC_PCDR0_CDATA_MASK 215 #define ADC_CDR_CDATA_SHIFT ADC_PCDR0_CDATA_SHIFT 216 #define ADC_CDR_RESULT_MASK ADC_PCDR0_RESULT_MASK 217 #define ADC_CDR_RESULT(x) ADC_PCDR0_RESULT(x) 218 #define ADC_CDR_OVERW_MASK ADC_PCDR0_OVERW_MASK 219 #define ADC_CDR_OVERW_SHIFT ADC_PCDR0_OVERW_SHIFT 220 #define ADC_CDR_VALID_MASK ADC_PCDR0_VALID_MASK 221 #else 222 #error "Unknown platform!" 223 #endif /* defined(ADC_PCDR_CDATA_MASK) */ 224 225 /* CWSELR */ 226 #define ADC_CWSELR_WSEL_CH0_MASK ADC_CWSELRPI_WSEL_SI0_0_MASK 227 #define ADC_CWSELR_WSEL_CH0(x) ADC_CWSELRPI_WSEL_SI0_0(x) 228 #define ADC_CWSELR_WSEL_CH1_SHIFT ADC_CWSELRPI_WSEL_SI0_1_SHIFT 229 230 /* USROFSGN - Offset and Gain User */ 231 #define ADC_USER_OFFSET_GAIN_REG OFSGNUSR 232 #define ADC_USER_OFFSET(x) ADC_OFSGNUSR_OFFSET_USER(x) 233 #define ADC_USER_GAIN(x) ADC_OFSGNUSR_GAIN_USER(x) 234 235 /* Tempsense module */ 236 #define ADC_SAR_IP_TEMPSENSE_CHANNEL (49U) 237 #define ADC_SAR_IP_TEMPSENSE_RESOLUTION (12U) 238 #define ADC_SAR_IP_TEMPSENSE_RESOLUTION_12B (4096U) 239 #define ADC_SAR_IP_TEMPSENSE_SIGN_MASK (0x8000U) 240 #define ADC_SAR_IP_TEMPSENSE_INTEGER_MASK (0x7FF0U) 241 #define ADC_SAR_IP_TEMPSENSE_INTEGER_SHIFT (4U) 242 #define ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK (0xFU) 243 #define ADC_SAR_IP_TEMPSENSE_MULTIPLIER (100U) 244 245 /*! @name CALBISTREG - Control And Calibration Status */ 246 /*! @{ */ 247 248 #define ADC_SAR_IP_CALBISTREG_TEST_EN_MASK ADC_CALBISTREG_TEST_EN_MASK 249 #define ADC_SAR_IP_CALBISTREG_TEST_EN(x) ADC_CALBISTREG_TEST_EN(x) 250 #define ADC_SAR_IP_CALBISTREG_TEST_FAIL_MASK ADC_CALBISTREG_TEST_FAIL_MASK 251 #define ADC_SAR_IP_CALBISTREG_AVG_EN_MASK ADC_CALBISTREG_AVG_EN_MASK 252 #define ADC_SAR_IP_CALBISTREG_AVG_EN(x) ADC_CALBISTREG_AVG_EN(x) 253 #define ADC_SAR_IP_CALBISTREG_NR_SMPL_MASK ADC_CALBISTREG_NR_SMPL_MASK 254 #define ADC_SAR_IP_CALBISTREG_NR_SMPL(x) ADC_CALBISTREG_NR_SMPL(x) 255 #define ADC_SAR_IP_CALBISTREG_C_T_BUSY_MASK ADC_CALBISTREG_C_T_BUSY_MASK 256 #define ADC_SAR_IP_CALBISTREG_TSAMP_MASK ADC_CALBISTREG_TSAMP_MASK 257 258 #ifdef __cplusplus 259 } 260 #endif 261 262 /** @} */ 263 264 #endif /* ADC_SAR_IP_HEADERWRAPPER_S32K3_H */ 265
