1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef EMIOS_PWM_IP_HWACCESS_H
8 #define EMIOS_PWM_IP_HWACCESS_H
9
10 /**
11 * @file Emios_Pwm_Ip_HwAccess.h
12 * @implements Emios_Pwm_Ip_HwAccess.h_Artifact
13 *
14 * @addtogroup emios_pwm_ip Emios Pwm IPL
15 * @{
16 */
17
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Emios_Pwm_Ip_Cfg.h"
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define EMIOS_PWM_IP_HWACCESS_VENDOR_ID 43
36 #define EMIOS_PWM_IP_HWACCESS_MODULE_ID 121
37 #define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION 4
38 #define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION 7
39 #define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_REVISION_VERSION 0
40 #define EMIOS_PWM_IP_HWACCESS_SW_MAJOR_VERSION 2
41 #define EMIOS_PWM_IP_HWACCESS_SW_MINOR_VERSION 0
42 #define EMIOS_PWM_IP_HWACCESS_SW_PATCH_VERSION 0
43
44 /*==================================================================================================
45 * FILE VERSION CHECKS
46 ==================================================================================================*/
47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
48 /* Check if header file and Std_Types.h are of the same AUTOSAR version */
49 #if ((EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
50 (EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
51 #error "AUTOSAR Version Numbers of Emios_Pwm_Ip_HwAccess.h and Std_Types.h are different"
52 #endif
53 #endif
54
55 /* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same vendor */
56 #if (EMIOS_PWM_IP_HWACCESS_VENDOR_ID != EMIOS_PWM_IP_CFG_VENDOR_ID)
57 #error "Vendor IDs of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
58 #endif
59
60 /* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same AUTOSAR version */
61 #if ((EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \
62 (EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_MINOR_VERSION) || \
63 (EMIOS_PWM_IP_HWACCESS_AR_RELEASE_REVISION_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_REVISION_VERSION))
64 #error "AUTOSAR version numbers of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
65 #endif
66
67 /* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same software version */
68 #if ((EMIOS_PWM_IP_HWACCESS_SW_MAJOR_VERSION != EMIOS_PWM_IP_CFG_SW_MAJOR_VERSION) || \
69 (EMIOS_PWM_IP_HWACCESS_SW_MINOR_VERSION != EMIOS_PWM_IP_CFG_SW_MINOR_VERSION) || \
70 (EMIOS_PWM_IP_HWACCESS_SW_PATCH_VERSION != EMIOS_PWM_IP_CFG_SW_PATCH_VERSION))
71 #error "Software version numbers of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
72 #endif
73
74 /*==================================================================================================
75 * CONSTANTS
76 ==================================================================================================*/
77
78 /*==================================================================================================
79 * DEFINES AND MACROS
80 ==================================================================================================*/
81
82 /*==================================================================================================
83 * ENUMS
84 ==================================================================================================*/
85 #if (EMIOS_PWM_IP_USED == STD_ON)
86 /*!
87 * @brief Emios PWM Channel modes
88 */
89 typedef enum
90 {
91 /** @brief Output Pulse Width and Frequency Modulation Buffered.*/
92 EMIOS_PWM_IP_HW_MODE_OPWFMB = 0x00U,
93 /** @brief Center Aligned Output Pulse Width Modulation Buffered */
94 EMIOS_PWM_IP_HW_MODE_OPWMCB = 0x01U,
95 /** @brief Output Pulse Width Modulation Buffered. */
96 EMIOS_PWM_IP_HW_MODE_OPWMB = 0x02U,
97 /** @brief Output Pulse-Width Modulation with Trigger */
98 EMIOS_PWM_IP_HW_MODE_OPWMT = 0x03U,
99 /** @brief Double Action Output Compare */
100 EMIOS_PWM_IP_HW_MODE_DAOC = 0x04U,
101 /** @brief Center Aligned Output Pulse Width Modulation */
102 EMIOS_PWM_IP_HW_MODE_OPWMC = 0x05U,
103 /** @brief Output Pulse Width Modulation. */
104 EMIOS_PWM_IP_HW_MODE_OPWM = 0x06U,
105 /** @brief Output Pulse Width and Frequency Modulation.*/
106 EMIOS_PWM_IP_HW_MODE_OPWFM = 0x07U
107 } Emios_Pwm_Ip_PwmType;
108
109 /*!
110 * @brief Emios PWM master bus modes
111 */
112 typedef enum
113 {
114 EMIOS_PWM_IP_MC_UP_COUNTER_START = 16u,
115 EMIOS_PWM_IP_MC_UP_COUNTER_END = 18u,
116 EMIOS_PWM_IP_MC_UP_DOWN_COUNTER = 20u,
117 EMIOS_PWM_IP_MCB_UP_COUNTER = 80u,
118 EMIOS_PWM_IP_MCB_UP_DOWN_COUNTER = 84u,
119 EMIOS_PWM_IP_NODEFINE_COUNTER = 0u
120 } Emios_Pwm_Ip_MasterBusModeType;
121
122 /*==================================================================================================
123 * STRUCTURES AND OTHER TYPEDEFS
124 ==================================================================================================*/
125
126 /*==================================================================================================
127 * GLOBAL VARIABLE DECLARATIONS
128 ==================================================================================================*/
129 #if (EMIOS_PWM_IP_NO_CACHE_NEEDED == STD_ON)
130 #define PWM_START_SEC_VAR_INIT_8_NO_CACHEABLE
131 #else
132 #define PWM_START_SEC_VAR_INIT_8
133 #endif
134 #include "Pwm_MemMap.h"
135
136 /* Arrays to store the channel logic Index State */
137 extern uint8 eMios_Pwm_Ip_IndexInChState[EMIOS_PWM_IP_INSTANCE_COUNT][EMIOS_PWM_IP_CHANNEL_COUNT];
138
139 #if (EMIOS_PWM_IP_NO_CACHE_NEEDED == STD_ON)
140 #define PWM_STOP_SEC_VAR_INIT_8_NO_CACHEABLE
141 #else
142 #define PWM_STOP_SEC_VAR_INIT_8
143 #endif
144 #include "Pwm_MemMap.h"
145
146 /*==================================================================================================
147 * FUNCTION PROTOTYPES
148 ==================================================================================================*/
149 #define PWM_START_SEC_CODE
150 #include "Pwm_MemMap.h"
151 /*-----------------------MCR Register----------------------------*/
152 /*!
153 * brief Get MCR Freeze enable bit
154 * param[in] Base The Emios base address pointer
155 */
Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType * const Base)156 static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const Base)
157 {
158 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE;
159 }
160
161 /*-----------------------OUDIS Register----------------------------*/
162 /*!
163 * brief Set OUDIS Channel n enable bit
164 * param[in] Base The Emios Base address pointer
165 * param[in] Channel The Channel id for the given instance
166 * param[in] Value The Value to set
167 */
Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)168 static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const Base,
169 uint8 Channel,
170 boolean Value
171 )
172 {
173 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel);
174 }
175
176 /*!
177 * brief Get OUDIS Channel n enable bit
178 * param[in] Base The Emios Base address pointer
179 * param[in] Channel The Channel id for the given instance
180 */
Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)181 static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const Base,
182 uint8 Channel
183 )
184 {
185 return (((Base->OUDIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE;
186 }
187
188 /*!
189 * brief Get OUDIS register
190 * param[in] Base The Emios Base address pointer
191 */
Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType * const Base)192 static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const Base)
193 {
194 return (Base->OUDIS);
195 }
196
197 /*-----------------------UC register A-----------------------------*/
198 /*!
199 * brief Set A register's Value, maximum Value is 0xFFFFFF
200 * param[in] Base The Emios Base address pointer
201 * param[in] Channel The Channel id for the given instance
202 * param[in] Value The Value to set
203 */
Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PeriodType Value)204 static inline void Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType *const Base,
205 uint8 Channel,
206 Emios_Pwm_Ip_PeriodType Value
207 )
208 {
209 Base->CH.UC[Channel].A = eMIOS_A_A(Value);
210 }
211
212 /*!
213 * brief Get A register's Value
214 * param[in] Base The Emios Base address pointer
215 * param[in] Channel The Channel id for the given instance
216 * return Value of Unified Channels A register
217 */
Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)218 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType *const Base,
219 uint8 Channel
220 )
221 {
222 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].A & eMIOS_A_A_MASK) >> eMIOS_A_A_SHIFT);
223 }
224
225 /*-----------------------UC register B-----------------------------*/
226 /*!
227 * brief Set B register's Value, maximum Value is 0xFFFFFF
228 * param[in] Base The Emios Base address pointer
229 * param[in] Channel The Channel id for the given instance
230 * param[in] Value The Value to set
231 */
Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PeriodType Value)232 static inline void Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType *const Base,
233 uint8 Channel,
234 Emios_Pwm_Ip_PeriodType Value
235 )
236 {
237 Base->CH.UC[Channel].B = eMIOS_B_B(Value);
238 }
239
240 /*!
241 * brief Get B register's Value
242 * param[in] Base The Emios Base address pointer
243 * param[in] Channel The Channel id for the given instance
244 * return Value of Unified Channels B register
245 */
Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)246 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType *const Base,
247 uint8 Channel
248 )
249 {
250 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].B & eMIOS_B_B_MASK) >> eMIOS_B_B_SHIFT);
251 }
252
253 /*-----------------------UC register CNT-----------------------------*/
254 /*!
255 * brief Get CNT register's Value
256 * param[in] Base The Emios Base address pointer
257 * param[in] Channel The Channel id for the given instance
258 * return Value of Unified Channels CNT register
259 */
Emios_Pwm_Ip_GetInternalCounterValue(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)260 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetInternalCounterValue(const Emios_Pwm_Ip_HwAddrType *const Base,
261 uint8 Channel
262 )
263 {
264 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].CNT & eMIOS_CNT_C_MASK) >> eMIOS_CNT_C_SHIFT);
265 }
266
267 /*----------------------------UC register C bit fields--------------------------*/
268 /*!
269 * brief Set Freeze Enable bit
270 * param[in] Base The Emios Base address pointer
271 * param[in] Channel The Channel id for the given instance
272 * param[in] Value The Value to set
273 * - 0 Normal operation
274 * - 1 Freeze UC registers values
275 */
Emios_Pwm_Ip_SetFreezeEnable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)276 static inline void Emios_Pwm_Ip_SetFreezeEnable(Emios_Pwm_Ip_HwAddrType *const Base,
277 uint8 Channel,
278 boolean Value
279 )
280 {
281 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
282 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FREN_MASK)) | eMIOS_C_FREN(ValueConvert);
283 }
284
285 /*!
286 * brief Set Output Disable bit
287 * param[in] Base The Emios Base address pointer
288 * param[in] Channel The Channel id for the given instance
289 * param[in] Value The Value to set
290 */
Emios_Pwm_Ip_SetOutDisable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)291 static inline void Emios_Pwm_Ip_SetOutDisable(Emios_Pwm_Ip_HwAddrType *const Base,
292 uint8 Channel,
293 boolean Value
294 )
295 {
296 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
297 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_ODIS_MASK)) | eMIOS_C_ODIS(ValueConvert);
298 }
299
300 /*!
301 * brief Set Output Disable select Value
302 * param[in] Base The Emios Base address pointer
303 * param[in] Channel The Channel id for the given instance
304 * param[in] Value The Value to set
305 */
Emios_Pwm_Ip_SetOutDisableSource(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_OutDisableSourceType Value)306 static inline void Emios_Pwm_Ip_SetOutDisableSource(Emios_Pwm_Ip_HwAddrType *const Base,
307 uint8 Channel,
308 Emios_Pwm_Ip_OutDisableSourceType Value
309 )
310 {
311 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_ODISSL_MASK)) | eMIOS_C_ODISSL(Value);
312 }
313
314 /*!
315 * brief Set Prescaler Enable bit.
316 * param[in] Base The Emios Base address pointer
317 * param[in] Channel The Channel id for the given instance
318 * param[in] Value The Value to set
319 * - 0 Prescaler disabled (no clock)
320 * - 1 Prescaler enabled
321 */
Emios_Pwm_Ip_SetPrescalerEnable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)322 static inline void Emios_Pwm_Ip_SetPrescalerEnable(Emios_Pwm_Ip_HwAddrType *const Base,
323 uint8 Channel,
324 boolean Value
325 )
326 {
327 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
328 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_UCPREN_MASK)) | eMIOS_C_UCPREN(ValueConvert);
329 }
330
331 /* Bitfiled UCPRE is not used. Instead the Value is controled using UCEXTPRE from C2 */
332
333 /*!
334 * brief Set Direct Memory Access bit
335 * param[in] Base The Emios Base address pointer
336 * param[in] Channel The Channel id for the given instance
337 * param[in] Value The Value to set
338 * - 0 Flag/overrun assigned to Interrupt request.
339 * - 1 Flag/overrun assigned to DMA request.
340 */
Emios_Pwm_Ip_SetDMARequest(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)341 static inline void Emios_Pwm_Ip_SetDMARequest(Emios_Pwm_Ip_HwAddrType *const Base,
342 uint8 Channel,
343 boolean Value
344 )
345 {
346 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
347 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_DMA_MASK)) | eMIOS_C_DMA(ValueConvert);
348 }
349
350 /*!
351 * brief Get Direct Memory Access bit
352 * param[in] Base The Emios Base address pointer
353 * param[in] Channel The Channel id for the given instance
354 * return Value of Direct Memory Access state in Unified Channels Control register
355 * - 0 Flag/overrun assigned to Interrupt request.
356 * - 1 Flag/overrun assigned to DMA request.
357 */
Emios_Pwm_Ip_GetDMARequest(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)358 static inline boolean Emios_Pwm_Ip_GetDMARequest(const Emios_Pwm_Ip_HwAddrType *const Base,
359 uint8 Channel
360 )
361 {
362 return (((Base->CH.UC[Channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE;
363 }
364
365 /*!
366 * brief Set FLAG Enable bit
367 * param[in] Base The Emios Base address pointer
368 * param[in] Channel The Channel id for the given instance
369 * param[in] Value The Value to set
370 * - 0 Disable (FLAG does not generate an interrupt request)
371 * - 1 Enable (FLAG generates an interrupt request)
372 */
Emios_Pwm_Ip_SetInterruptRequest(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)373 static inline void Emios_Pwm_Ip_SetInterruptRequest(Emios_Pwm_Ip_HwAddrType *const Base,
374 uint8 Channel,
375 boolean Value
376 )
377 {
378 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
379 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FEN_MASK)) | eMIOS_C_FEN(ValueConvert);
380 }
381
382 /*!
383 * brief Get FLAG Enable bit
384 * param[in] Base The Emios Base address pointer
385 * param[in] Channel The Channel id for the given instance
386 * return Value of FLAG Enable bit
387 * - 0 Disable (FLAG does not generate an interrupt request)
388 * - 1 Enable (FLAG generates an interrupt request)
389 */
Emios_Pwm_Ip_GetInterruptRequest(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)390 static inline boolean Emios_Pwm_Ip_GetInterruptRequest(const Emios_Pwm_Ip_HwAddrType *const Base,
391 uint8 Channel
392 )
393 {
394 return (((Base->CH.UC[Channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE;
395 }
396
397 /*!
398 * brief Force Match A bit
399 * param[in] Base The Emios Base address pointer
400 * param[in] Channel The Channel id for the given instance
401 * param[in] Value The Value to set
402 * - 0 Has no effect.
403 * - 1 Force a match at comparator A
404 */
Emios_Pwm_Ip_SetForceMatchA(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)405 static inline void Emios_Pwm_Ip_SetForceMatchA(Emios_Pwm_Ip_HwAddrType *const Base,
406 uint8 Channel,
407 boolean Value
408 )
409 {
410 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
411 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FORCMA_MASK)) | eMIOS_C_FORCMA(ValueConvert);
412 }
413
414 /*!
415 * brief Force Match B bit
416 * param[in] Base The Emios Base address pointer
417 * param[in] Channel The Channel id for the given instance
418 * param[in] Value The Value to set
419 * - 0 Has no effect.
420 * - 1 Force a match at comparator B
421 */
Emios_Pwm_Ip_SetForceMatchB(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)422 static inline void Emios_Pwm_Ip_SetForceMatchB(Emios_Pwm_Ip_HwAddrType *const Base,
423 uint8 Channel,
424 boolean Value
425 )
426 {
427 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
428 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FORCMB_MASK)) | eMIOS_C_FORCMB(ValueConvert);
429 }
430
431 /*!
432 * brief Set Bus Select bits.
433 * param[in] Base The Emios Base address pointer
434 * param[in] Channel The Channel id for the given instance
435 * param[in] Value The Value to set
436 */
Emios_Pwm_Ip_SetCounterBus(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_CounterBusSourceType Value)437 static inline void Emios_Pwm_Ip_SetCounterBus(Emios_Pwm_Ip_HwAddrType *const Base,
438 uint8 Channel,
439 Emios_Pwm_Ip_CounterBusSourceType Value
440 )
441 {
442 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_BSL_MASK)) | eMIOS_C_BSL(Value);
443 }
444
445 /*!
446 * brief Get Bus Select Value
447 * param[in] Base The Emios Base address pointer
448 * param[in] Channel The Channel id for the given instance
449 * return Value of Bus Select in Unified Channels Control register
450 */
Emios_Pwm_Ip_GetCounterBus(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)451 static inline Emios_Pwm_Ip_CounterBusSourceType Emios_Pwm_Ip_GetCounterBus(const Emios_Pwm_Ip_HwAddrType *const Base,
452 uint8 Channel
453 )
454 {
455 Emios_Pwm_Ip_CounterBusSourceType CounterBus;
456 switch((Base->CH.UC[Channel].C & eMIOS_C_BSL_MASK) >> eMIOS_C_BSL_SHIFT)
457 {
458 case 0x00U:
459 CounterBus = EMIOS_PWM_IP_BUS_A;
460 break;
461 case 0x01U:
462 CounterBus = EMIOS_PWM_IP_BUS_BCDE;
463 break;
464 case 0x02U:
465 CounterBus = EMIOS_PWM_IP_BUS_F;
466 break;
467 default:
468 CounterBus = EMIOS_PWM_IP_BUS_INTERNAL;
469 break;
470 }
471 return CounterBus;
472 }
473
474 /*!
475 * brief Get the timebase channel
476 * param[in] Channel The channel id for the given instance
477 * param[in] Value Bus Select in Unified Channels Control register
478 * return Timebase channel.
479 */
Emios_Pwm_Ip_GetTimebaseChannel(uint8 Channel,Emios_Pwm_Ip_CounterBusSourceType Value)480 static inline uint8 Emios_Pwm_Ip_GetTimebaseChannel(uint8 Channel,
481 Emios_Pwm_Ip_CounterBusSourceType Value
482 )
483 {
484 uint8 TimbaseChannel;
485 switch(Value)
486 {
487 case EMIOS_PWM_IP_BUS_A:
488 TimbaseChannel = (uint8)EMIOS_PWM_IP_COUNTER_BUS_A;
489 break;
490 case EMIOS_PWM_IP_BUS_F:
491 TimbaseChannel = (uint8)EMIOS_PWM_IP_COUNTER_BUS_F;
492 break;
493 case EMIOS_PWM_IP_BUS_BCDE:
494 TimbaseChannel = Channel & (uint8)EMIOS_PWM_IP_COUNTER_BUS_BCDE;
495 break;
496 default:
497 TimbaseChannel = (uint8)0xFFU;
498 break;
499 }
500 (void)Channel;
501
502 return TimbaseChannel;
503 }
504
505 /*FUNCTION**********************************************************************
506 *
507 * Function Name : Emios_Pwm_Ip_GetChannelIndex
508 * Description : Get the value of channel index corresponding the specific hw channel
509 *END**************************************************************************/
Emios_Pwm_Ip_GetChannelIndex(uint8 Instance,uint8 Channel)510 static inline uint8 Emios_Pwm_Ip_GetChannelIndex(uint8 Instance,
511 uint8 Channel
512 )
513 {
514 uint8 channelIdx = 0;
515
516 if ((Instance < EMIOS_PWM_IP_INSTANCE_COUNT) && (Channel < EMIOS_PWM_IP_CHANNEL_COUNT))
517 {
518 channelIdx = eMios_Pwm_Ip_IndexInChState[Instance][Channel];
519 }
520 else
521 {
522 /* Avoid compiler warning */
523 (void) Instance;
524 (void) Channel;
525 (void) channelIdx;
526 }
527
528 return channelIdx;
529 }
530
531 /*!
532 * brief Set Edge Polarity bit.
533 * param[in] Base The Emios Base address pointer
534 * param[in] Channel The Channel id for the given instance
535 * param[in] Value The Value to set
536 */
Emios_Pwm_Ip_SetEdgePolarity(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PolarityType Value)537 static inline void Emios_Pwm_Ip_SetEdgePolarity(Emios_Pwm_Ip_HwAddrType *const Base,
538 uint8 Channel,
539 Emios_Pwm_Ip_PolarityType Value
540 )
541 {
542 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_EDPOL_MASK)) | eMIOS_C_EDPOL(Value);
543 }
544
545 /*!
546 * brief Get Edge Polarity bit.
547 * param[in] Base The Emios Base address pointer
548 * param[in] Channel The Channel id for the given instance
549 * return Value of Edge Polarity bit in Unified Channels Control register
550 */
Emios_Pwm_Ip_GetEdgePolarity(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)551 static inline Emios_Pwm_Ip_PolarityType Emios_Pwm_Ip_GetEdgePolarity(const Emios_Pwm_Ip_HwAddrType *const Base,
552 uint8 Channel
553 )
554 {
555 return (((Base->CH.UC[Channel].C & eMIOS_C_EDPOL_MASK) >> eMIOS_C_EDPOL_SHIFT) == 0U)? (Emios_Pwm_Ip_PolarityType)EMIOS_PWM_IP_ACTIVE_LOW : (Emios_Pwm_Ip_PolarityType)EMIOS_PWM_IP_ACTIVE_HIGH;
556 }
557
558 /*!
559 * brief Set mode of operation of the Unified Channel
560 * param[in] Base The Emios Base address pointer
561 * param[in] Channel The Channel id for the given instance
562 * param[in] Mode The mode to set
563 */
Emios_Pwm_Ip_SetPwmMode(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PwmModeType Mode)564 static inline void Emios_Pwm_Ip_SetPwmMode(Emios_Pwm_Ip_HwAddrType *const Base,
565 uint8 Channel,
566 Emios_Pwm_Ip_PwmModeType Mode
567 )
568 {
569 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_MODE_MASK)) | eMIOS_C_MODE(Mode);
570 }
571
572 /*!
573 * brief Set mode and Edge Polarity bit of operation of the Unified Channel at the same time to avoid spike pulse
574 * param[in] Base The Emios Base address pointer
575 * param[in] Channel The Channel id for the given instance
576 * param[in] Mode The mode to set
577 * param[in] Pol The Edge polarity to set
578 * return void
579 */
Emios_Pwm_Ip_SetPwmModePol(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PwmModeType Mode,Emios_Pwm_Ip_PolarityType Pol)580 static inline void Emios_Pwm_Ip_SetPwmModePol(Emios_Pwm_Ip_HwAddrType *const Base,
581 uint8 Channel,
582 Emios_Pwm_Ip_PwmModeType Mode,
583 Emios_Pwm_Ip_PolarityType Pol
584 )
585 {
586 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_MODE_MASK) & ~(eMIOS_C_EDPOL_MASK)) | eMIOS_C_MODE(Mode) | eMIOS_C_EDPOL(Pol);
587 }
588
589 /*!
590 * brief Get mode of operation of the Unified Channel
591 * param[in] Base The Emios Base address pointer
592 * param[in] Channel The Channel id for the given instance
593 * return Value of Mode selection in Unified Channels Control register
594 */
Emios_Pwm_Ip_GetChannelPwmMode(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)595 static inline Emios_Pwm_Ip_MasterBusModeType Emios_Pwm_Ip_GetChannelPwmMode(const Emios_Pwm_Ip_HwAddrType *const Base,
596 uint8 Channel
597 )
598 {
599 Emios_Pwm_Ip_MasterBusModeType MasterBusMode;
600 switch ((Base->CH.UC[Channel].C & eMIOS_C_MODE_MASK) >> eMIOS_C_MODE_SHIFT)
601 {
602 case 16U:
603 MasterBusMode = EMIOS_PWM_IP_MC_UP_COUNTER_START;
604 break;
605 case 18U:
606 MasterBusMode = EMIOS_PWM_IP_MC_UP_COUNTER_END;
607 break;
608 case 20U:
609 MasterBusMode = EMIOS_PWM_IP_MC_UP_DOWN_COUNTER;
610 break;
611 case 80U:
612 MasterBusMode = EMIOS_PWM_IP_MCB_UP_COUNTER;
613 break;
614 case 84U:
615 MasterBusMode = EMIOS_PWM_IP_MCB_UP_DOWN_COUNTER;
616 break;
617 default:
618 MasterBusMode = EMIOS_PWM_IP_NODEFINE_COUNTER;
619 break;
620 }
621 return MasterBusMode;
622 }
623
624 /*----------------------UC register S bit field-----------------------------*/
625 /*!
626 * brief Write 1 to clear overrun bit
627 * param[in] Base The Emios Base address pointer
628 * param[in] Channel The Channel id for the given instance
629 */
Emios_Pwm_Ip_ClearOverRunFlag(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)630 static inline void Emios_Pwm_Ip_ClearOverRunFlag(Emios_Pwm_Ip_HwAddrType *const Base,
631 uint8 Channel
632 )
633 {
634 /* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
635 Base->CH.UC[Channel].S = (Base->CH.UC[Channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_OVR(1UL);
636 }
637
638 /*!
639 * brief Get overrun bit
640 * param[in] Base The Emios Base address pointer
641 * param[in] Channel The Channel id for the given instance
642 * return Value of Overrun bit in Unified Channels Control register
643 * The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set .
644 * The OVR bit can be cleared either by clearing the FLAG bit or by writing a 1 to the OVR bit.
645 * - 0 Overrun has not occurred
646 * - 1 Overrun has occurred
647 */
Emios_Pwm_Ip_GetOverRunFlag(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)648 static inline boolean Emios_Pwm_Ip_GetOverRunFlag(const Emios_Pwm_Ip_HwAddrType *const Base,
649 uint8 Channel
650 )
651 {
652 return (((Base->CH.UC[Channel].S & eMIOS_S_OVR_MASK) >> eMIOS_S_OVR_SHIFT) == 0U)? FALSE : TRUE;
653 }
654
655 /*!
656 * brief Write 1 to clear the overflow bit.
657 * param[in] Base The Emios Base address pointer
658 * param[in] Channel The Channel id for the given instance
659 */
Emios_Pwm_Ip_ClearOverFlowFlag(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)660 static inline void Emios_Pwm_Ip_ClearOverFlowFlag(Emios_Pwm_Ip_HwAddrType *const Base,
661 uint8 Channel
662 )
663 {
664 /* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
665 Base->CH.UC[Channel].S = (Base->CH.UC[Channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_OVFL(1UL);
666 }
667
668 /*!
669 * brief Get Overflow bit
670 * param[in] Base The Emios Base address pointer
671 * param[in] Channel The Channel id for the given instance
672 * return Value of Overflow bit in Unified Channels Control register
673 * The OVFL bit indicates that an overflow has occurred in the internal counter.
674 * The OVFL bit must be cleared by software writing a 1 to it.
675 * - 0 No overflow
676 * - 1 An overflow had occurred
677 */
Emios_Pwm_Ip_GetOverFlowFlag(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)678 static inline boolean Emios_Pwm_Ip_GetOverFlowFlag(const Emios_Pwm_Ip_HwAddrType *const Base,
679 uint8 Channel
680 )
681 {
682 return (((Base->CH.UC[Channel].S & eMIOS_S_OVFL_MASK) >> eMIOS_S_OVFL_SHIFT) == 0U)? FALSE : TRUE;
683 }
684
685 /*!
686 * brief Get Unified Channel Output pin bit
687 * param[in] Base The Emios Base address pointer
688 * param[in] Channel The Channel id for the given instance
689 * return Value of Unified Channel Output pin bit in Unified Channels Control register
690 */
Emios_Pwm_Ip_GetOutputPinState(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)691 static inline boolean Emios_Pwm_Ip_GetOutputPinState(const Emios_Pwm_Ip_HwAddrType *const Base,
692 uint8 Channel
693 )
694 {
695 return (((Base->CH.UC[Channel].S & eMIOS_S_UCOUT_MASK) >> eMIOS_S_UCOUT_SHIFT) == 0U)? FALSE : TRUE;
696 }
697
698 /*!
699 * brief Write 1 to clear the FLAG bit
700 * param[in] Base The Emios Base address pointer
701 * param[in] Channel The Channel id for the given instance
702 */
Emios_Pwm_Ip_ClearFlagEvent(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)703 static inline void Emios_Pwm_Ip_ClearFlagEvent(Emios_Pwm_Ip_HwAddrType *const Base,
704 uint8 Channel
705 )
706 {
707 /* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
708 Base->CH.UC[Channel].S = (Base->CH.UC[Channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_FLAG(1UL);
709 }
710
711 /*!
712 * brief Get FLAG bit
713 * param[in] Base The Emios Base address pointer
714 * param[in] Channel The Channel id for the given instance
715 * return Value of FLAG bit in Unified Channels Control register
716 * The FLAG bit indicates that a match event has occurred in the Channel.
717 * The FLAG bit must be cleared by software writing a 1 to it.
718 * - 0 No flag event
719 * - 1 A flag eventhad occurred
720 */
Emios_Pwm_Ip_GetOverFlagEvent(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)721 static inline boolean Emios_Pwm_Ip_GetOverFlagEvent(const Emios_Pwm_Ip_HwAddrType *const Base,
722 uint8 Channel
723 )
724 {
725 return (((Base->CH.UC[Channel].S & eMIOS_S_FLAG_MASK) >> eMIOS_S_FLAG_SHIFT) == 0U)? FALSE : TRUE;
726 }
727
728 /*-----------------------UC register ALTA-----------------------------*/
729 /*!
730 * brief Set A2 Channel registers Value
731 * param[in] Base The Emios Base address pointer
732 * param[in] Channel The Channel id for the given instance
733 * param[in] Value The Value to set
734 */
Emios_Pwm_Ip_SetTrigger(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PeriodType Value)735 static inline void Emios_Pwm_Ip_SetTrigger(Emios_Pwm_Ip_HwAddrType *const Base,
736 uint8 Channel,
737 Emios_Pwm_Ip_PeriodType Value
738 )
739 {
740 Base->CH.UC[Channel].ALTA = (Base->CH.UC[Channel].ALTA & ~(eMIOS_ALTA_ALTA_MASK)) | eMIOS_ALTA_ALTA(Value);
741 }
742
743 /*!
744 * brief Get A2 Channel registers Value
745 * param[in] Base The Emios Base address pointer
746 * param[in] Channel The Channel id for the given instance
747 * return Value of A2 Channel registers in Unified Channels Control register
748 */
Emios_Pwm_Ip_GetTrigger(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)749 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetTrigger(const Emios_Pwm_Ip_HwAddrType *const Base,
750 uint8 Channel
751 )
752 {
753 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].ALTA & eMIOS_ALTA_ALTA_MASK) >> eMIOS_ALTA_ALTA_SHIFT);
754 }
755
756 /*------------------UC register C2 --------------------------*/
757 /*!
758 * brief Set Extended Prescaler bits
759 * param[in] Base The Emios Base address pointer
760 * param[in] Channel The Channel id for the given instance
761 * param[in] Value The Value to set
762 */
763 #ifdef EMIOS_PWM_IP_PRESCALER_14BIT
Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,uint16 Value)764 static inline void Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType *const Base,
765 uint8 Channel,
766 uint16 Value
767 )
768 {
769 uint32 ClockDividerValue = (uint32)Value - 1U;
770 /* Set Extended Prescaler bits */
771 Base->CH.UC[Channel].C2 = (Base->CH.UC[Channel].C2 & ~(eMIOS_C2_UCEXTPRE_MASK)) | eMIOS_C2_UCEXTPRE(ClockDividerValue);
772 }
773 #else
774 /*!
775 * brief Set Extended Prescaler bits
776 */
Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_InternalClkPsType Value)777 static inline void Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType *const Base,
778 uint8 Channel,
779 Emios_Pwm_Ip_InternalClkPsType Value
780 )
781 {
782 Base->CH.UC[Channel].C2 = (Base->CH.UC[Channel].C2 & ~(eMIOS_C2_UCEXTPRE_MASK)) | eMIOS_C2_UCEXTPRE(Value);
783 }
784 #endif
785
786 /*!
787 * brief Set Prescaler Clock select bit
788 * param[in] Base The Emios Base address pointer
789 * param[in] Channel The Channel id for the given instance
790 * param[in] Value The Value to set
791 * - 0 Prescaled Clock
792 * - 1 eMIOS module clock
793 */
Emios_Pwm_Ip_SetPrescalerSource(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_InternalPsSrcType Value)794 static inline void Emios_Pwm_Ip_SetPrescalerSource(Emios_Pwm_Ip_HwAddrType *const Base,
795 uint8 Channel,
796 Emios_Pwm_Ip_InternalPsSrcType Value
797 )
798 {
799 Base->CH.UC[Channel].C2 = (Base->CH.UC[Channel].C2 & ~(eMIOS_C2_UCPRECLK_MASK)) | eMIOS_C2_UCPRECLK(Value);
800 }
801
802 #define PWM_STOP_SEC_CODE
803 #include "Pwm_MemMap.h"
804 #endif /* EMIOS_PWM_IP_USED == STD_ON */
805
806
807 #ifdef __cplusplus
808 }
809 #endif
810
811 /** @} */
812
813 #endif /* EMIOS_PWM_IP_HWACCESS_H */
814
