1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Emios_Mcl_Ip.c
9 *
10 * @version 2.0.0
11 *
12 * @brief AUTOSAR Mcl - Emios Common driver source file.
13 * @details
14 *
15 * @addtogroup EMIOS_IP_DRIVER EMIOS IP Driver
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Emios_Mcl_Ip.h"
30
31 /*==================================================================================================
32 * SOURCE FILE VERSION INFORMATION
33 ==================================================================================================*/
34 #define EMIOS_MCL_IP_VENDOR_ID_C 43
35 #define EMIOS_MCL_IP_AR_RELEASE_MAJOR_VERSION_C 4
36 #define EMIOS_MCL_IP_AR_RELEASE_MINOR_VERSION_C 7
37 #define EMIOS_MCL_IP_AR_RELEASE_REVISION_VERSION_C 0
38 #define EMIOS_MCL_IP_SW_MAJOR_VERSION_C 2
39 #define EMIOS_MCL_IP_SW_MINOR_VERSION_C 0
40 #define EMIOS_MCL_IP_SW_PATCH_VERSION_C 0
41 /*==================================================================================================
42 * FILE VERSION CHECKS
43 ==================================================================================================*/
44 #if (EMIOS_MCL_IP_VENDOR_ID_C != EMIOS_MCL_IP_VENDOR_ID)
45 #error "Emios_Mcl_Ip.c and Emios_Mcl_Ip.h have different vendor ids"
46 #endif
47
48 /* Check if source file and Emios_Mcl_Ip.h file are of the same Autosar version */
49 #if ((EMIOS_MCL_IP_AR_RELEASE_MAJOR_VERSION_C != EMIOS_MCL_IP_AR_RELEASE_MAJOR_VERSION) || \
50 (EMIOS_MCL_IP_AR_RELEASE_MINOR_VERSION_C != EMIOS_MCL_IP_AR_RELEASE_MINOR_VERSION) || \
51 (EMIOS_MCL_IP_AR_RELEASE_REVISION_VERSION_C != EMIOS_MCL_IP_AR_RELEASE_REVISION_VERSION))
52 #error "AutoSar Version Numbers of Emios_Mcl_Ip.c and Emios_Mcl_Ip.h are different"
53 #endif
54
55 /* Check if source file and Emios_Mcl_Ip.h file are of the same Software version */
56 #if ((EMIOS_MCL_IP_SW_MAJOR_VERSION_C != EMIOS_MCL_IP_SW_MAJOR_VERSION) || \
57 (EMIOS_MCL_IP_SW_MINOR_VERSION_C != EMIOS_MCL_IP_SW_MINOR_VERSION) || \
58 (EMIOS_MCL_IP_SW_PATCH_VERSION_C != EMIOS_MCL_IP_SW_PATCH_VERSION))
59 #error "Software Version Numbers of Emios_Mcl_Ip.c and Emios_Mcl_Ip.h are different"
60 #endif
61 /*==================================================================================================
62 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
63 ==================================================================================================*/
64
65 /*==================================================================================================
66 * LOCAL MACROS
67 ==================================================================================================*/
68
69 /*==================================================================================================
70 * LOCAL CONSTANTS
71 ==================================================================================================*/
72
73 /*==================================================================================================
74 * LOCAL VARIABLES
75 ==================================================================================================*/
76 #define MCL_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
77 #include "Mcl_MemMap.h"
78
79 eMIOS_Type *const Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT] = IP_eMIOS_BASE_PTRS;
80
81 #define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
82 #include "Mcl_MemMap.h"
83
84 #if (EMIOS_IP_MULTICORE_IS_AVAILABLE == STD_ON)
85
86 #define MCL_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
87 #include "Mcl_MemMap.h"
88
89 static Emios_Ip_InstStateType Emios_Ip_axIpIsInitialized[eMIOS_INSTANCE_COUNT] =
90 {
91 {(boolean)FALSE, (uint8)255}
92 };
93
94 #define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
95 #include "Mcl_MemMap.h"
96
97 #else
98
99 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
100 #include "Mcl_MemMap.h"
101
102 VAR_SEC_NOCACHE(Emios_Ip_axIpIsInitialized) static Emios_Ip_InstStateType Emios_Ip_axIpIsInitialized[eMIOS_INSTANCE_COUNT];
103
104 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
105 #include "Mcl_MemMap.h"
106
107 #endif
108
109
110 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
111 #include "Mcl_MemMap.h"
112
113 VAR_SEC_NOCACHE(Emios_Ip_axChState) static Emios_Ip_ChStateType Emios_Ip_axChState[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
114
115 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
116 #include "Mcl_MemMap.h"
117
118 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
119 #define MCL_START_SEC_VAR_CLEARED_32
120 #include "Mcl_MemMap.h"
121
122 /* Array to store the period master bus */
123 static uint32 Emios_Ip_ChPeriodMasterBus[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
124
125 #define MCL_STOP_SEC_VAR_CLEARED_32
126 #include "Mcl_MemMap.h"
127 #else
128 #define MCL_START_SEC_VAR_CLEARED_16
129 #include "Mcl_MemMap.h"
130
131 /* Array to store the period master bus */
132 static uint16 Emios_Ip_ChPeriodMasterBus[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
133
134 #define MCL_STOP_SEC_VAR_CLEARED_16
135 #include "Mcl_MemMap.h"
136 #endif
137
138 /*==================================================================================================
139 * GLOBAL CONSTANTS
140 ==================================================================================================*/
141
142 /*==================================================================================================
143 * GLOBAL VARIABLES
144 ==================================================================================================*/
145
146 /*==================================================================================================
147 * LOCAL FUNCTION PROTOTYPES
148 ==================================================================================================*/
149
150 /*==================================================================================================
151 * LOCAL FUNCTIONS
152 ==================================================================================================*/
153
154 /*==================================================================================================
155 * GLOBAL FUNCTIONS
156 ==================================================================================================*/
157 #define MCL_START_SEC_CODE
158 #include "Mcl_MemMap.h"
159
160 /** @implements Emios_Mcl_Ip_Init_Activity */
Emios_Mcl_Ip_Init(uint8 Instance,const Emios_Mcl_Ip_ConfigType * const ConfigPtr)161 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType* const ConfigPtr)
162 {
163 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
164 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
165 DevAssert(ConfigPtr != NULL_PTR);
166 #endif
167
168 uint8 CurrentChannel;
169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
170 Emios_Ip_CommonStatusType Status = EMIOS_IP_COMMON_STATUS_SUCCESS;
171
172 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
173 Emios_Ip_axIpIsInitialized[Instance].runCore = ConfigPtr->instanceCoreNumber;
174 uint8 UserId = (uint8)OsIf_GetUserId();
175 if (Emios_Ip_axIpIsInitialized[Instance].runCore == UserId)
176 {
177 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
178 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == TRUE)
179 {
180 Status = EMIOS_IP_COMMON_STATUS_FAIL;
181 }
182 else
183 {
184 /* Initialization of EMIOS instance specific parameters. */
185 Base->MCR &= ~eMIOS_MCR_GPREN_MASK;
186 Base->MCR = eMIOS_MCR_GPRE(ConfigPtr->emiosGlobalConfig->clkDivVal) | eMIOS_MCR_FRZ(((uint32)ConfigPtr->emiosGlobalConfig->allowDebugMode)) | \
187 eMIOS_MCR_GTBE(ConfigPtr->emiosGlobalConfig->enableGlobalTimeBase);
188
189 /* Initialization of EMIOS channel specific parameters. */
190 for (CurrentChannel = 0; CurrentChannel < ConfigPtr->channelsNumber; CurrentChannel++)
191 {
192 if ((*ConfigPtr->masterBusConfig)[CurrentChannel].allowDebugMode)
193 {
194 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK;
195 }
196
197 /* Set Cn UCPRE to divider. */
198 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*ConfigPtr->masterBusConfig)[CurrentChannel].masterBusPrescaler);
199
200 switch ((*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode)
201 {
202 case EMIOS_IP_MC_UP_COUNTER_START:
203 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
204 break;
205 case EMIOS_IP_MC_UP_COUNTER_END:
206 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
207 break;
208 case EMIOS_IP_MC_UP_DOWN_COUNTER:
209 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].B = 0;
210 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
211 break;
212 case EMIOS_IP_MCB_UP_COUNTER:
213 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
214 break;
215 case EMIOS_IP_MCB_UP_DOWN_COUNTER:
216 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
217 break;
218 default:
219 /* Do nothing. */
220 break;
221 }
222
223 /* Write CNT register with start offset value. */
224 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].CNT = (*ConfigPtr->masterBusConfig)[CurrentChannel].offsetStartValue;
225
226 /* Set mode Cn_MODE = mode. */
227 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_MODE((*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode);
228
229 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_UCPREN(1U);
230
231 /* Save current state of channel. */
232 Emios_Ip_axChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].counterMode = (*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode;
233 Emios_Ip_axChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].channelInitState = TRUE;
234 /* Save the period of master bus channel. */
235 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
236 Emios_Ip_ChPeriodMasterBus[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel] = (uint32)(*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
237 #else
238 Emios_Ip_ChPeriodMasterBus[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel] = (uint16)(*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
239 #endif
240 }
241
242 /* Save current state of the instance. */
243 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = TRUE;
244 }
245
246 Base->MCR |= eMIOS_MCR_GPREN_MASK;
247
248 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
249 }
250 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
251
252 return Status;
253 }
254
255 /** @implements Emios_Mcl_Ip_ComparatorTransferEnable_Activity */
Emios_Mcl_Ip_ComparatorTransferEnable(uint8 Instance,uint32 ChannelMask)256 void Emios_Mcl_Ip_ComparatorTransferEnable(uint8 Instance, uint32 ChannelMask)
257 {
258 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
259 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
260 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL);
261 #endif
262
263 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
264 /* Update enable. */
265 Base->OUDIS &= ~(ChannelMask);
266 }
267
268 /** @implements Emios_Mcl_Ip_ComparatorTransferDisable_Activity */
Emios_Mcl_Ip_ComparatorTransferDisable(uint8 Instance,uint32 ChannelMask)269 void Emios_Mcl_Ip_ComparatorTransferDisable(uint8 Instance, uint32 ChannelMask)
270 {
271 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
272 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
273 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL);
274 #endif
275
276 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
277 /* Disable channel output. */
278 Base->OUDIS |= ChannelMask;
279 }
280
281 /** @implements Emios_Mcl_Ip_Deinit_Activity */
Emios_Mcl_Ip_Deinit(uint8 Instance)282 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Deinit(uint8 Instance)
283 {
284 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
285 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
286 #endif
287
288 uint8 CurrentChannel;
289 Emios_Ip_CommonStatusType Status = EMIOS_IP_COMMON_STATUS_SUCCESS;
290 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
291
292 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
293 uint8 UserId = (uint8)OsIf_GetUserId();
294 if (Emios_Ip_axIpIsInitialized[Instance].runCore == UserId)
295 {
296 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
297 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == FALSE)
298 {
299 Status = EMIOS_IP_COMMON_STATUS_FAIL;
300 }
301 else
302 {
303 Base->MCR &= ~eMIOS_MCR_GPREN_MASK;
304 Base->MCR = eMIOS_MCR_GPRE(0U) | eMIOS_MCR_FRZ(0U) | eMIOS_MCR_GTBE(0U);
305
306 for (CurrentChannel = 0; CurrentChannel < eMIOS_CH_UC_UC_COUNT; CurrentChannel++)
307 {
308 if(Emios_Ip_axChState[Instance][CurrentChannel].channelInitState == TRUE)
309 {
310 /* Disable channel pre-scaler (reset default) */
311 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].C = 0U;
312 /* Reset An and Bn registers */
313 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].A = 0UL;
314 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].B = 0UL;
315 /* Clear the period of master bus channel. */
316 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
317 Emios_Ip_ChPeriodMasterBus[Instance][CurrentChannel] = (uint32)0U;
318 #else
319 Emios_Ip_ChPeriodMasterBus[Instance][CurrentChannel] = (uint16)0U;
320 #endif
321 Emios_Ip_axChState[Instance][CurrentChannel].channelInitState = FALSE;
322 }
323 }
324 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = FALSE;
325 }
326 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
327 }
328 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
329
330 return Status;
331 }
332
333 /** @implements Emios_Mcl_Ip_SetReloadInterval_Activity */
Emios_Mcl_Ip_SetReloadInterval(uint8 HwInstance,uint8 HwChannel,uint8 Interval)334 void Emios_Mcl_Ip_SetReloadInterval(uint8 HwInstance, uint8 HwChannel, uint8 Interval)
335 {
336 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
337 DevAssert((uint8)31 > Interval);
338 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT);
339 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
340 #endif
341 /* Specifies the delay interval, in counter bus reload events, between each assertion
342 * of AS1-BS1 reload in MC and MCB modes. */
343 Emios_Ip_paxBase[HwInstance]->CH.UC[HwChannel].C2 = eMIOS_C2_UCRELDEL_INT(Interval);
344 }
345
346 /** @implements Emios_Mcl_Ip_ValidateChannel_Activity */
Emios_Mcl_Ip_ValidateChannel(uint8 HwInstance,uint8 HwChannel)347 boolean Emios_Mcl_Ip_ValidateChannel(uint8 HwInstance, uint8 HwChannel)
348 {
349 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
350 /* Check input parameter*/
351 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT);
352 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
353 #endif
354 boolean Valid = FALSE;
355
356 if (TRUE == Emios_Ip_axChState[HwInstance][HwChannel].channelInitState)
357 {
358 Valid = TRUE;
359 }
360 return Valid;
361 }
362
363 /** @implements Emios_Mcl_Ip_SetCounterBusPeriod_Activity */
Emios_Mcl_Ip_SetCounterBusPeriod(uint8 HwInstance,uint8 HwChannel,uint32 Period)364 Emios_Ip_CommonStatusType Emios_Mcl_Ip_SetCounterBusPeriod(uint8 HwInstance, uint8 HwChannel, uint32 Period)
365 {
366 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
367 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
368 DevAssert((uint32)16777215 > Period);
369 #else
370 DevAssert((uint32)65535 > Period);
371 #endif
372 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT);
373 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
374 #endif
375 Emios_Ip_CommonStatusType Status = EMIOS_IP_COMMON_STATUS_FAIL;
376
377 if (((Emios_Ip_axChState[HwInstance][HwChannel].counterMode == EMIOS_IP_MCB_UP_COUNTER) || \
378 (Emios_Ip_axChState[HwInstance][HwChannel].counterMode == EMIOS_IP_MCB_UP_DOWN_COUNTER)) && \
379 (Period < 1U))
380 {
381 Status = EMIOS_IP_COMMON_STATUS_FAIL;
382 }
383 else
384 {
385 Emios_Ip_paxBase[HwInstance]->CH.UC[HwChannel].A = Period;
386 /* Store the new period */
387 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
388 Emios_Ip_ChPeriodMasterBus[HwInstance][HwChannel] = Period;
389 #else
390 Emios_Ip_ChPeriodMasterBus[HwInstance][HwChannel] = (uint16)Period;
391 #endif
392 Status = EMIOS_IP_COMMON_STATUS_SUCCESS;
393 }
394 return Status;
395 }
396
397
398 /** @implements Emios_Mcl_Ip_GetCounterBusPeriod_Activity */
399 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance,uint8 Channel)400 uint32 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel)
401 #else
402 uint16 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel)
403 #endif
404 {
405 #if (EMIOS_MCL_IP_DEV_ERROR_DETECT == STD_ON)
406 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
407 DevAssert(Channel < eMIOS_CH_UC_UC_COUNT);
408 #endif
409 /* Get period of counter bus channels. */
410 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
411 uint32 PeriodCounterBus = Emios_Ip_ChPeriodMasterBus[Instance][Channel];
412 #else
413 uint16 PeriodCounterBus = Emios_Ip_ChPeriodMasterBus[Instance][Channel];
414 #endif
415
416 return PeriodCounterBus;
417 }
418
419 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
420 /** @implements Emios_Mcl_Ip_ValidateMultiCoreInit_Activity */
Emios_Mcl_Ip_ValidateMultiCoreInit(uint8 HwInstance)421 boolean Emios_Mcl_Ip_ValidateMultiCoreInit(uint8 HwInstance)
422 {
423 boolean Valid = FALSE;
424 uint8 UserId = (uint8)OsIf_GetUserId();
425
426 if (Emios_Ip_axIpIsInitialized[HwInstance].runCore == UserId)
427 {
428 Valid = TRUE;
429 }
430
431 return Valid;
432 }
433 #endif
434
Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance,uint8 Value)435 void Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance, uint8 Value)
436 {
437 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
438 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
439 DevAssert(((uint8)STD_ON == Value)||((uint8)STD_OFF == Value));
440 #endif
441
442 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
443 /* Configure GTBE bit. */
444 if ((uint8)STD_ON == Value)
445 {
446 Base->MCR |= eMIOS_MCR_GTBE_MASK;
447 }
448 else
449 {
450 Base->MCR &= (~eMIOS_MCR_GTBE_MASK);
451 }
452 }
453
454 /** @implements Emios_Mcl_Ip_SetClockMode_Activity */
Emios_Mcl_Ip_SetClockMode(uint8 Instance,const Emios_Mcl_Ip_ConfigType * const ConfigPtr,Emios_Ip_SelectPrescalerType Prescaler)455 void Emios_Mcl_Ip_SetClockMode(uint8 Instance, const Emios_Mcl_Ip_ConfigType* const ConfigPtr, Emios_Ip_SelectPrescalerType Prescaler)
456 {
457 uint8 CurrentChannel;
458 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
459 uint32 reg;
460
461 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
462 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
463 DevAssert(ConfigPtr != NULL_PTR);
464 #endif
465
466 for (CurrentChannel = 0U; CurrentChannel < ConfigPtr->channelsNumber; CurrentChannel++)
467 {
468 reg = Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2;
469 if (EMIOS_IP_PRESCALER == Prescaler)
470 {
471 /* Set Cn UCPRE to divider. */
472 reg = ((reg & (~(eMIOS_C2_UCEXTPRE_MASK))) | (eMIOS_C2_UCEXTPRE((*ConfigPtr->masterBusConfig)[CurrentChannel].masterBusPrescaler)));
473 }
474 else
475 {
476 /* Set Cn UCPRE to divider. */
477 reg = ((reg & (~(eMIOS_C2_UCEXTPRE_MASK))) | (eMIOS_C2_UCEXTPRE((*ConfigPtr->masterBusConfig)[CurrentChannel].masterBusAltPrescaler)));
478 }
479 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 = reg;
480 }
481 }
482
483 #define MCL_STOP_SEC_CODE
484 #include "Mcl_MemMap.h"
485
486 #ifdef __cplusplus
487 }
488 #endif
489
490 /** @} */
491
